GB1309502A - Semiconductor device and method of making the same - Google Patents
Semiconductor device and method of making the sameInfo
- Publication number
- GB1309502A GB1309502A GB3321971A GB3321971A GB1309502A GB 1309502 A GB1309502 A GB 1309502A GB 3321971 A GB3321971 A GB 3321971A GB 3321971 A GB3321971 A GB 3321971A GB 1309502 A GB1309502 A GB 1309502A
- Authority
- GB
- United Kingdom
- Prior art keywords
- type
- region
- ring
- diffused
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
- H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
- H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/67—Complementary BJTs
- H10D84/673—Vertical complementary BJTs
-
- H10W10/031—
-
- H10W10/30—
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
1309502 Semi-conductor devices SONY CORP 15 July 1971 [16 July 1970] 33219/71 Heading H1K In an IC two superposed epitaxial layers of the same conductivity type formed on a substrate of the opposite conductivity type are subdivided into two sections by an isolating wall of the same conductivity type of the substrate, a first transistor formed in one section having a buried layer of the same conductivity type as the epitaxial layers arranged between the lower epitaxial layer and the substrate, and a second transistor formed in the other section and having a buried layer of the same conductivity type as the substrate arranged between the two epitaxial layers. As shown, Fig. 1D, a P<SP>+</SP> type ring 3 and an N<SP>+</SP> type region 2 are diffused into a P-type wafer 1, an N-type epitaxial layer 4 is deposited, a second P<SP>+</SP> type ring 5 is diffused above the first ring 3, a P+ type region 6 is diffused into the layer outside ring 5 and a small N+ type region 26 is diffused within ring 5, a second N-type epitaxial layer is deposited, two P+ type rings 9, 13 are diffused-in one above rings 3 and 5 and the other above the region 6, and the structure is then heated to redistribute the impurities so that the rings join up to form isolation walls surrounding N-type islands 11, 14. An NPN transistor is formed in island 11 by diffusing-in a P-type base region (15) and N<SP>+</SP> type emitter and collector contact regions (16, 17). A PNP transistor is formed using island 14 as part of the base region by diffusing-in an N<SP>+</SP> type base region (18) within which is diffused a P-type emitter region (19), the buried region 6 and ring 13 forming the collector region. The N+ type emitter and collector regions of the NPN transistor and the base region of the PNP transistor are formed by a single diffusion step. In a modification, Fig. 2 (not shown), the initial isolation rings are extended to enclose both islands in a figure-8 configuration and the portion containing the P+ type buried layer is processed to form an FET by diffusing a P-type gate region diametrically across the contacting P+ type ring and diffusing in N+ type source and drain regions. These P-type and N<SP>+</SP> type are formed simultaneously with the base and emitter regions of an NPN bipolar transistor formed in the other island.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP45062437A JPS50278B1 (en) | 1970-07-16 | 1970-07-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1309502A true GB1309502A (en) | 1973-03-14 |
Family
ID=13200155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB3321971A Expired GB1309502A (en) | 1970-07-16 | 1971-07-15 | Semiconductor device and method of making the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS50278B1 (en) |
| CA (1) | CA936624A (en) |
| GB (1) | GB1309502A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2543739A1 (en) * | 1983-03-30 | 1984-10-05 | Radiotechnique Compelec | METHOD FOR MAKING A HIGH VOLTAGE BIPOLAR TRANSISTOR |
| CN118091384A (en) * | 2024-04-29 | 2024-05-28 | 杭州广立微电子股份有限公司 | SDB isolation test structure generation method, SDB isolation test structure and storage medium |
-
1970
- 1970-07-16 JP JP45062437A patent/JPS50278B1/ja active Pending
-
1971
- 1971-07-15 GB GB3321971A patent/GB1309502A/en not_active Expired
- 1971-07-15 CA CA118326A patent/CA936624A/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2543739A1 (en) * | 1983-03-30 | 1984-10-05 | Radiotechnique Compelec | METHOD FOR MAKING A HIGH VOLTAGE BIPOLAR TRANSISTOR |
| EP0126499A1 (en) * | 1983-03-30 | 1984-11-28 | Rtc-Compelec | Process for making a high-voltage bipolar transistor |
| CN118091384A (en) * | 2024-04-29 | 2024-05-28 | 杭州广立微电子股份有限公司 | SDB isolation test structure generation method, SDB isolation test structure and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CA936624A (en) | 1973-11-06 |
| JPS50278B1 (en) | 1975-01-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |