GB1368190A - Monolithic integrated circuit - Google Patents

Abstract

1368190 Semi-conductor devices SONY CORP 28 Sept 1972 [30 Sept 1971] 44882/72 Heading H1K A pair of complementary vertical transistors are formed in an integrated circuit by dividing a pair of opposite conductivity type epitaxial layers on a substrate of the opposite type to the lower layer into device areas by means of concentric isolating rings extending through the individual epitaxial layers and utilizing the two epitaxial layers and a diffused emitter region as a transistor in one isolated device area and the upper epitaxial layer and diffused base and emitter regions as a complementary transistor in another device area. As shown, an N type Si substrate 1 is provided with a first epitaxial layer 2 comprising a P+ type portion 2A and a P type portion 2B. An SiO 2 layer (5) is used as a mask for the diffusion of P to form N + type isolating rings 4, in the form of a chain, through the epitaxial layer 2 and a diffusion of As is used to produce an N + type buried layer 6 in one of the isolated regions. The SiO 2 layer is removed, and N type epitaxial layer 7 is deposited and individual P+ type isolating rings 9A, 9B, 9B concentric with rings 4 are diffused through the layer 7 using a second SiO 2 masking layer 11. An NPN transistor 10 is formed in the isolated area containing the buried layer 6 by diffusing- in a P type base region 10b and N + type emitter and collector contact regions 10e, 10c<SP>1</SP>. The part 10c of the top epitaxial layer 7 forms the collector region. A PNP transistor 12 is formed in a second isolated area by diffusing-in a P type emitter region 12e and an N+ type base contact region 12b<SP>1</SP>. The parts 12b and 12c of the two epitaxial layers form the base and collector regions respectively and the collector region is contacted via the P+ type isolating ring 9B. A JUGFET 14 is formed in a further isolated area by diffusing-in a P type upper gate 13g 2 and N + type source and drain regions 15s, 15d. The isolated part of the top epitaxial layer forms the channel region and the part 13g 1 of the lower epitaxial layer forms the lower gate region to which contact is made via the P + type isolating ring 9C. The P type regions 10b, 12e and 13g 2 may be formed simultaneously as can the N+ type regions 10e, 10c<SP>1</SP>, 15s and 15d. Electrodes are applied by vapour deposition and photo-etching. The lower face of the wafer is mechanically or chemically planed down and an electrode 19 is deposited which in use is connected to the highest fixed potential of the circuit to ensure that the isolating junctions are reverse biased.