GB1391560A - Bistable circuit and alarm annunciator - Google Patents

Abstract

1391560 Alarm systems HIGHLAND ELECTRONICS Ltd 29 Dec 1972 60183/72 Heading G4N [Also in Division H3] A bi-stable is formed by cross-coupling the output transistors (T2) and input transistors (T1) of similar logic gates (Fig. 2, not shown) so that the output transistors (T2) draw current from the supply only through the associated input transistor (T1); and the couplings contain time constants RC to temporarily memorize the bi-stable state during short power failures, and to reduce sensitivity to transients. The gates may be simple inverters, or multi-emitter input transistors (T1) may be used to perform NAND or NOR logic. Such bi-stables are used in 10, 12 Fig. 5, in an alarm annunciator. In the alarm annunciator Figs. 4, 5 lamps L1, L2 and a horn 61 are operated by an alarm emit 6 detailed in Fig. 5, in response to operation of contacts A.C. by an unspecified fault condition. The contacts A.C. control a pulse shaper 8 whose output or inverted output is selected by a switch 17 and fed to a mode selector circuit 9. A switch 24 therein selects locked (responsive to momentary faults) or non-locked operation, and a switch 27 selects manual or automatic reset. The latter provides automatic reset of the system when a fault is cleared, and manual reset is effected by an input signal r on line 47a generated in a control unit 1, Fig. 4; (and Fig. 8, not shown) in response to an operator's switch 47c. In the mode selector 9 NAND gates 19 to 22 permit the introduction from the control unit (Fig. 8, not shown) of a function test signal FT which mimics a fault condition, and of an inhibit signal I which resets the alarm system at initial switch on. A bi-stable 10, according to the invention, responds to the alarm signal from 9 and sends a signal to an "accept" circuit 11 and a second similar bi-stable 12 which drives a lamp control circuit 13 and a horn drive signal generator 36. The horn signal H goes to a horn drive circuit (53, Fig. 8, not shown) and the lamp control circuit 13 supplies to T4, T5 and lamps L1, L2 in circuit 14 the output X of an oscillator (52, Fig. 8, not shown). The lamps thus flash on and off to signal an alarm, until an operator-controlled "acknowledge" switch (46) sends a signal a to the above mentioned "accept" circuit 11 whereupon the lamps are held full on and the horn stopped, by the circuit 13. When the fault is cleared T5 is turned off by the output of NAND 19, and L2 glows dimly and L1 brightly. When the circuit is reset, both L1 and L2 go off. The "accept" circuit 11 is also made responsive to a (delayed) priority signal DP on line 11a (from Fig. 10, not shown), which controls the response of the alarm system when a group of different alarm units each as in Fig. 5 is used. A group repeater and associated lamp 3, Fig. 4, are also responsive to different priority signals from the different alarm units. A horn cancel unit 5, Fig. 4, and (Fig. 7, not shown) stop the horn in response to a switch (50) on the control unit (Fig. 8, not shown) and a "clear" horn is sounded by a unit 4, Fig. 4 (and Fig. 11, not shown) when all fault conditions have returned to normal.