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FR3049761B1 - Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel - Google Patents

Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel Download PDF

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Publication number
FR3049761B1
FR3049761B1 FR1652768A FR1652768A FR3049761B1 FR 3049761 B1 FR3049761 B1 FR 3049761B1 FR 1652768 A FR1652768 A FR 1652768A FR 1652768 A FR1652768 A FR 1652768A FR 3049761 B1 FR3049761 B1 FR 3049761B1
Authority
FR
France
Prior art keywords
substrate
layer
manufacturing
forming
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1652768A
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English (en)
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FR3049761A1 (fr
Inventor
Christophe Figuet
Ludovic Ecarnot
Bich-Yen Nguyen
Walter Schwarzenbach
Daniel Delprat
Ionut Radu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1652768A priority Critical patent/FR3049761B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to TW106111032A priority patent/TWI717491B/zh
Priority to CN201780021471.2A priority patent/CN109075036B/zh
Priority to EP17715662.7A priority patent/EP3437121B1/fr
Priority to KR1020187031346A priority patent/KR102323616B1/ko
Priority to US16/086,275 priority patent/US11205702B2/en
Priority to PCT/EP2017/057717 priority patent/WO2017167976A1/fr
Priority to SG11201808193SA priority patent/SG11201808193SA/en
Publication of FR3049761A1 publication Critical patent/FR3049761A1/fr
Application granted granted Critical
Publication of FR3049761B1 publication Critical patent/FR3049761B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10W20/01—
    • H10P10/128—
    • H10P50/642—
    • H10P95/04—
    • H10W90/00—
    • H10W72/07331—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Fuses (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une structure comprenant un premier substrat (1) comprenant au moins un composant électronique (10) susceptible d'être endommagé par une température supérieure à 400°C et une couche semi-conductrice s'étendant sur ledit premier substrat, caractérisé en ce qu'il comprend les étapes suivantes : (a) la fourniture d'une première couche métallique (11) de collage sur le premier substrat (1), (b) la fourniture d'un second substrat (2) comprenant successivement : - un substrat de base (20) semi-conducteur, - un empilement (21) d'une pluralité de couches épitaxiales semi-conductrices, une couche (210) de SixGe1-x, avec 0 ≤ x ≤ 1 étant située à la surface dudit empilement (21) opposée au substrat de base (20), - une seconde couche métallique (22) de collage, (c) le collage du premier substrat et du second substrat par l'intermédiaire des première et seconde couches métalliques (11, 22) de collage, (d) l'enlèvement d'une partie du second substrat de sorte à transférer la couche (210) de SixGe1-x sur le premier substrat (1), ledit enlèvement comprenant au moins une gravure sélective d'une couche du second substrat (2).
FR1652768A 2016-03-31 2016-03-31 Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel Active FR3049761B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1652768A FR3049761B1 (fr) 2016-03-31 2016-03-31 Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel
CN201780021471.2A CN109075036B (zh) 2016-03-31 2017-03-31 用于形成三维单片集成电路的结构的制造方法
EP17715662.7A EP3437121B1 (fr) 2016-03-31 2017-03-31 Procédé de fabrication d'une structure destinée à former un circuit intégré monolithique tridimensionnel
KR1020187031346A KR102323616B1 (ko) 2016-03-31 2017-03-31 3차원 모놀리식 집적 회로를 형성하기 위한 구조물을 제조하는 방법
TW106111032A TWI717491B (zh) 2016-03-31 2017-03-31 用於製造用以形成三維單片積體電路之結構的方法
US16/086,275 US11205702B2 (en) 2016-03-31 2017-03-31 Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit
PCT/EP2017/057717 WO2017167976A1 (fr) 2016-03-31 2017-03-31 Procédé de fabrication d'une structure destinée à former un circuit intégré monolithique tridimensionnel
SG11201808193SA SG11201808193SA (en) 2016-03-31 2017-03-31 Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1652768A FR3049761B1 (fr) 2016-03-31 2016-03-31 Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel
FR1652768 2016-03-31

Publications (2)

Publication Number Publication Date
FR3049761A1 FR3049761A1 (fr) 2017-10-06
FR3049761B1 true FR3049761B1 (fr) 2018-10-05

Family

ID=58009868

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1652768A Active FR3049761B1 (fr) 2016-03-31 2016-03-31 Procede de fabrication d'une structure pour former un circuit integre monolithique tridimensionnel

Country Status (8)

Country Link
US (1) US11205702B2 (fr)
EP (1) EP3437121B1 (fr)
KR (1) KR102323616B1 (fr)
CN (1) CN109075036B (fr)
FR (1) FR3049761B1 (fr)
SG (1) SG11201808193SA (fr)
TW (1) TWI717491B (fr)
WO (1) WO2017167976A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102607828B1 (ko) * 2021-05-28 2023-11-29 아주대학교산학협력단 모놀리식 3차원 집적 회로 및 이의 제조 방법
KR102596333B1 (ko) 2021-11-16 2023-10-31 재단법인대구경북과학기술원 모놀리식 3차원 집적 구조, 및 이의 제조 방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
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US5414276A (en) * 1993-10-18 1995-05-09 The Regents Of The University Of California Transistors using crystalline silicon devices on glass
US7052941B2 (en) * 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
KR100442105B1 (ko) * 2001-12-03 2004-07-27 삼성전자주식회사 소이형 기판 형성 방법
KR101003542B1 (ko) * 2008-10-14 2010-12-30 이상윤 3차원 반도체 장치의 제조 방법 및 이에 따라 제조된 3차원반도체 장치
FR2864336B1 (fr) 2003-12-23 2006-04-28 Commissariat Energie Atomique Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci
US20050280081A1 (en) * 2004-06-16 2005-12-22 Massachusetts Institute Of Technology Semiconductor devices having bonded interfaces and methods for making the same
FR2880189B1 (fr) * 2004-12-24 2007-03-30 Tracit Technologies Sa Procede de report d'un circuit sur un plan de masse
FR2922359B1 (fr) 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
GB2467934B (en) 2009-02-19 2013-10-30 Iqe Silicon Compounds Ltd Photovoltaic cell
FR2950734B1 (fr) * 2009-09-28 2011-12-09 Soitec Silicon On Insulator Procede de collage et de transfert d'une couche
US8742476B1 (en) * 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US8405201B2 (en) * 2009-11-09 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure
CN102668098B (zh) * 2009-12-28 2015-07-22 株式会社半导体能源研究所 制造半导体装置的方法
US7935612B1 (en) 2010-02-05 2011-05-03 International Business Machines Corporation Layer transfer using boron-doped SiGe layer
KR101913322B1 (ko) 2010-12-24 2018-10-30 퀄컴 인코포레이티드 반도체 소자들을 위한 트랩 리치 층
CN103208472B (zh) * 2012-01-12 2016-03-02 稳懋半导体股份有限公司 具有三维元件的复合物半导体集成电路
SG11201407282XA (en) * 2012-07-31 2015-01-29 Univ Nanyang Tech Semiconductor device and method for forming the same
KR20140113151A (ko) * 2013-03-15 2014-09-24 삼성전자주식회사 금속 접합층 형성방법 및 그를 이용한 반도체 발광소자 제조방법
FR3006236B1 (fr) * 2013-06-03 2016-07-29 Commissariat Energie Atomique Procede de collage metallique direct
US9299736B2 (en) * 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density

Also Published As

Publication number Publication date
US20200295138A1 (en) 2020-09-17
WO2017167976A1 (fr) 2017-10-05
EP3437121B1 (fr) 2022-05-11
KR20180132091A (ko) 2018-12-11
FR3049761A1 (fr) 2017-10-06
US11205702B2 (en) 2021-12-21
CN109075036A (zh) 2018-12-21
TWI717491B (zh) 2021-02-01
CN109075036B (zh) 2023-07-28
SG11201808193SA (en) 2018-10-30
KR102323616B1 (ko) 2021-11-08
EP3437121A1 (fr) 2019-02-06
TW201802881A (zh) 2018-01-16

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