FR2847077B1 - Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation - Google Patents
Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisationInfo
- Publication number
- FR2847077B1 FR2847077B1 FR0214123A FR0214123A FR2847077B1 FR 2847077 B1 FR2847077 B1 FR 2847077B1 FR 0214123 A FR0214123 A FR 0214123A FR 0214123 A FR0214123 A FR 0214123A FR 2847077 B1 FR2847077 B1 FR 2847077B1
- Authority
- FR
- France
- Prior art keywords
- semiconductor components
- making same
- soi type
- mixed
- mixed soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/959—Mechanical polishing of wafer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0214123A FR2847077B1 (fr) | 2002-11-12 | 2002-11-12 | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation |
| AU2003294783A AU2003294783A1 (en) | 2002-11-12 | 2003-11-06 | Semiconductor structure, and methods for fabricating same |
| DE10393700.5T DE10393700B4 (de) | 2002-11-12 | 2003-11-06 | Verfahren zur Herstellung einer Halbleiteranordnung durch Ausbildung geschwächter Bereiche oder einer geschwächten Schicht und zugehöriges Halbleiterbauelement |
| KR1020057007871A KR100877252B1 (ko) | 2002-11-12 | 2003-11-06 | 반도체 구조 제조방법 |
| PCT/EP2003/013697 WO2004044975A1 (fr) | 2002-11-12 | 2003-11-06 | Structure semi-conductrice et procede de fabrication de cette structure |
| US10/704,703 US6955971B2 (en) | 2002-11-12 | 2003-11-12 | Semiconductor structure and methods for fabricating same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0214123A FR2847077B1 (fr) | 2002-11-12 | 2002-11-12 | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2847077A1 FR2847077A1 (fr) | 2004-05-14 |
| FR2847077B1 true FR2847077B1 (fr) | 2006-02-17 |
Family
ID=32116550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0214123A Expired - Lifetime FR2847077B1 (fr) | 2002-11-12 | 2002-11-12 | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6955971B2 (fr) |
| KR (1) | KR100877252B1 (fr) |
| AU (1) | AU2003294783A1 (fr) |
| DE (1) | DE10393700B4 (fr) |
| FR (1) | FR2847077B1 (fr) |
| WO (1) | WO2004044975A1 (fr) |
Families Citing this family (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006041422A (ja) | 2004-07-30 | 2006-02-09 | Seiko Epson Corp | 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法 |
| KR20070050988A (ko) * | 2004-09-02 | 2007-05-16 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 반도체 디바이스 및 그 제조 방법 |
| FR2875947B1 (fr) * | 2004-09-30 | 2007-09-07 | Tracit Technologies | Nouvelle structure pour microelectronique et microsysteme et procede de realisation |
| FR2876220B1 (fr) * | 2004-10-06 | 2007-09-28 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
| FR2876219B1 (fr) * | 2004-10-06 | 2006-11-24 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
| US20060094257A1 (en) * | 2004-11-04 | 2006-05-04 | Tower Semiconductor Ltd. | Low thermal budget dielectric stack for SONOS nonvolatile memories |
| FR2897982B1 (fr) | 2006-02-27 | 2008-07-11 | Tracit Technologies Sa | Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat |
| FR2910702B1 (fr) * | 2006-12-26 | 2009-04-03 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat mixte |
| WO2008114099A1 (fr) * | 2007-03-19 | 2008-09-25 | S.O.I.Tec Silicon On Insulator Technologies | Silicium sur isolant mince à motifs |
| TWI357108B (en) * | 2007-08-21 | 2012-01-21 | Nat Univ Tsing Hua | Semiconductor device structure |
| US8673163B2 (en) | 2008-06-27 | 2014-03-18 | Apple Inc. | Method for fabricating thin sheets of glass |
| FR2933233B1 (fr) * | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat de haute resistivite bon marche et procede de fabrication associe |
| FR2933234B1 (fr) * | 2008-06-30 | 2016-09-23 | S O I Tec Silicon On Insulator Tech | Substrat bon marche a structure double et procede de fabrication associe |
| US7810355B2 (en) | 2008-06-30 | 2010-10-12 | Apple Inc. | Full perimeter chemical strengthening of substrates |
| FR2933235B1 (fr) * | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat bon marche et procede de fabrication associe |
| FR2936357B1 (fr) * | 2008-09-24 | 2010-12-10 | Commissariat Energie Atomique | Procede de report de puces sur un substrat. |
| TWI451534B (zh) * | 2008-10-30 | 2014-09-01 | Corning Inc | 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置 |
| US8003491B2 (en) * | 2008-10-30 | 2011-08-23 | Corning Incorporated | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
| US9063605B2 (en) | 2009-01-09 | 2015-06-23 | Apple Inc. | Thin glass processing using a carrier |
| US7918019B2 (en) * | 2009-01-09 | 2011-04-05 | Apple Inc. | Method for fabricating thin touch sensor panels |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| WO2010101961A2 (fr) | 2009-03-02 | 2010-09-10 | Apple Inc. | Techniques de renforcement de protections en verre pour dispositifs électroniques portables |
| US9778685B2 (en) | 2011-05-04 | 2017-10-03 | Apple Inc. | Housing for portable electronic device with reduced border region |
| US9213451B2 (en) | 2010-06-04 | 2015-12-15 | Apple Inc. | Thin glass for touch panel sensors and methods therefor |
| US10189743B2 (en) | 2010-08-18 | 2019-01-29 | Apple Inc. | Enhanced strengthening of glass |
| US8824140B2 (en) | 2010-09-17 | 2014-09-02 | Apple Inc. | Glass enclosure |
| US8950215B2 (en) | 2010-10-06 | 2015-02-10 | Apple Inc. | Non-contact polishing techniques for reducing roughness on glass surfaces |
| KR101867385B1 (ko) * | 2010-10-15 | 2018-06-15 | 어플라이드 머티어리얼스, 인코포레이티드 | 광학 모니터링을 위한 스펙트럼들의 라이브러리 구축 |
| JP5454485B2 (ja) * | 2011-02-09 | 2014-03-26 | 信越半導体株式会社 | 貼り合わせ基板の製造方法 |
| FR2972564B1 (fr) | 2011-03-08 | 2016-11-04 | S O I Tec Silicon On Insulator Tech | Procédé de traitement d'une structure de type semi-conducteur sur isolant |
| US10781135B2 (en) | 2011-03-16 | 2020-09-22 | Apple Inc. | Strengthening variable thickness glass |
| US9725359B2 (en) | 2011-03-16 | 2017-08-08 | Apple Inc. | Electronic device having selectively strengthened glass |
| US9128666B2 (en) | 2011-05-04 | 2015-09-08 | Apple Inc. | Housing for portable electronic device with reduced border region |
| KR20130017914A (ko) * | 2011-08-12 | 2013-02-20 | 삼성전자주식회사 | 광전 집적회로 기판 및 그 제조방법 |
| US9944554B2 (en) | 2011-09-15 | 2018-04-17 | Apple Inc. | Perforated mother sheet for partial edge chemical strengthening and method therefor |
| US9516149B2 (en) | 2011-09-29 | 2016-12-06 | Apple Inc. | Multi-layer transparent structures for electronic device housings |
| US10144669B2 (en) | 2011-11-21 | 2018-12-04 | Apple Inc. | Self-optimizing chemical strengthening bath for glass |
| US10133156B2 (en) | 2012-01-10 | 2018-11-20 | Apple Inc. | Fused opaque and clear glass for camera or display window |
| US8773848B2 (en) | 2012-01-25 | 2014-07-08 | Apple Inc. | Fused glass device housings |
| US9946302B2 (en) | 2012-09-19 | 2018-04-17 | Apple Inc. | Exposed glass article with inner recessed area for portable electronic device housing |
| KR102007258B1 (ko) * | 2012-11-21 | 2019-08-05 | 삼성전자주식회사 | 광전 집적회로 기판의 제조방법 |
| US9459661B2 (en) | 2013-06-19 | 2016-10-04 | Apple Inc. | Camouflaged openings in electronic device housings |
| CN104752311B (zh) * | 2013-12-27 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | 一种绝缘体上硅衬底及其制造方法 |
| US9886062B2 (en) | 2014-02-28 | 2018-02-06 | Apple Inc. | Exposed glass article with enhanced stiffness for portable electronic device housing |
| CN106252219A (zh) * | 2016-07-29 | 2016-12-21 | 浙江大学 | 一种制备高平整度绝缘层上半导体结构的方法 |
| FR3086096B1 (fr) * | 2018-09-14 | 2021-08-27 | Soitec Silicon On Insulator | Procede de realisation d'un substrat avance pour une integration hybride |
| CN114724934A (zh) * | 2021-01-06 | 2022-07-08 | 格科微电子(上海)有限公司 | 半导体材料的键合方法及键合结构 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5238865A (en) * | 1990-09-21 | 1993-08-24 | Nippon Steel Corporation | Process for producing laminated semiconductor substrate |
| US5091330A (en) * | 1990-12-28 | 1992-02-25 | Motorola, Inc. | Method of fabricating a dielectric isolated area |
| JP3174786B2 (ja) * | 1991-05-31 | 2001-06-11 | 富士通株式会社 | 半導体装置の製造方法 |
| JPH05190657A (ja) * | 1992-01-16 | 1993-07-30 | Fujitsu Ltd | 半導体基板およびその製造方法 |
| US5436173A (en) * | 1993-01-04 | 1995-07-25 | Texas Instruments Incorporated | Method for forming a semiconductor on insulator device |
| US5364800A (en) * | 1993-06-24 | 1994-11-15 | Texas Instruments Incorporated | Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate |
| JP3427114B2 (ja) | 1994-06-03 | 2003-07-14 | コマツ電子金属株式会社 | 半導体デバイス製造方法 |
| EP0701286B1 (fr) * | 1994-06-16 | 1999-11-24 | Nec Corporation | Substrat à silicium sur isolateur et procédé de sa fabrication |
| US6043166A (en) | 1996-12-03 | 2000-03-28 | International Business Machines Corporation | Silicon-on-insulator substrates using low dose implantation |
| JPH1174531A (ja) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JPH11145481A (ja) * | 1997-11-06 | 1999-05-28 | Denso Corp | 半導体基板およびその製造方法 |
| KR100273281B1 (ko) | 1998-02-27 | 2000-12-15 | 김영환 | 반도체 소자의 절연막 형성 방법 |
| JP3194370B2 (ja) * | 1998-05-11 | 2001-07-30 | 日本電気株式会社 | 半導体装置とその製造方法 |
| AU2993600A (en) | 1999-02-12 | 2000-08-29 | Ibis Technology Corporation | Patterned silicon-on-insulator devices |
| US5950094A (en) | 1999-02-18 | 1999-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating fully dielectric isolated silicon (FDIS) |
| JP2000349148A (ja) * | 1999-06-08 | 2000-12-15 | Sony Corp | 半導体層を有する基板の製造方法 |
| US6333532B1 (en) * | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
| US6583011B1 (en) * | 2000-01-11 | 2003-06-24 | Chartered Semiconductor Manufacturing Ltd. | Method for forming damascene dual gate for improved oxide uniformity and control |
| TW476993B (en) * | 2000-01-19 | 2002-02-21 | Advanced Micro Devices Inc | Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same |
| US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| JP4437352B2 (ja) * | 2000-02-29 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2001274368A (ja) * | 2000-03-27 | 2001-10-05 | Shin Etsu Handotai Co Ltd | 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ |
| JP2001351987A (ja) * | 2000-06-09 | 2001-12-21 | Nec Corp | 半導体装置の製造方法 |
| JP3998408B2 (ja) * | 2000-09-29 | 2007-10-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP2002124652A (ja) * | 2000-10-16 | 2002-04-26 | Seiko Epson Corp | 半導体基板の製造方法、半導体基板、電気光学装置並びに電子機器 |
| JP2002299591A (ja) * | 2001-03-30 | 2002-10-11 | Toshiba Corp | 半導体装置 |
| FR2823596B1 (fr) * | 2001-04-13 | 2004-08-20 | Commissariat Energie Atomique | Substrat ou structure demontable et procede de realisation |
-
2002
- 2002-11-12 FR FR0214123A patent/FR2847077B1/fr not_active Expired - Lifetime
-
2003
- 2003-11-06 AU AU2003294783A patent/AU2003294783A1/en not_active Abandoned
- 2003-11-06 DE DE10393700.5T patent/DE10393700B4/de not_active Expired - Lifetime
- 2003-11-06 KR KR1020057007871A patent/KR100877252B1/ko not_active Expired - Lifetime
- 2003-11-06 WO PCT/EP2003/013697 patent/WO2004044975A1/fr not_active Ceased
- 2003-11-12 US US10/704,703 patent/US6955971B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| FR2847077A1 (fr) | 2004-05-14 |
| WO2004044975A1 (fr) | 2004-05-27 |
| DE10393700T5 (de) | 2005-09-15 |
| KR20050070116A (ko) | 2005-07-05 |
| US20040150067A1 (en) | 2004-08-05 |
| US6955971B2 (en) | 2005-10-18 |
| DE10393700B4 (de) | 2019-06-06 |
| KR100877252B1 (ko) | 2009-01-07 |
| AU2003294783A1 (en) | 2004-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| FR2847077B1 (fr) | Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation | |
| AU2003278428A1 (en) | SiGe GATE ELECTRODES ON SiGe SUBSTRATES AND METHODS OF MAKING THE SAME | |
| TWI371061B (en) | Semiconductor device and method of fabricating the same | |
| AU2003247798A1 (en) | Nozzles and components thereof and methods for making the same | |
| PT1296564E (pt) | Concentrado liquido para granizado e metodo para o fabrico do mesmo | |
| EP1485191A4 (fr) | Systemes microfluidiques en mode mixte | |
| BRPI0406565B1 (pt) | mistura de agente de suporte e mÉtodo para sua formaÇço. | |
| AU2003239560A1 (en) | Microwave field effect transistor structure | |
| SG116499A1 (en) | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures. | |
| FI20010797L (fi) | Menetelmä antennin virittämiseksi ja antenni | |
| FI20031814A7 (fi) | Menetelmä ja laite taajuusselektiiviseen keilanmuodostukseen | |
| AU2003291351A1 (en) | Semiconductor component and method of manufacture | |
| AU2003244417A1 (en) | Cellular mosfet devices and their manufacture | |
| ITTO20020724A1 (it) | Procedimento e sistema per la trasmissione di messaggi su | |
| DE60038323D1 (de) | Halbleiterkristall, dessen Herstellungsverfahren und Halbleiterbauelement | |
| GB2404283B (en) | Silicon-on-insulator transistor and method of manufacturing the same | |
| AU2003281740A1 (en) | Field effect transistor and method of manufacturing same | |
| AU2003207199A1 (en) | Structure, method of manufacturing the same, and device using the same | |
| EP1679089A4 (fr) | Membre anatomique et procede de realisation associe | |
| AU2002219550A1 (en) | Vegetable fiber-digesting agent and method of processing vegetable waste by using the same | |
| AU2003265862A1 (en) | Semiconductor component and method of manufacture | |
| DE60236994D1 (de) | Halbleiterbauelement und dessen Herstellungsverfahren | |
| AU2003290457A1 (en) | Flotation device and method of manufacturing the same | |
| EP1473774A4 (fr) | Dispositif semi-conducteur et procede de fabrication associe | |
| EP1363333A4 (fr) | Dispositif de semi-conducteurs et procede de fabrication associe |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120907 |
|
| PLFP | Fee payment |
Year of fee payment: 14 |
|
| PLFP | Fee payment |
Year of fee payment: 15 |
|
| PLFP | Fee payment |
Year of fee payment: 16 |
|
| PLFP | Fee payment |
Year of fee payment: 17 |
|
| PLFP | Fee payment |
Year of fee payment: 18 |
|
| PLFP | Fee payment |
Year of fee payment: 19 |
|
| PLFP | Fee payment |
Year of fee payment: 20 |