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ES402164A1 - A METHOD FOR MANUFACTURING SEMICONDUCTOR MONOLITHIC DEVICES. - Google Patents

A METHOD FOR MANUFACTURING SEMICONDUCTOR MONOLITHIC DEVICES.

Info

Publication number
ES402164A1
ES402164A1 ES402164A ES402164A ES402164A1 ES 402164 A1 ES402164 A1 ES 402164A1 ES 402164 A ES402164 A ES 402164A ES 402164 A ES402164 A ES 402164A ES 402164 A1 ES402164 A1 ES 402164A1
Authority
ES
Spain
Prior art keywords
substrate
epitaxic
layer
epitaxic layer
conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES402164A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES402164A1 publication Critical patent/ES402164A1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P32/15—
    • H10W10/031—
    • H10W10/30—
    • H10W15/00—
    • H10W15/01—

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method of manufacturing monolithic semiconductor devices, comprising the steps of: arranging a semiconductor substrate of a certain type of conductivity; introducing into said substrate, through some desired surface places, two impurities of different diffusion rates and of the other type of conductivity; on said substrate, forming an epitaxic layer of semiconductor material of the same type of conductivity as said substrate; subjecting said epitaxic layer and said substrate to a treatment whereby one of said impurities diffuses out completely through said epitaxic layer until reaching the surface of said epitaxic layer opposite to the interface between said epitaxic layer and said substrate; forming at one of said desired surface locations a bipolar transistor, fully comprised within the ruler of said epitaxic layer through which the first of said impurities has completely diffused outward, through said epitaxic layer, until reaching said surface of said epitaxic layer opposite to said interfacial zone; and forming a field effect transistor in said epitaxic layer, outside or outside of said region. (Machine-translation by Google Translate, not legally binding)
ES402164A 1971-04-28 1972-04-27 A METHOD FOR MANUFACTURING SEMICONDUCTOR MONOLITHIC DEVICES. Expired ES402164A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13816171A 1971-04-28 1971-04-28

Publications (1)

Publication Number Publication Date
ES402164A1 true ES402164A1 (en) 1975-03-01

Family

ID=22480723

Family Applications (2)

Application Number Title Priority Date Filing Date
ES402164A Expired ES402164A1 (en) 1971-04-28 1972-04-27 A METHOD FOR MANUFACTURING SEMICONDUCTOR MONOLITHIC DEVICES.
ES402165A Expired ES402165A1 (en) 1971-04-28 1972-04-27 A MONOLITHIC SEMICONDUCTOR DEVICE.

Family Applications After (1)

Application Number Title Priority Date Filing Date
ES402165A Expired ES402165A1 (en) 1971-04-28 1972-04-27 A MONOLITHIC SEMICONDUCTOR DEVICE.

Country Status (12)

Country Link
JP (1) JPS5037507B1 (en)
AU (1) AU459156B2 (en)
CA (1) CA966231A (en)
CH (1) CH536029A (en)
DE (1) DE2219696C3 (en)
ES (2) ES402164A1 (en)
FR (1) FR2134360B1 (en)
GB (1) GB1358612A (en)
IT (1) IT947674B (en)
NL (1) NL7204804A (en)
SE (1) SE384949B (en)
ZA (1) ZA721782B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2608267A1 (en) * 1976-02-28 1977-09-08 Itt Ind Gmbh Deutsche METHOD OF MANUFACTURING A MONOLITHIC INTEGRATED CIRCUIT
JPS5851561A (en) * 1981-09-24 1983-03-26 Hitachi Ltd Semiconductor integrated circuit device
JPS58225663A (en) * 1982-06-23 1983-12-27 Toshiba Corp Manufacture of semiconductor device
JPS5955052A (en) * 1982-09-24 1984-03-29 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS59177960A (en) * 1983-03-28 1984-10-08 Hitachi Ltd Semiconductor device and manufacture thereof
IT1214808B (en) * 1984-12-20 1990-01-18 Ates Componenti Elettron TICO AND SEMICONDUCTOR PROCESS FOR THE FORMATION OF A BURIED LAYER AND OF A COLLECTOR REGION IN A MONOLI DEVICE
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
KR890004420B1 (en) * 1986-11-04 1989-11-03 삼성반도체통신 주식회사 Manufacturing method of bicmos device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293087A (en) * 1963-03-05 1966-12-20 Fairchild Camera Instr Co Method of making isolated epitaxial field-effect device
US3481801A (en) * 1966-10-10 1969-12-02 Frances Hugle Isolation technique for integrated circuits
US3479233A (en) * 1967-01-16 1969-11-18 Ibm Method for simultaneously forming a buried layer and surface connection in semiconductor devices
US3440503A (en) * 1967-05-31 1969-04-22 Westinghouse Electric Corp Integrated complementary mos-type transistor structure and method of making same
GB1280022A (en) * 1968-08-30 1972-07-05 Mullard Ltd Improvements in and relating to semiconductor devices

Also Published As

Publication number Publication date
CA966231A (en) 1975-04-15
CH536029A (en) 1973-04-15
ZA721782B (en) 1973-10-31
SE384949B (en) 1976-05-24
GB1358612A (en) 1974-07-03
IT947674B (en) 1973-05-30
NL7204804A (en) 1972-10-31
AU459156B2 (en) 1975-03-20
FR2134360A1 (en) 1972-12-08
FR2134360B1 (en) 1974-06-28
ES402165A1 (en) 1975-03-16
DE2219696B2 (en) 1978-04-06
JPS5037507B1 (en) 1975-12-03
DE2219696C3 (en) 1982-02-18
DE2219696A1 (en) 1972-11-16
AU4164272A (en) 1973-12-20

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