EP0296015B1 - Power line impedance testing appliance, and its use in a pyrotecnical device firing test - Google Patents

Description

The invention relates to a device for testing the impedance of a power line and its application to testing primers of pyrotechnic means with electric ignition.

There are many electronic circuits in which an electrical load must be able to be supplied under a high nominal current, for example from a few amps to a few tens of amps, via a power stage. If the impedance of the power line constituted by the serial connection of the power stage with the electrical load is too high, the source of electrical current or voltage will not always be able to circulate in the loads the nominal current or, at the very least, a minimum current capable of causing the effect sought by the supply of the load.

In a certain number of applications this defect can have serious consequences and it is advisable to ensure beforehand that the impedance of the power line does not exceed a predetermined value and, correlatively, that its electrical continuity is well ensured.

EP-A-0061 860 describes an apparatus and a method for testing a detonating module, the firing of which is ensured by supplying it with an alternating current of given intensity via a transformer.

The test current must also be alternating and of sufficient intensity to allow precise measurement of the impedance of the detonating module. A test under an alternating current of given frequency and constant amplitude would require an electrical power source of excessive capacity and size for a device supposed to be portable. The apparatus therefore includes a capacitor which, when testing a detonating module, is preloaded to a predetermined voltage. The discharge of the capacitor generates between the terminals of the transformer primary a voltage peak which is representative of the impedance of the detonating module.

However, the solution described in this document cannot be transposed to the test -----> of electric power lines -----> supplied with direct current. However, apart from any consideration of capacity or size of the electrical power source, it is not always possible to test a power line under a high direct current, either because the load is a consumable member (for example, the initiation of a pyrotechnic element), either because the direct or indirect effect (electrical, magnetic, thermal, mechanical, etc.) which would result therefrom is incompatible, for safety or other reasons, with the test conditions. On the other hand, the electrical charge cannot always be tested independently of the power stage, if only because of its inaccessibility.

These various constraints make it necessary to have a device making it possible to test under a low direct current the impedance of a power line comprising an electrical load connected to a power stage capable of supplying it with a current. high nominal continuous.

This need, and the difficulties encountered, will be illustrated in connection with the test of an electric fired cartridge primer. Such a primer comprises in known manner the assembly of an electrical charge, that is to say a heating resistor, and a small pyrotechnic pellet capable of detonating in the event of sufficient heating. It is noted that excessive heating, but less than the minimum heating causing the detonation, can gradually create a kind of chemical fatigue of the pellet, which then introduces drifts of its detonation characteristics relative to those it initially had. Such deterioration is hereinafter called "phlegmatization".

French patent application FR-A-2 611 883, filed on March 4, 1987 by the Applicant and published after the priority date of this application, describes a device and a method for the selective firing of cartridges for aircraft or other apparatus. This device includes modular chargers each containing several cartridges and electronic circuits ensuring the management of cartridge loading and the selective distribution of firing orders to the primers of the different cartridges. To this end, these circuits construct firing tables containing only the addresses of the cartridges whose firing line comprising a power stage and a primer is correct. Each line of fire must therefore have been tested during the initialization of the device and / or prior to the firing order of the cartridge.

FIG. 1 shows a simplified electrical circuit of the prior art forming part of the general knowledge of those skilled in the art, comprising a primer symbolized by a load resistor Rc, a power stage T2 consisting of two transistors mounted in Darlington circuit between a current supply source SC and the load Rc, and a switching transistor T1 allowing the selection of the firing line from the electronic circuits of the aforementioned selective firing device. The base of transistor T1 is attacked via a resistor Rb1, its emitter is connected to ground via a resistor Re and its collector is connected to the base of the Darlington circuit T2 via of a resistance Rb2.

$$\text{Vm = 2Vbe + Vcel + Rb2Ib2 + ReIe (circuit d'entrée)}$$

avec, Im étant l'intensité à la source SC : $$\text{Im = (βT2 + 1) Ib2}$$

$$\text{Ic = Im - Ib2}$$

$$\text{Ie = Ib1 + Ib2}$$

The impedance of the firing line can be determined by measuring the voltage Vm at its terminals when a direct test current Im is injected into it by the current source SC. We have : $$\text{Vm = Vr + Vce2 = RcIc + Vce2 (output circuit)}$$

$$\text{Vm = 2Vbe + Vcel + Rb2Ib2 + ReIe (input circuit)}$$

with, Im being the intensity at the source SC: $$\text{Im = (βT2 + 1) Ib2}$$

$$\text{Ic = Im - Ib2}$$

$$\text{Ie = Ib1 + Ib2}$$

βT2 being the current gain of the Darlington circuit.

$$\text{Vm (sortie) = Vce2sat + RccIc, d'où :}$$

$$\text{Rcc =}\frac{\text{2Vbe+Vce1sat+Rb2Ib2+Re(Ib1+Ib2)-Vce2sat}}{\text{Ic}}$$

For the measurement of Vm to be significant, its variations must be a function of the value of the resistance of the charge (primer) Rc. This means that the test (measurement of Vm) can only be done when the transistor T2 (Darlington circuit) is saturated. We then have: $$\text{Vm (input) = 2Vbe + Vce1sat + Rb2Ib2 + Re (Ib1 + Ib2)}$$

$$\text{Vm (output) = Vce2sat + RccIc, hence:}$$

$$\text{Rcc =}\frac{\text{2Vbe + Vce1sat + Rb2Ib2 + Re (Ib1 + Ib2) -Vce2sat}}{\text{Ic}}$$

Rcc being the value of the load resistance which, for a given current Ic, brings the transistor T2 to saturation.

Vce1sat = 0,1V

2VbcT2 = 1,2V

Vce2sat = 0,8V

βT2 = 100

   et dans cet exemple

le courant Ic traversant la charge est sensiblement égal à 50 mA.In a specific exemplary embodiment where a “1A1W 5 minutes fire-free” type primer is used, the maximum authorized test current enabling the phlegmatization of the primer to be avoided is a direct current of 50 mA. If the 2N2222A and BDX64C components are used for the T1 and T2 transistors, the characteristics provided by the manufacturers are as follows:

Vce1sat = 0.1V

2VbcT2 = 1.2V

Vce2sat = 0.8V

βT2 = 100

and in this example

the current Ic passing through the load is substantially equal to 50 mA.

If we transfer these values to expression 8, we obtain: Rcc # 10Ω.

However, the minimum current which must pass through a primer of the aforementioned type to ensure its ignition is 3A. If the available electrical voltage is 24V, we note that a firing channel can only be declared operational if the value of the firing line impedance is at most equal to 8 Ω.

The previous result allows to conclude that it will be impossible, under a direct current of 50 mA, to measure a value lower than 8 Ω for this type of assembly.

The invention aims to provide a device for testing a power line which overcomes this difficulty.

• des moyens générateurs de courant constant aptes à faire circuler dans chaque ligne un courant continu de test de faible valeur par rapport au courant nominal,
• un dipôle électrique connecté dans chaque ligne de puissance pour engendrer une tension de décalage sensiblement constante lorsque ladite ligne de puissance est parcourue par le courant continu de test ou le courant nominal, ladite tension de décalage s'ajoutant à la chute de tension aux bornes de la charge pour porter l'étage de puissance à saturation lorsque la charge est parcourue par le courant continu de test,
• des moyens de mesure de la chute de tension aux bornes de chaque ligne de puissance, et
• des moyens d'exploitation du résultat de ladite mesure de tension.

To this end, it relates to a DC test device for the impedance of at least one power line, each line comprising an electrical load connected to a power stage capable of supplying it with a nominal DC current. high, characterized in that it comprises:

• constant current generating means able to circulate in each line a direct test current of low value compared to the nominal current,
• an electrical dipole connected in each power line to generate a substantially constant offset voltage when said power line is traversed by the test direct current or the nominal current, said offset voltage being added to the voltage drop across the terminals of the load to bring the power stage to saturation when the load is traversed by the direct test current,
• means for measuring the voltage drop across each power line, and
• means for exploiting the result of said voltage measurement.

• la figure 1 est un schéma électrique d'un étage de puissance suivant l'état de la technique ;
• la figure 2 est un schéma analogue à celui de la figure 1 représentant un étage de puissance modifié conformément à l'invention ;
• la figure 3 est un graphique illustrant l'effet original obtenu au moyen du circuit modifié de la figure 2 ;
• la figure 4A est un schéma synoptique d'un dispositif permettant le test d'une pluralité de lignes de puissance adressables sélectivement :
• la figure 4B est une vue analogue à la figure 4A d'un dispositif de test suivant une variante de réalisation ; et
• la figure 5 est un schéma synoptique plus détaillé du circuit de test proprement dit des figures 4A et 4B.

Other characteristics and advantages of the invention will result from the description which follows of an embodiment given solely by way of example and illustrated by the appended drawings in which:

• Figure 1 is an electrical diagram of a power stage according to the state of the art;
• Figure 2 is a diagram similar to that of Figure 1 showing a power stage modified according to the invention;
• Figure 3 is a graph illustrating the original effect obtained by means of the modified circuit of Figure 2;
• FIG. 4A is a block diagram of a device allowing the testing of a plurality of selectively addressable power lines:
• Figure 4B is a view similar to Figure 4A of a test device according to an alternative embodiment; and
• Figure 5 is a more detailed block diagram of the actual test circuit of Figures 4A and 4B.

The power stage 10 in FIG. 2 is similar to that in FIG. 1. It includes a Darlington T2 circuit made up of two PNP transistors. The emitter of T2 is connected to a current supply source SC and its base is connected to the collector of a switching transistor T1 via a resistor Rb2. The emitter of transistor T1 is connected to ground via a resistor Re and its base is attacked by an addressing circuit (not shown) through a resistor Rb1.

Unlike the circuit of Figure 1, the collector of T2 is connected to the electrical load Rc via a power diode D.

The currents and voltages present at different points on the circuit have been shown in FIG. 2 and it will be assumed that the electrical components used are identical to those of the circuit in FIG. 1.

Given the presence of the diode D which introduces an offset voltage VD, the formula (7) expressing the value of the voltage Vm on the output side of the power stage is modified as follows: $$\text{Vm (output) = Vce2sat + VD + RccIc.}$$

Expression (8) then becomes: $$\text{Rcc =}\frac{\text{2Vbe + Vce1sat + Rb2Ib2 + Re (Ib1 + Ib2) -Vce2sat-VD}}{\text{Ic}}$$

If we carry over the numerical values mentioned above in expression 10, we see that it is now possible, for a resistance Rcc of approximately 8Ω, to obtain the saturation of the circuit T2 if the switching voltage VD is at least equal to about 0.1V.

This phenomenon will be better understood by examining the graph in FIG. 3 where we have traced, for a given direct current Ic, the evolution of the output stage voltage Vm and of the voltage RcIc across the terminals of the load Rcen as a function of the latter's impedance.

In the absence of the diode D, the output voltage Vm remains constant as long as Rc is less than a value Rcc such that the difference between the voltage Vm and the voltage RcIc is equal to the saturation voltage Vce2sat of T2. For higher values of Rc, Vm varies linearly with Rc.

In the presence of an offset voltage VD, the saturation of the circuit T2 is reached for a lower value R′cc of the load Rc: the output voltage of the power stage then has the shape represented by the curve V ′ m in dashed lines.

The measurement of the output voltage Vm, V′m being the reflection of the impedance of the power line only when the saturation of T2 is reached, we observe that for a given current Ic, the modified circuit of figure 2 allows such a measurement for lower values of the load resistance Rc.

In the aforementioned digital example, it was calculated that the minimum value of the offset voltage VD was 0.1 V. In reality, taking into account the intrinsic dispersion of the characteristics of the components and their dispersion linked to the temperature, this value must be greater to ensure that the measurement under low direct current takes place in the linear variation zone of Vm as a function of Rc. In addition, for the measurement carried out under the low measurement current Im to be a faithful image of the impedance of the power line, it is necessary that the offset voltage introduced by the dipole interposed in the collector circuit of T2 remains substantially unchanged when this line is crossed by the high nominal current (at least 3 amperes) intended to ensure the ignition of the primer Rc.

This is the reason why a power diode is particularly well suited, since it generates an offset voltage of the order of 0.6 to 0.8 V for currents ranging from a few tens of milliamps to several amps. However, the invention is not limited to this type of component and any other electrical dipole capable of generating a substantially constant offset voltage of the desired order of magnitude would be perfectly suitable.

It will also be noted that the diode D could be connected, not between the circuit T2 and the load Rc, but between the load Rc and the ground.

This second configuration has the advantage of requiring only a single diode for testing a certain number of power lines in parallel, by means of a single test circuit 20 as shown in FIG. 4A.

However, it may be preferable to provide a diode Di associated with each load Rci if, for example, the overall configuration of the circuits does not make it possible to have a good common ground. The diode Di can be connected between the power stage and the load as shown in FIG. 4B, or between the load and the ground. Despite the multiplication of the number of diodes Di, this configuration can also be justified if the manufacturing technology used (hybrid circuits for example) allows the power stage 10i and the corresponding diode Di to be integrated into the same substrate.

The devices of FIGS. 4A and 4B differ only in the position and the number of diodes used, they will be the subject of a common description.

The test circuit 20, comprising the current source SC, is connected in parallel to all the stages of power 10 _{l ... 10i ... 10n} which should be tested. It will be assumed below that the power stages 10i, the charges Rci and the diodes Di have the same intrinsic characteristics in each power line Ll .... Li .... Ln and that the same current is circulated there. continuous test Im. The test circuit 20 has an input E for test control and an output S for reading the response to the test.

The blocks 21 and 22 shown for the record show respectively a circuit for generating the nominal direct current for supplying the loads Rci and an addressing circuit for the power stages 10 _{l ... 10i ... 10n} . The addressing circuit 22 selects the address of the input Ai of the power stage 10i which should be tested or supplied under the nominal current.

In a particularly simple embodiment of the invention, the test circuit 20 comprises the current source SC and a circuit for measuring the voltage Vm. The test is triggered by applying an appropriate command to the input E and by selecting the address of the power stage forming part of the power line Ll .... Li .... Ln whose l should be measured. 'impedance. This is provided by measuring the voltage Vm between point P and ground.

Preferably, the measured voltage Vm is compared with a predetermined threshold value and the result of this comparison may or may not validate the power line tested. The circuits generating a threshold and comparison value can be part of the test circuit 20 or be external to it. In the first case, the output S then delivers a signal capable of taking one or the other of two logical states depending on the result of the comparison.

The operations of supplying the load under the direct test current Im, of measuring the voltage Vm and possibly of comparison are repeated for each power line to be tested.

Nevertheless, the intrinsic dispersion of the characteristics of the components as well as their dispersion linked to the temperature means that the precision of the measurement obtained by this simplified embodiment will not be sufficient in certain applications. We can then use a test circuit implementing a differential measurement and an exemplary embodiment of which is given in FIG. 5.

$$\text{Vm2 = (Vce2sat)2 + VD2 + RcIm2}$$

This measurement will be made by a variation of the direct current of test Im in a very short time (a few microseconds), which will allow to consider the temperature of the composites as constant. If we take again the power stage of figure 2, we have the following system of equation: $$\text{Vm1 = (Vce2sat) 1 + VD1 + RcIm1}$$

$$\text{Vm2 = (Vce2sat) 2 + VD2 + RcIm2}$$

ΔIm = Im2 - Im1, est la variation connue du courant de test,
ΔVm = Vm2 - Vm1, est la variation de la tension Vm mesurée aux bornes de la ligne de puissance testée,
ΔVce2sat est la variation de la tension de saturation du circuit T2 pour la variation de courant ΔIm,
ΔVD est la variation de la tension de décalage de la diode D pour la variation de courant ΔIm.
ΔVce2 et ΔVD sont fonction des composants utilisés et seront à déterminer une fois pour toutes.If we choose Im2> Im1, we have: $$\text{Rc =}\frac{\text{ΔVm - (ΔVce2sat + ΔVD)}}{\text{ΔIm}}\text{, or :}$$

ΔIm = Im2 - Im1, is the known variation of the test current,
ΔVm = Vm2 - Vm1, is the variation of the voltage Vm measured at the terminals of the power line tested,
ΔVce2sat is the variation of the saturation voltage of circuit T2 for the variation of current ΔIm,
ΔVD is the variation of the offset voltage of diode D for the variation of current ΔIm.
ΔVce2 and ΔVD are a function of the components used and will be determined once and for all.

By way of example, for the numerical values considered above with reference to FIGS. 1 and 2, the correct operation of the power stage 10 is ensured for currents between 35 and 50 mA, which leads to adopt ΔIm = 15 my. The variation of the saturation voltage of the power transistor (T2) Vce2sat is 15 ± 5 mV for a variation ΔIm of 15 mA, in the temperature range between -55 and + 100 ° C. The variation of the forward voltage of the ΔVD diode in the same conditions is 15 mV ± 5 mV.

soit $$\text{ΔVm = 150 mV.}$$

It follows that the detection threshold for a load value equal to 8Ω is:
$$\text{ΔVm = 8x15x10⁻³ + (15 + 15) x 10⁻³}$$

is $$\text{ΔVm = 150 mV.}$$

, soit
   R mesure = 8Ω ± 0,7ΩIf the measurement circuit of ΔVm is set to this value, the error linked to variations in ΔVce2sat and ΔVD is ± 0.7. $$\frac{\text{(+10 mV)}}{\text{(+15 mA)}}$$

, is
R measurement = 8Ω ± 0.7Ω

Reference will now be made to FIG. 5 which shows a differential measurement test circuit applicable in particular to the test of cartridge primers in the context of the device which is the subject of the above-mentioned French patent application No. FR-A-2 611 883.

The test circuit 20 comprises at the input an optoelectronic isolation circuit 201 to which the test trigger commands are applied to its input E. The output of the isolation circuit 201 attacks the trigger input of a first monostable circuit 202 having a time constant of 40 µs, an input of an AND gate 203 and the trigger input of a second monostable circuit 204 having a time constant of 65 µs.

The inverted output Q of the first monostable 202 attacks the second input of the AND gate 203 and its non-inverted output Q drives a first current source 205 generating a first direct measurement current of 35 mA, as well as an authorization input d '' an analog memory 206.

The output of the AND gate 203 controls a second current source 207 generating a second direct measurement current of 50 mA, as well as the authorization input of a measurement circuit 208.

The current sources 205 and 207 are connected in parallel to the different power stages of the lines to be tested (only one of which has been shown for the sake of simplicity) by means of a diode 214. Similarly, the generator circuit 21 shooting current is connected to these same power stages via a diode 215. The diodes 214 and 215 together play the role of an OR gate.

The outputs of the analog memory 206 and of the measurement circuit 208 are applied to a measurement comparator 209 whose output is connected to a logic memory 210.

The clock input of the logic memory 210 is attacked by the output of a read circuit 211 itself controlled by the monostable circuit 204.

The result of the measurement present at the output Q of the logic memory 210 is transmitted to the output S of the test circuit 20 via an optoelectronic isolation circuit 212 and an adapter output circuit 213.

In operation, a test of the power line Li is triggered by selecting the input Ai of the power stage 10i and by applying a test command signal to the input E. Cellui, transmitted by the circuit d isolation 201 (photocoupler), causes the generation of a 40 µs pulse by the monostable circuit 202. This pulse controls the current source 205 which circulates a direct current of 35 mA in the power line Li. Simultaneously, this 40µs pulse applied to analog memory 206 authorizes the latter to memorize the voltage developed at point P.

After 40 µs, the Q output of the monostable circuit 202 changes to "0" and its Q output changes to "1".

The output of the AND gate 203 also changes to "1" and the current source 207 circulates a direct current of 50 mA in the power line Li. The level "1" at the output of the AND gate 203 also allows the circuit 208 to measure the voltage at point P. Comparator 209 compares to a predetermined threshold value the difference ΔVm between the voltages generated at point P by the currents of 50 and 35 mA respectively or, which is equivalent, compares the output of the measuring circuit 208 at the sum of the threshold value and the memorized value present at the output of the analog memory 206. Of course, it is also possible to subtract the threshold value from the output of the measurement circuit 208 and compare this difference to the output of the analog memory 206.

If ΔVm is greater than the threshold value, that is to say if the impedance of the load Rci is greater than the predetermined admitted value, the output of the comparator takes the logic value "0". Otherwise, it takes the logical value "1". Alternatively, one can naturally adapt a reverse logic.

At the end of 65 μs, the monostable circuit 204 causes the emission of a pulse by the read circuit 211. The logic state of the comparator 209 applied to the input D of the logic memory 20 is transferred to its output Q. This logic state is transmitted to the output S via the optoelectronic output circuit 212 and the adapter output circuit 213.

The output S of the test circuit 20 is in state "1" if the power line Li associated with the primer Rci is operational and in state "0" if the latter is defective.

It follows from the above that the invention allows, with good precision, a low resistance measurement across a power stage, this by overcoming the dispersion (intrinsic and related to temperature) of the characteristics of the constituent components. the measurement line.

Currently the measurement performed corresponds to the total impedance, line (L), transistor plus load (Rc). It would be possible, knowing the impedance of the line (cable L) without load and an approximate value of the dynamic impedances of the power transistor, to obtain a measurement of the load resistance with good accuracy.

The device described also makes it possible to use only one test circuit for any number of lines to be tested, which ensures a significant gain in components compared to a solution using a circuit. test per line. This results in better reliability of the device and a reduced cost.

Furthermore, it is possible to test power lines of different characteristics by means of the same test circuit, by adapting the comparison threshold and / or the intensity of the measurement direct current to each power line addressed. For this purpose, it is possible to use, for example, a programmable current generator and / or a circuit which will apply to the comparator 209 a threshold value depending on the selected power line Li.

Finally, it should be noted that the purpose of the test carried out by means of the device described may be to ensure that the impedance of the line is not less, but more than a predetermined value. If the load is supplied by a voltage source instead of a current source, the power line impedance test will then protect it or the source against overcurrents.

It goes without saying that the embodiments described are only examples and that they could be modified, in particular by substitution of technical equivalents, without departing from the scope of the invention.

Claims (12)

1. Device for direct current testing of the impedance of at least one power line, each line comprising an electrical load connected to a power stage capable of supplying it at a high nominal direct current, characterised in that it comprises:

- means for generating steady current (SC; 205, 207) capable of causing to flow in each line (Li) a DC test current (Im) of low value compared with the nominal current,

- an electric dipole (D; Di) connected in each power line in order to generate an offset voltage (VD) which is substantially constant when the DC test current or the nominal current passes through the said power line, the said offse voltage (VD) being added to the voltage drop at the terminals of the load (Rc; Rci) to put the power stage (10; 10i) at saturation when the DC test current passes through the load,

- means (206, 208) for measuring the voltage drop at the terminals of each power line, and

- means (209-213) for using the result of the said voltage measurement.

2. Device according to claim 1, characterised in that the electric dipole is a power diode (D).

3. Device according to either of claims 1 and 2, characterised in that each power stage (10; 10i) comprises two transistors configured in a Darlington circuit.

4. Device according to any one of claims 1 to 3, characterised in that the steady current generating means (Sc; 205, 207) are suitable for causing to pass through each power line (Li), successively a first (Im1) and a second (Im2) DC test current greater than the first and in that the said means of use comprise a comparator (209) for comparing the voltage drops generated at the terminals of the power line respectively by the first and second DC test currents.

5. Device according to claim 4, characterised in that the measuring means comprise an analogue memory (206) in which is stored the voltage drop generated by the first test current and a circuit (208) for measuring the voltage drop generated by the second test current and in that the said comparator (209) compares the difference between the said voltage drops with a predetermined threshold.

6. Device according to claim 5, characterised in that it comprises a first time delay circuit (202) controlling the steady current generating means (205) and the analogue memory (206) to cause the first test current to pass for a predetermined period of time and to store the resulting voltage drop at the terminals of each power line and a logic gate (203) controlling the steady current generating means (207) and the measuring circuit (208) to cause the second test current to flow and to measure the resulting voltage drop at the terminals of each power line after the elapse of the said predetermined time period.

7. Device according to claim 6, characterised in that the comparator (209) applies to the input of a logic memory (210) a logic signal capable of adopting one or other of two states depending on the result of the said comparison and in that the said device comprises a second delay circuit (204) with a time constant greater than that of the first time delay circuit (202) controlling a circuit (211) for reading the logic state applied by the comparator to the said logic memory (210).

8. Device according to any one of claims 1 to 7 for measuring the impedance of several power lines, each power stage of which is addressable selectively, comprising, in parallel with the said power lines (Li), a common test circuit (20) incorporating the steady current generating means, the measuring means and the means of use.

9. Device according to claim 8, characterised in that the electrical loads (Rci) of the different power lines (Li) are connected in parallel to earth through a common electric dipole (D).

10. Device according to claim 8, characterised in that each power line (Li) comprises an electric dipole (Di).

11. Device according to claim 10, characterised in that each electric dipole (Di) is connected between the power stage (10i) and the electrical load (Rci).

12. Application of the device according to any one of claims 1 to 11 to the testing of primers for pyrotechnic devices with electrical ignition resistive elements, characterised in that the said resistances constitute the electrical loads (Rci) of the power lines (Li) and the test current or currents have a value less than the current liable to cause the "flegmatisation" of the said primers.

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