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EP0000480A1 - Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium - Google Patents

Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium Download PDF

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Publication number
EP0000480A1
EP0000480A1 EP78100268A EP78100268A EP0000480A1 EP 0000480 A1 EP0000480 A1 EP 0000480A1 EP 78100268 A EP78100268 A EP 78100268A EP 78100268 A EP78100268 A EP 78100268A EP 0000480 A1 EP0000480 A1 EP 0000480A1
Authority
EP
European Patent Office
Prior art keywords
silicon
semiconductor elements
layer
semiconductor element
applying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP78100268A
Other languages
German (de)
English (en)
Other versions
EP0000480B1 (fr
Inventor
Jürgen Krausse
Wilhelm Ladenhauf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0000480A1 publication Critical patent/EP0000480A1/fr
Application granted granted Critical
Publication of EP0000480B1 publication Critical patent/EP0000480B1/fr
Expired legal-status Critical Current

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Classifications

    • H10W74/147—
    • H10W74/01—
    • H10W74/137—
    • H10W74/481—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Definitions

  • a protective layer at least at the points at which the pn junctions occur at the surface, by vapor deposition of silicon 8, for example, 0.1 / can also be thicker, for example, or. / um.
  • the areas of the semiconductor element that are not to be vaporized are covered before vapor deposition.
  • a further protective layer 9 can be applied to the vapor-deposited silicon layer 8, which can consist, for example, of normal rubber or another protective lacquer.
  • the evaporated silicon layer 8 can contain dopants such as boron or phosphorus to adjust the specific resistance. A content of the dopants mentioned is obtained in that one or more of these substances are vaporized with the silicon.
  • the layer 8 can also contain one or more metals such as aluminum to adjust the specific resistance. The metals can also be built into the silicon by vapor deposition. The potential relationships at the edge of the semiconductor element can be adjusted by changing the specific resistance of layer 8.
  • the layer 8 can be doped with phosphorus and have a specific resistance of 10 8 ohm cm.
  • the silicon layer 8 was in a vacuum evaporation system at a pressure of about 6.5. 10-4 PA ( 5.10 -6 Torr) evaporated.
  • a silicon block can be used as the silicon source.
  • the silicon can be evaporated using an electron beam. With an acceleration voltage of 8 kV and a current of around 0.5 A, a vapor deposition rate of 0.25 ⁇ m / min was achieved. It can also be increased, for example, to 0.5 ⁇ m / min and above by increasing the energy of the electron beam.
  • the silicon can also be evaporated by an ion beam, by direct current flow or by inductive heating. It is also possible to evaporate the silicon by radiant heat.
  • the layer 8 can also consist of several successively vapor-deposited layers, each with different properties. A change in the specific resistance via the thickness and an influence on the potential relationships on the edge surface of the semiconductor element are thus obtained.
  • the evaporated silicon layer is annealed.
  • the annealing takes place at a temperature between room temperature and the crystallization temperature of the silicon.
  • the crystallization temperature of the silicon is between 700 and 900 K.
  • the annealing is carried out at a temperature which is below the melting temperature of the material used for contacting, for example soft solder, or another metallization.
  • the reverse current in the reverse direction and the reverse current in the tilting direction of the semiconductor element can be drastically reduced by the annealing.
  • FIG. 2 shows that the reverse current for a certain type of semiconductor without annealing was 2. 10 3 nA.
  • the blocking current for three test specimens was at 280 ° C, the blocking current for three ashamed specimens was between 3 and 5.10 1 nA. After 23 and 41 hours of tempering at 280 ° C, further reductions in the blocking currents were observed.
  • Evaporation of the silicon itself can be carried out at room temperature.
  • the temperature of the subsequent heat treatment can then be selected so that the desired reduction in the blocking currents is achieved without, for example, components which have already been contacted being affected. This makes it possible to passivate chips that have already been soldered and contacted, so that no masking or selective etching of the chips is required.
  • FIG. 3 in which the shape of the space charge zone is shown when the pn junction 7 is stressed in the reverse direction.
  • the boundaries 11, 12 of the space charge zone 10 run parallel to the pn junctions, for example. If there is a blocking load for a long time, the space charge zone widens in that the boundary 12 of the space charge zone 10 at the edge of the semiconductor element shifts in the direction of the pn junction 6. At the same time, the boundary 11 of the space charge zone 10 moves away from the pn junction 7, but only to a much weaker extent, since the zone 4 is more heavily doped than the zone 3.
  • the expansion of the space charge zone is shown in dashed lines in the figure.
  • the reverse current increases until the so-called punch-through effect occurs at the edge when the pn junction 6 is reached, where the pn junction 7 loses its ability to block.
  • the widening also takes place at the pn junction 6 when the semiconductor element is loaded with a voltage in the reverse direction, that is to say the tilting direction.
  • the space charge zone 10 no longer widens at the edge. This can be done, for example, using the known photoelectric method for examining the space charge zones Determine the edge of a semiconductor element. This tet that the reverse currents do not increase, in other words that the characteristics remain stable in the reverse direction.
  • the invention has been described in connection with a semiconductor element for a thyristor. However, it can also be used in diodes, transistors and other semiconductor components. It can be used equally for mesa or planar structures. It is essential that silicon is evaporated onto at least the region in which the pn junctions occur on the surface of the semiconductor element.

Landscapes

  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
EP78100268A 1977-07-05 1978-06-28 Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium Expired EP0000480B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19772730367 DE2730367A1 (de) 1977-07-05 1977-07-05 Verfahren zum passivieren von halbleiterelementen
DE2730367 1977-07-05

Publications (2)

Publication Number Publication Date
EP0000480A1 true EP0000480A1 (fr) 1979-02-07
EP0000480B1 EP0000480B1 (fr) 1981-08-12

Family

ID=6013203

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100268A Expired EP0000480B1 (fr) 1977-07-05 1978-06-28 Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium

Country Status (7)

Country Link
US (1) US4322452A (fr)
EP (1) EP0000480B1 (fr)
JP (1) JPS5417672A (fr)
CA (1) CA1111149A (fr)
DE (1) DE2730367A1 (fr)
GB (1) GB1587030A (fr)
IT (1) IT1096857B (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0041684A1 (fr) * 1980-06-04 1981-12-16 Siemens Aktiengesellschaft Méthode de préparation de prise de contact de dispositifs en silicium pourvus de couches d'aluminium
US4561171A (en) * 1982-04-06 1985-12-31 Shell Austria Aktiengesellschaft Process of gettering semiconductor devices
AT384121B (de) * 1983-03-28 1987-10-12 Shell Austria Verfahren zum gettern von halbleiterbauelementen
EP0543257A3 (en) * 1991-11-13 1994-07-13 Siemens Ag Method of manufacturing a power-misfet

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860066A (en) * 1987-01-08 1989-08-22 International Business Machines Corporation Semiconductor electro-optical conversion
EP0381110B1 (fr) * 1989-02-01 1994-06-29 Siemens Aktiengesellschaft Couche de protection pour couches de passivation électroactives
ES2072321T3 (es) * 1989-02-01 1995-07-16 Siemens Ag Capa de pasivado electroactiva.
US5213670A (en) * 1989-06-30 1993-05-25 Siemens Aktiengesellschaft Method for manufacturing a polycrystalline layer on a substrate
JP2501641B2 (ja) * 1989-07-19 1996-05-29 住友重機械工業株式会社 長尺搬送材の横送り装置
US5451550A (en) * 1991-02-20 1995-09-19 Texas Instruments Incorporated Method of laser CVD seal a die edge
US6885522B1 (en) 1999-05-28 2005-04-26 Fujitsu Limited Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation
DE10358985B3 (de) * 2003-12-16 2005-05-19 Infineon Technologies Ag Halbleiterbauelement mit einem pn-Übergang und einer auf einer Oberfläche aufgebrachten Passivierungsschicht
US10581082B2 (en) * 2016-11-15 2020-03-03 Nanocomp Technologies, Inc. Systems and methods for making structures defined by CNT pulp networks

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2290040A1 (fr) * 1974-10-26 1976-05-28 Sony Corp Composant semi-conducteur, circuit integre comprenant de tels composants et procede de fabrication
DE2618733A1 (de) * 1975-04-30 1976-11-11 Sony Corp Halbleiterbauelement mit heterouebergang
NL7613893A (nl) * 1975-12-19 1977-06-21 Philips Nv Halfgeleiderinrichting met gepassiveerd opper- vlak, en werkwijze voor het vervaardigen van de inrichting.
FR2359510A1 (fr) * 1976-07-20 1978-02-17 Siemens Ag Composant a semi-conducteurs comportant une couche de protection realisant une passivation
DE2642413A1 (de) * 1976-09-21 1978-03-23 Siemens Ag Verfahren zum aufbringen einer aus silicium bestehenden passivierungsschicht

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2789258A (en) * 1955-06-29 1957-04-16 Raytheon Mfg Co Intrinsic coatings for semiconductor junctions
SE300472B (fr) * 1965-03-31 1968-04-29 Asea Ab
DE2018517B2 (de) * 1970-04-17 1973-02-22 Hitachi, Ltd , Tokio Erfahren zum herstellen eines halbleiterbauelements
US3765940A (en) * 1971-11-08 1973-10-16 Texas Instruments Inc Vacuum evaporated thin film resistors
US3806361A (en) * 1972-01-24 1974-04-23 Motorola Inc Method of making electrical contacts for and passivating a semiconductor device
JPS532552B2 (fr) * 1974-03-30 1978-01-28
JPS6041458B2 (ja) * 1975-04-21 1985-09-17 ソニー株式会社 半導体装置の製造方法
US4179528A (en) * 1977-05-18 1979-12-18 Eastman Kodak Company Method of making silicon device with uniformly thick polysilicon
US4134125A (en) * 1977-07-20 1979-01-09 Bell Telephone Laboratories, Incorporated Passivation of metallized semiconductor substrates

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2290040A1 (fr) * 1974-10-26 1976-05-28 Sony Corp Composant semi-conducteur, circuit integre comprenant de tels composants et procede de fabrication
DE2618733A1 (de) * 1975-04-30 1976-11-11 Sony Corp Halbleiterbauelement mit heterouebergang
NL7613893A (nl) * 1975-12-19 1977-06-21 Philips Nv Halfgeleiderinrichting met gepassiveerd opper- vlak, en werkwijze voor het vervaardigen van de inrichting.
FR2359510A1 (fr) * 1976-07-20 1978-02-17 Siemens Ag Composant a semi-conducteurs comportant une couche de protection realisant une passivation
DE2642413A1 (de) * 1976-09-21 1978-03-23 Siemens Ag Verfahren zum aufbringen einer aus silicium bestehenden passivierungsschicht

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0041684A1 (fr) * 1980-06-04 1981-12-16 Siemens Aktiengesellschaft Méthode de préparation de prise de contact de dispositifs en silicium pourvus de couches d'aluminium
US4561171A (en) * 1982-04-06 1985-12-31 Shell Austria Aktiengesellschaft Process of gettering semiconductor devices
AT384121B (de) * 1983-03-28 1987-10-12 Shell Austria Verfahren zum gettern von halbleiterbauelementen
EP0543257A3 (en) * 1991-11-13 1994-07-13 Siemens Ag Method of manufacturing a power-misfet

Also Published As

Publication number Publication date
DE2730367A1 (de) 1979-01-18
JPS6158976B2 (fr) 1986-12-13
US4322452A (en) 1982-03-30
IT7825181A0 (it) 1978-06-30
CA1111149A (fr) 1981-10-20
DE2730367C2 (fr) 1988-01-14
GB1587030A (en) 1981-03-25
EP0000480B1 (fr) 1981-08-12
JPS5417672A (en) 1979-02-09
IT1096857B (it) 1985-08-26

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