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EP0000170A1 - Procédé et dispositif pour controler le déroulement de procédés de développement ou de décapage - Google Patents

Procédé et dispositif pour controler le déroulement de procédés de développement ou de décapage Download PDF

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Publication number
EP0000170A1
EP0000170A1 EP78100197A EP78100197A EP0000170A1 EP 0000170 A1 EP0000170 A1 EP 0000170A1 EP 78100197 A EP78100197 A EP 78100197A EP 78100197 A EP78100197 A EP 78100197A EP 0000170 A1 EP0000170 A1 EP 0000170A1
Authority
EP
European Patent Office
Prior art keywords
etched
development
developed
grating
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP78100197A
Other languages
German (de)
English (en)
Other versions
EP0000170B1 (fr
Inventor
Holger Moritz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0000170A1 publication Critical patent/EP0000170A1/fr
Application granted granted Critical
Publication of EP0000170B1 publication Critical patent/EP0000170B1/fr
Expired legal-status Critical Current

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • H10P76/2041—

Definitions

  • the invention relates to a method and apparatus for controlling development or etch processes by measuring a g from the workpiece during the machining; svor- passage influenced radiation.
  • the deterioration of the tolerances that occurs during a development or etching process can be explained, among other things, by the fact that the illuminance in the peripheral zones of an exposed area, for example a linear area, is generally much lower than in the middle even with the most precise illumination .
  • Das has the consequence that the illuminance as a function of the distance from the center of the line does not have a rectangular shape, but has a gradual decrease towards the line edges, with the result that the width of the areas exposed by a development or an etching has a strong dependence on the development or etching time. Even with an approximately rectangular course of the exposure profiles, a widening of the exposed areas beyond the exposed areas can under certain circumstances be significantly enlarged by so-called "under-etching".
  • the above-mentioned high demands on the accuracy of the developed or etched patterns are further increased by the fact that a large number of exposures in successive process steps are required in the manufacture of an integrated circuit.
  • the development of the exposed photoresist layer is usually controlled by precisely observing a development time determined by test series to be carried out beforehand.
  • a number of other parameters such as concentration, purity and temperature of the developer and the nature, purity and thickness of the lacquer layers, but above all the illuminance during the exposure of the photoresist layers, have a major influence on the thickness of the exposed lines , despite the most exact process monitoring, errors cannot be excluded with the necessary security.
  • the invention is based on the object of specifying a method for monitoring and controlling development and / or etching processes, with the aid of which it is possible, with little technical effort, to terminate the development or etching process when there are precisely defined line widths and thus even during the process Exposure errors can largely compensate.
  • This object is achieved by the invention described in claim 1.
  • the method according to the invention has the advantage that instead of a series of very exact measurements required for carrying out a development or etching process, only the intensity of one or more diffraction orders has to be measured. Because of this Then only a single parameter, for example the development time, has to be changed in order to make changes to one or more of the above-mentioned parameters harmless. Instead of measurements and controls a variety of parameters thereby only the measurement of a light intensity and the control einzi- a g s parameter required.
  • the width of the exposed area of the semiconductor die 6 will be the same as the width of the transparent area of the mask 4 after a time that can only be determined experimentally.
  • this experimentally determined development time only applies if all other parameters, namely the intensity of the exposure, the duration of the exposure, the concentration, purity and temperature of the developer and the composition, purity and thickness of the photoresist layer can be kept constant with great accuracy .
  • the exposed area of the semiconductor die 6 will gradually take up the entire area between the lines 13 and 14 and, for some photoresists, after a further extension of the development time by " Undercutting "of the lacquer layer become even larger It is easy to see that at one exact transmission of the permeable areas of the mask 4, a whole series of parameters, some of which are very difficult to monitor, must be observed with the greatest accuracy.
  • any change in one of these parameters can lead to a reduction or enlargement of the exposed areas of the semiconductor wafer 6, as a result of which, in the worst case, several areas to be doped separately or to be provided separately with conductive coatings merge with one another or at least come so close to one another that the electrical properties of one another semiconductor circuit manufactured using this method can be changed very substantially.
  • Fig. 2 a simple embodiment of the invention is shown schematically and in Fig. 3 a section of Fig. 2 is shown in perspective.
  • the device consists of a vessel 15 in which a developer 16 is accommodated.
  • a developer 16 In the developer 16 there is a semiconductor chip 6 coated with a photoresist layer, which was exposed using the method illustrated in FIG. 1.
  • the areas of the semiconductor chip 6 designated with S and shown on a reduced scale and the photoresist layer thereon were exposed with a pattern which contains the areas and line structures which are doped in different ways or covered with conductive layers in order to build up an integrated circuit.
  • the central region of the semiconductor wafer, designated by G, and the photoresist layer thereon were exposed with a pattern consisting of a number of lines having predetermined widths and distances from one another.
  • the width of the lines and the distances between the individual lines of the grid generally correspond to the mean width of the lines and the distances between the lines in the areas S. These widths and distances can also be chosen larger or smaller than the widths and distances of the lines in the area S.
  • a light source 18 is provided for generating a monochromatic collimated light beam 19, which falls through a window 17 of the vessel 15 onto the region G of the semiconductor wafer exposed with a lattice structure.
  • the device also consists of two light detectors 22 and 23 which, in the direction of the second and third diffraction orders, fall on the grating formed in region G by the development luminescent radiation 19. !
  • the locations of the light detectors 22 and 23 are a unique function of the lattice constant g of the lattice formed in the region G. While the position of the diffraction orders for a given direction and for a given wavelength of the radiation 19 is a clear function of the grating constant g, that is to say independent of the process, the intensity of these diffraction orders is a clear function of the width of the line areas exposed by the development process. If, during the development process, the width b of the areas between the grating lines exposed by the development process is equal to half the grating constant g, i.e. the line spacing is equal to the line widths, then, as is known from diffraction optics, the intensity of the second-order diffraction maximum becomes O.
  • the intensity of the second diffraction order does not become 0 in practice, but passes through a minimum.
  • the course of this intensity is shown schematically in FIG. 4 as a function of the development time.
  • the line widths and lines can be advantageous Make the distances of the grating used for process control larger in order to prevent the intensity curve in the region of the second diffraction order or in the region of other diffraction orders from being falsified in the case of the sine-like grating which may result in this case.
  • an optimal grating constant can be determined experimentally, in which the minimum of certain diffraction orders is a clear criterion for the completion of the development process for the exposed circuit pattern.
  • the circuit pattern transmitted by exposure of the photoresist layer very large line widths and line spacing, it may be advisable to make the grid constant smaller and thereby increase the sensitivity of the display.
  • This course of the intensity of the second diffraction order is converted by the light detector 22 into electrical signals converts that are transmitted via a line 24 to an evaluation circuit 26.
  • the evaluation circuit 26 is designed such that a signal terminating the development process occurs on an output line 27 when certain intensity values in the range of one or more diffraction orders are reached.
  • the invention is of course not limited to patterns transmitted by masks or other physical templates to be reproduced. Rather, it can also be used in connection with patterns generated by so-called "artwork” generators, which can be designed, for example, as light or electron beam recorders.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
EP78100197A 1977-06-23 1978-06-20 Procédé et dispositif pour controler le déroulement de procédés de développement ou de décapage Expired EP0000170B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2728361 1977-06-23
DE2728361A DE2728361C2 (de) 1977-06-23 1977-06-23 Verfahren zum Feststellen eines vorgebbaren Endzustands eines Entwicklungs- oder Ätzvorgangs

Publications (2)

Publication Number Publication Date
EP0000170A1 true EP0000170A1 (fr) 1979-01-10
EP0000170B1 EP0000170B1 (fr) 1982-01-20

Family

ID=6012193

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100197A Expired EP0000170B1 (fr) 1977-06-23 1978-06-20 Procédé et dispositif pour controler le déroulement de procédés de développement ou de décapage

Country Status (4)

Country Link
US (1) US4179622A (fr)
EP (1) EP0000170B1 (fr)
JP (1) JPS5410677A (fr)
DE (2) DE2728361C2 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145332A (en) * 1980-04-12 1981-11-12 Victor Co Of Japan Ltd Detecting device for state of proper development
JPS589242A (ja) * 1981-07-08 1983-01-19 Pioneer Electronic Corp フオトレジスト湿式現像方法及び装置
JPS5814343A (ja) * 1981-07-17 1983-01-27 Pioneer Electronic Corp フオトレジスト湿式現像方法及び装置
JPS5870530A (ja) * 1981-10-22 1983-04-27 Toshiba Corp レジストパタ−ン形成方法
US4482424A (en) * 1983-05-06 1984-11-13 At&T Bell Laboratories Method for monitoring etching of resists by monitoring the flouresence of the unetched material
US4496425A (en) * 1984-01-30 1985-01-29 At&T Technologies, Inc. Technique for determining the end point of an etching process
US4636073A (en) * 1984-10-31 1987-01-13 International Business Machines Corporation Universal calibration standard for surface inspection systems
JP2509572B2 (ja) * 1985-08-19 1996-06-19 株式会社東芝 パタ−ン形成方法及び装置
JPS62193247A (ja) * 1986-02-20 1987-08-25 Fujitsu Ltd 現像終点決定方法
JPS63136625A (ja) * 1986-11-28 1988-06-08 Tokyo Univ 半導体素子の製造方法
JPH02125683A (ja) * 1988-11-04 1990-05-14 Nec Corp 回折格子の製造方法
US5264328A (en) * 1992-04-24 1993-11-23 International Business Machines Corporation Resist development endpoint detection for X-ray lithography
US20050042777A1 (en) * 2003-08-20 2005-02-24 The Boc Group Inc. Control of etch and deposition processes
DE102006037294A1 (de) * 2006-08-09 2008-02-14 Christian Spörl Verfahren und Vorrichtung zum Beobachten des Ätzvorgangs eines Substrats

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3957376A (en) * 1974-01-25 1976-05-18 International Business Machines Corporation Measuring method and system using a diffraction pattern
US4039370A (en) * 1975-06-23 1977-08-02 Rca Corporation Optically monitoring the undercutting of a layer being etched

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1564290C3 (de) * 1966-10-13 1975-08-07 Ernst Leitz Gmbh, 6330 Wetzlar Verfahren zum Ausrichten von Kopiermasken bei der Halbleiterfertigung und Vorrichtung zur Durchführung des Verfahrens
US3802940A (en) * 1969-08-18 1974-04-09 Computervision Corp Enhanced contrast semiconductor wafer alignment target and method for making same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3957376A (en) * 1974-01-25 1976-05-18 International Business Machines Corporation Measuring method and system using a diffraction pattern
US4039370A (en) * 1975-06-23 1977-08-02 Rca Corporation Optically monitoring the undercutting of a layer being etched

Also Published As

Publication number Publication date
DE2728361C2 (de) 1981-09-24
EP0000170B1 (fr) 1982-01-20
JPS5649447B2 (fr) 1981-11-21
JPS5410677A (en) 1979-01-26
DE2728361A1 (de) 1979-01-11
US4179622A (en) 1979-12-18
DE2861541D1 (en) 1982-03-04

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