DE60329192D1 - Transfer einer dünnschicht von einem wafer mit einer pufferschicht - Google Patents

Transfer einer dünnschicht von einem wafer mit einer pufferschicht

Info

Publication number: DE60329192D1
Authority: DE; Germany
Prior art keywords: layer; lattice parameter; wafer; buffer layer; semiconductor material
Prior art date: 2002-07-09
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE60329192T

Other languages

English (en)

Inventor

Bruno Ghyselen

Cecile Aulnette

Benedite Osternaud

Nicolas Daval

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Soitec SA

Original Assignee

Soitec SA

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-07-09

Filing date

2003-07-09

Publication date

2009-10-22

2003-07-09 Application filed by Soitec SA filed Critical Soitec SA

2009-10-22 Application granted granted Critical

2009-10-22 Publication of DE60329192D1 publication Critical patent/DE60329192D1/de

2023-07-10 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- H10P14/20—
- H10P90/1924—
- H10P90/1916—
- H10W10/181—

Landscapes

Recrystallisation Techniques (AREA)
Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Element Separation (AREA)
Mechanical Treatment Of Semiconductor (AREA)
Storage Of Web-Like Or Filamentary Materials (AREA)
Laminated Bodies (AREA)
Magnetic Record Carriers (AREA)

DE60329192T 2002-07-09 2003-07-09 Transfer einer dünnschicht von einem wafer mit einer pufferschicht Expired - Lifetime DE60329192D1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
FR0208600A FR2842349B1 (fr)	2002-07-09	2002-07-09	Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
PCT/IB2003/003466 WO2004006327A2 (en)	2002-07-09	2003-07-09	Transfer of a thin layer from a wafer comprising a buffer layer

Publications (1)

Publication Number	Publication Date
DE60329192D1 true DE60329192D1 (de)	2009-10-22

Family

ID=29763664

Family Applications (2)

Application Number	Title	Priority Date	Filing Date
DE60329293T Expired - Lifetime DE60329293D1 (de)	2002-07-09	2003-07-09	Übertragung einer dünnen schicht von einer scheibe mit einer pufferschicht
DE60329192T Expired - Lifetime DE60329192D1 (de)	2002-07-09	2003-07-09	Transfer einer dünnschicht von einem wafer mit einer pufferschicht

Family Applications Before (1)

Application Number	Title	Priority Date	Filing Date
DE60329293T Expired - Lifetime DE60329293D1 (de)	2002-07-09	2003-07-09	Übertragung einer dünnen schicht von einer scheibe mit einer pufferschicht

Country Status (11)

Country	Link
US (1)	US6991956B2 (de)
EP (2)	EP1535326B1 (de)
JP (2)	JP2005532688A (de)
KR (1)	KR100796832B1 (de)
CN (1)	CN100477150C (de)
AT (2)	ATE443344T1 (de)
AU (2)	AU2003249475A1 (de)
DE (2)	DE60329293D1 (de)
FR (1)	FR2842349B1 (de)
TW (1)	TWI289900B (de)
WO (2)	WO2004006311A2 (de)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
FR2773261B1 (fr)	1997-12-30	2000-01-28	Commissariat Energie Atomique	Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7227176B2 (en)	1998-04-10	2007-06-05	Massachusetts Institute Of Technology	Etch stop layer system
JP2004507084A (ja)	2000-08-16	2004-03-04	マサチューセッツ　インスティテュート　オブ　テクノロジー	グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
US6649480B2 (en)	2000-12-04	2003-11-18	Amberwave Systems Corporation	Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6830976B2 (en)	2001-03-02	2004-12-14	Amberwave Systems Corproation	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en)	2001-03-02	2004-03-09	Amberwave Systems Corporation	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6940089B2 (en)	2001-04-04	2005-09-06	Massachusetts Institute Of Technology	Semiconductor device structure
US6717213B2 (en) *	2001-06-29	2004-04-06	Intel Corporation	Creation of high mobility channels in thin-body SOI devices
US7074623B2 (en)	2002-06-07	2006-07-11	Amberwave Systems Corporation	Methods of forming strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en)	2002-06-07	2007-12-11	Amberwave Systems Corporation	Control of strain in device layers by selective relaxation
US7335545B2 (en)	2002-06-07	2008-02-26	Amberwave Systems Corporation	Control of strain in device layers by prevention of relaxation
US20030227057A1 (en)	2002-06-07	2003-12-11	Lochtefeld Anthony J.	Strained-semiconductor-on-insulator device structures
US6995430B2 (en)	2002-06-07	2006-02-07	Amberwave Systems Corporation	Strained-semiconductor-on-insulator device structures
US7615829B2 (en)	2002-06-07	2009-11-10	Amberwave Systems Corporation	Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
AU2003247513A1 (en)	2002-06-10	2003-12-22	Amberwave Systems Corporation	Growing source and drain elements by selecive epitaxy
US6982474B2 (en)	2002-06-25	2006-01-03	Amberwave Systems Corporation	Reacted conductive gate electrodes
US7018910B2 (en) *	2002-07-09	2006-03-28	S.O.I.Tec Silicon On Insulator Technologies S.A.	Transfer of a thin layer from a wafer comprising a buffer layer
US7510949B2 (en)	2002-07-09	2009-03-31	S.O.I.Tec Silicon On Insulator Technologies	Methods for producing a multilayer semiconductor structure
US6953736B2 (en)	2002-07-09	2005-10-11	S.O.I.Tec Silicon On Insulator Technologies S.A.	Process for transferring a layer of strained semiconductor material
EP1532676A2 (de) *	2002-08-26	2005-05-25	S.O.I.Tec Silicon on Insulator Technologies	Mechanische wiederverwertung einer halbleiterscheibe, die eine pufferschicht enthält, nach der entfernung einer dünnen schicht daher
EP1532677B1 (de) *	2002-08-26	2011-08-03	S.O.I.Tec Silicon on Insulator Technologies	Wiederverwertung einer halbleiterscheibe, die eine pufferschicht enthält, nach der entfernung einer dünnen schicht daher
US6730576B1 (en) *	2002-12-31	2004-05-04	Advanced Micro Devices, Inc.	Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer
US7332417B2 (en)	2003-01-27	2008-02-19	Amberwave Systems Corporation	Semiconductor structures with structural homogeneity
KR100728173B1 (ko)	2003-03-07	2007-06-13	앰버웨이브 시스템즈 코포레이션	쉘로우 트렌치 분리법
FR2861497B1 (fr) *	2003-10-28	2006-02-10	Soitec Silicon On Insulator	Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2867310B1 (fr)	2004-03-05	2006-05-26	Soitec Silicon On Insulator	Technique d'amelioration de la qualite d'une couche mince prelevee
FR2867307B1 (fr)	2004-03-05	2006-05-26	Soitec Silicon On Insulator	Traitement thermique apres detachement smart-cut
US7282449B2 (en)	2004-03-05	2007-10-16	S.O.I.Tec Silicon On Insulator Technologies	Thermal treatment of a semiconductor layer
US8227319B2 (en) *	2004-03-10	2012-07-24	Agere Systems Inc.	Bipolar junction transistor having a high germanium concentration in a silicon-germanium layer and a method for forming the bipolar junction transistor
FR2868202B1 (fr) *	2004-03-25	2006-05-26	Commissariat Energie Atomique	Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium.
US7495266B2 (en) *	2004-06-16	2009-02-24	Massachusetts Institute Of Technology	Strained silicon-on-silicon by wafer bonding and layer transfer
US6893936B1 (en) *	2004-06-29	2005-05-17	International Business Machines Corporation	Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
WO2006033292A1 (ja) *	2004-09-24	2006-03-30	Shin-Etsu Handotai Co., Ltd.	半導体ウェーハの製造方法
JP4617820B2 (ja) *	2004-10-20	2011-01-26	信越半導体株式会社	半導体ウェーハの製造方法
US7247545B2 (en) *	2004-11-10	2007-07-24	Sharp Laboratories Of America, Inc.	Fabrication of a low defect germanium film by direct wafer bonding
JP2006140187A (ja) *	2004-11-10	2006-06-01	Shin Etsu Handotai Co Ltd	半導体ウェーハの製造方法
US7393733B2 (en)	2004-12-01	2008-07-01	Amberwave Systems Corporation	Methods of forming hybrid fin field-effect transistor structures
FR2880988B1 (fr) *	2005-01-19	2007-03-30	Soitec Silicon On Insulator	TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
FR2886052B1 (fr)	2005-05-19	2007-11-23	Soitec Silicon On Insulator	Traitement de surface apres gravure selective
FR2886053B1 (fr)	2005-05-19	2007-08-10	Soitec Silicon On Insulator	Procede de gravure chimique uniforme
FR2888400B1 (fr)	2005-07-08	2007-10-19	Soitec Silicon On Insulator	Procede de prelevement de couche
KR100707654B1 (ko)	2005-07-26	2007-04-13	동부일렉트로닉스 주식회사	반도체 장치의 소자 분리 구조 및 그 형성방법
FR2891281B1 (fr) *	2005-09-28	2007-12-28	Commissariat Energie Atomique	Procede de fabrication d'un element en couches minces.
FR2892733B1 (fr) *	2005-10-28	2008-02-01	Soitec Silicon On Insulator	Relaxation de couches
US8012592B2 (en)	2005-11-01	2011-09-06	Massachuesetts Institute Of Technology	Monolithically integrated semiconductor materials and devices
US8063397B2 (en)	2006-06-28	2011-11-22	Massachusetts Institute Of Technology	Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
FR2910179B1 (fr) *	2006-12-19	2009-03-13	Commissariat Energie Atomique	PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2912550A1 (fr) *	2007-02-14	2008-08-15	Soitec Silicon On Insulator	Procede de fabrication d'une structure ssoi.
US8461055B2 (en)	2007-05-03	2013-06-11	Soitec	Process for preparing cleaned surfaces of strained silicon
FR2922359B1 (fr) *	2007-10-12	2009-12-18	Commissariat Energie Atomique	Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2947098A1 (fr) *	2009-06-18	2010-12-24	Commissariat Energie Atomique	Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US8492234B2 (en) *	2010-06-29	2013-07-23	International Business Machines Corporation	Field effect transistor device
US8415253B2 (en) *	2011-03-30	2013-04-09	International Business Machinees Corporation	Low-temperature in-situ removal of oxide from a silicon surface during CMOS epitaxial processing
FR2978605B1 (fr)	2011-07-28	2015-10-16	Soitec Silicon On Insulator	Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support
CN104517883B (zh) *	2013-09-26	2017-08-15	中国科学院上海微系统与信息技术研究所	一种利用离子注入技术制备绝缘体上半导体材料的方法
FR3064398B1 (fr) *	2017-03-21	2019-06-07	Soitec	Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure
US20190181218A1 (en) *	2017-12-08	2019-06-13	Qualcomm Incorporated	Semiconductor device with high charge carrier mobility materials on porous silicon
GB201916515D0 (en)	2019-11-13	2019-12-25	Pilkington Group Ltd	Coated glass substrate

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5461243A (en) *	1993-10-29	1995-10-24	International Business Machines Corporation	Substrate for tensilely strained semiconductor
EP0799495A4 (de) *	1994-11-10	1999-11-03	Lawrence Semiconductor Researc	Silizium-germanium-kohlenstoff-verbindung und dazugehörende prozesse
ATE261612T1 (de)	1996-12-18	2004-03-15	Canon Kk	Vefahren zum herstellen eines halbleiterartikels unter verwendung eines substrates mit einer porösen halbleiterschicht
US5906951A (en) *	1997-04-30	1999-05-25	International Business Machines Corporation	Strained Si/SiGe layers on insulator
US5882987A (en)	1997-08-26	1999-03-16	International Business Machines Corporation	Smart-cut process for the production of thin semiconductor material films
FR2777115B1 (fr)	1998-04-07	2001-07-13	Commissariat Energie Atomique	Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
WO1999053539A1 (en)	1998-04-10	1999-10-21	Massachusetts Institute Of Technology	Silicon-germanium etch stop layer system
JP3358550B2 (ja) *	1998-07-07	2002-12-24	信越半導体株式会社	Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP3884203B2 (ja) *	1998-12-24	2007-02-21	株式会社東芝	半導体装置の製造方法
US6323108B1 (en) *	1999-07-27	2001-11-27	The United States Of America As Represented By The Secretary Of The Navy	Fabrication ultra-thin bonded semiconductor layers
JP2003506883A (ja) *	1999-08-10	2003-02-18	シリコンジェネシスコーポレイション	低打ち込みドーズ量を用いて多層基板を製造するための劈開プロセス
JP3607194B2 (ja) *	1999-11-26	2005-01-05	株式会社東芝	半導体装置、半導体装置の製造方法、及び半導体基板
KR100429869B1 (ko) *	2000-01-07	2004-05-03	삼성전자주식회사	매몰 실리콘 저머늄층을 갖는 ｃｍｏｓ 집적회로 소자 및기판과 그의 제조방법
JP2001284558A (ja) *	2000-03-31	2001-10-12	Fujitsu Ltd	積層半導体基板及びその製造方法並びに半導体装置
JP2003536273A (ja)	2000-06-22	2003-12-02	マサチューセッツインスティテュートオブテクノロジー	エッチング阻止層システム
JP2004507084A (ja) *	2000-08-16	2004-03-04	マサチューセッツ　インスティテュート　オブ　テクノロジー	グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
JP3998408B2 (ja) *	2000-09-29	2007-10-24	株式会社東芝	半導体装置及びその製造方法
US6410371B1 (en) *	2001-02-26	2002-06-25	Advanced Micro Devices, Inc.	Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
US6717213B2 (en) *	2001-06-29	2004-04-06	Intel Corporation	Creation of high mobility channels in thin-body SOI devices

2002
- 2002-07-09 FR FR0208600A patent/FR2842349B1/fr not_active Expired - Fee Related
2003
- 2003-07-09 EP EP03762848A patent/EP1535326B1/de not_active Expired - Lifetime
- 2003-07-09 WO PCT/IB2003/003497 patent/WO2004006311A2/en not_active Ceased
- 2003-07-09 TW TW092118765A patent/TWI289900B/zh not_active IP Right Cessation
- 2003-07-09 EP EP03762850A patent/EP1522097B9/de not_active Expired - Lifetime
- 2003-07-09 DE DE60329293T patent/DE60329293D1/de not_active Expired - Lifetime
- 2003-07-09 JP JP2004519128A patent/JP2005532688A/ja active Pending
- 2003-07-09 JP JP2004519126A patent/JP4904478B2/ja not_active Expired - Lifetime
- 2003-07-09 AU AU2003249475A patent/AU2003249475A1/en not_active Abandoned
- 2003-07-09 CN CNB038162032A patent/CN100477150C/zh not_active Expired - Lifetime
- 2003-07-09 WO PCT/IB2003/003466 patent/WO2004006327A2/en not_active Ceased
- 2003-07-09 KR KR1020057000477A patent/KR100796832B1/ko not_active Expired - Lifetime
- 2003-07-09 AU AU2003250462A patent/AU2003250462A1/en not_active Abandoned
- 2003-07-09 DE DE60329192T patent/DE60329192D1/de not_active Expired - Lifetime
- 2003-07-09 AT AT03762850T patent/ATE443344T1/de not_active IP Right Cessation
- 2003-07-09 AT AT03762848T patent/ATE442667T1/de not_active IP Right Cessation
2005
- 2005-01-10 US US11/032,844 patent/US6991956B2/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
ATE442667T1 (de)	2009-09-15
AU2003249475A1 (en)	2004-01-23
TWI289900B (en)	2007-11-11
JP2005532688A (ja)	2005-10-27
US6991956B2 (en)	2006-01-31
CN100477150C (zh)	2009-04-08
JP2005532687A (ja)	2005-10-27
AU2003250462A1 (en)	2004-01-23
WO2004006311A3 (en)	2004-03-04
ATE443344T1 (de)	2009-10-15
AU2003250462A8 (en)	2004-01-23
EP1522097A2 (de)	2005-04-13
JP4904478B2 (ja)	2012-03-28
WO2004006311A2 (en)	2004-01-15
EP1535326A2 (de)	2005-06-01
WO2004006327A3 (en)	2004-03-04
KR100796832B1 (ko)	2008-01-22
EP1522097B9 (de)	2010-03-03
TW200411820A (en)	2004-07-01
EP1522097B1 (de)	2009-09-16
EP1535326B1 (de)	2009-09-09
DE60329293D1 (de)	2009-10-29
FR2842349B1 (fr)	2005-02-18
KR20050018984A (ko)	2005-02-28
WO2004006327A2 (en)	2004-01-15
US20050191825A1 (en)	2005-09-01
FR2842349A1 (fr)	2004-01-16
CN1666330A (zh)	2005-09-07

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