DE60322154D1 - Verfahren zur Selbstausrichtung einer damascenen Gatterstruktur zu Isolationsgebieten - Google Patents
Verfahren zur Selbstausrichtung einer damascenen Gatterstruktur zu IsolationsgebietenInfo
- Publication number
- DE60322154D1 DE60322154D1 DE60322154T DE60322154T DE60322154D1 DE 60322154 D1 DE60322154 D1 DE 60322154D1 DE 60322154 T DE60322154 T DE 60322154T DE 60322154 T DE60322154 T DE 60322154T DE 60322154 D1 DE60322154 D1 DE 60322154D1
- Authority
- DE
- Germany
- Prior art keywords
- silicon oxide
- shallow trench
- regions
- gate structures
- gate structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H10D64/01342—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0188—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H10W10/0143—
-
- H10W10/17—
-
- H10D64/01316—
-
- H10D64/0132—
-
- H10D64/01336—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
- H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/225,805 US6713335B2 (en) | 2002-08-22 | 2002-08-22 | Method of self-aligning a damascene gate structure to isolation regions |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE60322154D1 true DE60322154D1 (de) | 2008-08-28 |
Family
ID=31187999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60322154T Expired - Lifetime DE60322154D1 (de) | 2002-08-22 | 2003-08-20 | Verfahren zur Selbstausrichtung einer damascenen Gatterstruktur zu Isolationsgebieten |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6713335B2 (de) |
| EP (1) | EP1391925B1 (de) |
| JP (1) | JP2004134757A (de) |
| AT (1) | ATE401665T1 (de) |
| DE (1) | DE60322154D1 (de) |
| SG (1) | SG102720A1 (de) |
| TW (1) | TWI260732B (de) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200425298A (en) * | 2003-05-01 | 2004-11-16 | Nanya Technology Corp | Fabrication method for a damascene bitline contact |
| US20050196946A1 (en) * | 2004-03-02 | 2005-09-08 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing solid-state imaging device |
| JP4577680B2 (ja) * | 2004-04-13 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
| JP4054321B2 (ja) * | 2004-06-23 | 2008-02-27 | 松下電器産業株式会社 | 半導体装置 |
| US7118952B2 (en) * | 2004-07-14 | 2006-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making transistor with strained source/drain |
| US7148548B2 (en) * | 2004-07-20 | 2006-12-12 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
| US7138323B2 (en) * | 2004-07-28 | 2006-11-21 | Intel Corporation | Planarizing a semiconductor structure to form replacement metal gates |
| KR100641993B1 (ko) * | 2004-12-15 | 2006-11-02 | 동부일렉트로닉스 주식회사 | 고유전율의 절연막을 갖는 씨모스 이미지 센서의 제조 방법 |
| EP1997044B1 (de) * | 2006-03-15 | 2014-05-07 | Google, Inc. | Automatische anzeige von bildern mit neuer grösse |
| TWI336918B (en) * | 2007-05-08 | 2011-02-01 | Nanya Technology Corp | Method of manufacturing the shallow trench isolation structure |
| US7998832B2 (en) | 2008-08-27 | 2011-08-16 | Advanced Micro Devices, Inc. | Semiconductor device with isolation trench liner, and related fabrication methods |
| US8735991B2 (en) | 2011-12-01 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High gate density devices and methods |
| US9865690B2 (en) * | 2012-04-10 | 2018-01-09 | Qorvo Us, Inc. | Methods for fabricating a metal structure for a semiconductor device |
| US9165838B2 (en) * | 2014-02-26 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company Limited | Methods of forming low resistance contacts |
| US9530853B2 (en) | 2014-03-10 | 2016-12-27 | Qorvo Us, Inc. | Semiconductor device with reduced leakage current and method for making the same |
| DE102014107994A1 (de) * | 2014-06-05 | 2015-12-17 | Infineon Technologies Austria Ag | Halbleitervorrichtung und Verfahren zum Herstellen der Halbleitervorrichtung |
| US9666586B2 (en) * | 2014-08-14 | 2017-05-30 | Gil Asa | CMOS compatible memory cells |
| US9378968B2 (en) * | 2014-09-02 | 2016-06-28 | United Microelectronics Corporation | Method for planarizing semiconductor device |
| FR3036846B1 (fr) | 2015-05-29 | 2018-06-15 | Stmicroelectronics (Crolles 2) Sas | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
| US10147719B2 (en) * | 2016-11-17 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor field effect transistors and manufacturing method thereof |
| US10784359B2 (en) | 2018-05-18 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-conformal oxide liner and manufacturing methods thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1070187A (ja) * | 1996-08-28 | 1998-03-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP4160167B2 (ja) * | 1997-06-30 | 2008-10-01 | 株式会社東芝 | 半導体装置の製造方法 |
| US6261887B1 (en) * | 1997-08-28 | 2001-07-17 | Texas Instruments Incorporated | Transistors with independently formed gate structures and method |
| US6248643B1 (en) * | 1999-04-02 | 2001-06-19 | Vanguard International Semiconductor Corporation | Method of fabricating a self-aligned contact |
| US6258677B1 (en) * | 1999-10-01 | 2001-07-10 | Chartered Seminconductor Manufacturing Ltd. | Method of fabricating wedge isolation transistors |
| JP3538108B2 (ja) * | 2000-03-14 | 2004-06-14 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
| JP2001267561A (ja) * | 2000-03-21 | 2001-09-28 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
| US6204137B1 (en) * | 2000-04-24 | 2001-03-20 | Chartered Semiconductor Manufacturing, Ltd. | Method to form transistors and local interconnects using a silicon nitride dummy gate technique |
-
2002
- 2002-08-22 US US10/225,805 patent/US6713335B2/en not_active Expired - Fee Related
-
2003
- 2003-08-05 SG SG200304568A patent/SG102720A1/en unknown
- 2003-08-05 TW TW092121331A patent/TWI260732B/zh active
- 2003-08-20 DE DE60322154T patent/DE60322154D1/de not_active Expired - Lifetime
- 2003-08-20 AT AT03368080T patent/ATE401665T1/de not_active IP Right Cessation
- 2003-08-20 EP EP03368080A patent/EP1391925B1/de not_active Expired - Lifetime
- 2003-08-21 JP JP2003297152A patent/JP2004134757A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US6713335B2 (en) | 2004-03-30 |
| US20040038466A1 (en) | 2004-02-26 |
| JP2004134757A (ja) | 2004-04-30 |
| EP1391925A3 (de) | 2005-04-20 |
| TW200403803A (en) | 2004-03-01 |
| TWI260732B (en) | 2006-08-21 |
| EP1391925B1 (de) | 2008-07-16 |
| EP1391925A2 (de) | 2004-02-25 |
| ATE401665T1 (de) | 2008-08-15 |
| SG102720A1 (en) | 2004-03-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| R082 | Change of representative |
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