FR3036846B1 - Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant - Google Patents
Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant Download PDFInfo
- Publication number
- FR3036846B1 FR3036846B1 FR1554853A FR1554853A FR3036846B1 FR 3036846 B1 FR3036846 B1 FR 3036846B1 FR 1554853 A FR1554853 A FR 1554853A FR 1554853 A FR1554853 A FR 1554853A FR 3036846 B1 FR3036846 B1 FR 3036846B1
- Authority
- FR
- France
- Prior art keywords
- fdsoi
- integrated circuit
- soi substrate
- corresponding integrated
- transistors made
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0188—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- H10P90/1906—
-
- H10W10/011—
-
- H10W10/014—
-
- H10W10/0143—
-
- H10W10/061—
-
- H10W10/10—
-
- H10W10/17—
-
- H10W10/181—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1554853A FR3036846B1 (fr) | 2015-05-29 | 2015-05-29 | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
| CN201520976019.XU CN205542782U (zh) | 2015-05-29 | 2015-11-30 | 集成电路 |
| CN201510860495.XA CN106206455B (zh) | 2015-05-29 | 2015-11-30 | 用于在soi衬底特别是fdsoi衬底上制造的晶体管之间局部隔离的方法以及对应的集成电路 |
| US14/956,594 US9876076B2 (en) | 2015-05-29 | 2015-12-02 | Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit |
| DE102015121913.1A DE102015121913B4 (de) | 2015-05-29 | 2015-12-16 | Verfahren zur lokalen Isolierung zwischen Transistoren, die auf einem Substrat SOI, insbesondere FDSOI, verwirklicht sind, und entsprechende integrierte Schaltung |
| US15/845,930 US10283588B2 (en) | 2015-05-29 | 2017-12-18 | Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1554853A FR3036846B1 (fr) | 2015-05-29 | 2015-05-29 | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
| FR1554853 | 2015-05-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR3036846A1 FR3036846A1 (fr) | 2016-12-02 |
| FR3036846B1 true FR3036846B1 (fr) | 2018-06-15 |
Family
ID=54199786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1554853A Expired - Fee Related FR3036846B1 (fr) | 2015-05-29 | 2015-05-29 | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US9876076B2 (fr) |
| CN (2) | CN106206455B (fr) |
| DE (1) | DE102015121913B4 (fr) |
| FR (1) | FR3036846B1 (fr) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3036846B1 (fr) * | 2015-05-29 | 2018-06-15 | Stmicroelectronics (Crolles 2) Sas | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
| JP6594261B2 (ja) * | 2016-05-24 | 2019-10-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US12349454B2 (en) * | 2022-02-17 | 2025-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Checkerboard dummy design for epitaxial open ratio |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303962B1 (en) * | 1999-01-06 | 2001-10-16 | Advanced Micro Devices, Inc. | Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures |
| JP4698793B2 (ja) * | 2000-04-03 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US6713335B2 (en) | 2002-08-22 | 2004-03-30 | Chartered Semiconductor Manufacturing Ltd. | Method of self-aligning a damascene gate structure to isolation regions |
| US7834662B2 (en) | 2006-12-13 | 2010-11-16 | Apple Inc. | Level shifter with embedded logic and low minimum voltage |
| US9349655B2 (en) * | 2008-08-29 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for mechanical stress enhancement in semiconductor devices |
| JP2010251344A (ja) * | 2009-04-10 | 2010-11-04 | Hitachi Ltd | 半導体装置およびその製造方法 |
| US8502316B2 (en) | 2010-02-11 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned two-step STI formation through dummy poly removal |
| US9263339B2 (en) * | 2010-05-20 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective etching in the formation of epitaxy regions in MOS devices |
| US8492210B2 (en) * | 2010-12-17 | 2013-07-23 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor, semiconductor device comprising the transistor and method for manufacturing the same |
| US8546208B2 (en) * | 2011-08-19 | 2013-10-01 | International Business Machines Corporation | Isolation region fabrication for replacement gate processing |
| CN103050525B (zh) * | 2011-10-12 | 2015-06-17 | 中国科学院微电子研究所 | Mosfet及其制造方法 |
| US8735991B2 (en) | 2011-12-01 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High gate density devices and methods |
| FR3036846B1 (fr) * | 2015-05-29 | 2018-06-15 | Stmicroelectronics (Crolles 2) Sas | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant |
-
2015
- 2015-05-29 FR FR1554853A patent/FR3036846B1/fr not_active Expired - Fee Related
- 2015-11-30 CN CN201510860495.XA patent/CN106206455B/zh active Active
- 2015-11-30 CN CN201520976019.XU patent/CN205542782U/zh not_active Withdrawn - After Issue
- 2015-12-02 US US14/956,594 patent/US9876076B2/en active Active
- 2015-12-16 DE DE102015121913.1A patent/DE102015121913B4/de active Active
-
2017
- 2017-12-18 US US15/845,930 patent/US10283588B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN205542782U (zh) | 2016-08-31 |
| DE102015121913A1 (de) | 2016-12-01 |
| US10283588B2 (en) | 2019-05-07 |
| US20160351660A1 (en) | 2016-12-01 |
| CN106206455B (zh) | 2020-11-13 |
| US9876076B2 (en) | 2018-01-23 |
| CN106206455A (zh) | 2016-12-07 |
| US20180108731A1 (en) | 2018-04-19 |
| FR3036846A1 (fr) | 2016-12-02 |
| DE102015121913B4 (de) | 2023-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2579756B (en) | Optimization method for integrated circuit wafer test | |
| JP2017199900A5 (ja) | 半導体装置の作製方法 | |
| EP3288063A4 (fr) | Dispositif de pré-alignement et procédé pour plaquette | |
| TW201612991A (en) | Apparatus and methods for micro-transfer-printing | |
| EP3496138A4 (fr) | Substrat de support, stratifié avec substrat de support, et procédé de fabrication d'un substrat de boîtier pour monter un élément semi-conducteur | |
| SG10201911900YA (en) | Mask blank, method for manufacturing transfer mask, and method for manufacturing semiconductor device | |
| IL275116A (en) | A method for depositing an epitaxial layer in the front part of a semiconductor wafer and a device for performing the method | |
| FR3051596B1 (fr) | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant | |
| SG11202007053XA (en) | Manufacturing method for semiconductor device, and adhesive film | |
| SG10201907085QA (en) | Semiconductor substrate processing method | |
| EP3818561C0 (fr) | Substrat pour un dispositif integre radioafrequence et son procede de fabrication | |
| FR3051968B1 (fr) | Procede de fabrication d'un substrat semi-conducteur a haute resistivite | |
| SG11202001374SA (en) | Method for cleaning silicon wafer | |
| FR3036846B1 (fr) | Procede d'isolation locale entre des transistors realises sur un substrat soi, en particulier fdsoi, et circuit integre correspondant | |
| SG11202002544SA (en) | Mask blank, transfer mask, and method for manufacturing semiconductor device | |
| FR3051595B1 (fr) | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant | |
| FR3048244B1 (fr) | Procede de gravure selective d'une couche ou d'un empilement de couches sur substrat verrier | |
| JP2017139047A5 (ja) | データのリフレッシュの方法、半導体ウェハ、電子機器 | |
| GB202020038D0 (en) | Semiconductor device, and manufacturing method for semiconductor device | |
| GB2556205B (en) | Method for manufacturing thin film transistor array substrate | |
| FR3048245B1 (fr) | Procede de gravure selective d'une couche ou d'un empilement de couches sur substrat verrier | |
| EP3561855A4 (fr) | Substrat en semiconducteur au nitrure du groupe iii et procédé de production du substrat en semiconducteur au nitrure de group iii | |
| GB201706041D0 (en) | Manufacturing method and device for thin flim transistor substrate | |
| SG11202011164PA (en) | Method for manufacturing semiconductor device | |
| SG11202011945RA (en) | Method for manufacturing bonded soi wafer and bonded soi wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PLFP | Fee payment |
Year of fee payment: 2 |
|
| PLSC | Publication of the preliminary search report |
Effective date: 20161202 |
|
| PLFP | Fee payment |
Year of fee payment: 3 |
|
| PLFP | Fee payment |
Year of fee payment: 4 |
|
| PLFP | Fee payment |
Year of fee payment: 5 |
|
| PLFP | Fee payment |
Year of fee payment: 6 |
|
| ST | Notification of lapse |
Effective date: 20220105 |