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DE60314301D1 - Frequenzvervielfacher - Google Patents

Frequenzvervielfacher

Info

Publication number
DE60314301D1
DE60314301D1 DE60314301T DE60314301T DE60314301D1 DE 60314301 D1 DE60314301 D1 DE 60314301D1 DE 60314301 T DE60314301 T DE 60314301T DE 60314301 T DE60314301 T DE 60314301T DE 60314301 D1 DE60314301 D1 DE 60314301D1
Authority
DE
Germany
Prior art keywords
signal
level
combining
pairs
flanks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314301T
Other languages
English (en)
Other versions
DE60314301T2 (de
Inventor
Harald Jacobsson
Thomas Lewin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Application granted granted Critical
Publication of DE60314301D1 publication Critical patent/DE60314301D1/de
Publication of DE60314301T2 publication Critical patent/DE60314301T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Amplitude Modulation (AREA)
  • Transplanting Machines (AREA)
  • Steroid Compounds (AREA)
DE60314301T 2003-12-10 2003-12-10 Frequenzvervielfacher Expired - Lifetime DE60314301T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2003/001919 WO2005057786A1 (en) 2003-12-10 2003-12-10 A freqency multiplier

Publications (2)

Publication Number Publication Date
DE60314301D1 true DE60314301D1 (de) 2007-07-19
DE60314301T2 DE60314301T2 (de) 2008-02-07

Family

ID=34676086

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314301T Expired - Lifetime DE60314301T2 (de) 2003-12-10 2003-12-10 Frequenzvervielfacher

Country Status (8)

Country Link
US (1) US7414443B2 (de)
EP (1) EP1692765B1 (de)
JP (1) JP2007521703A (de)
CN (1) CN1879303B (de)
AT (1) ATE364259T1 (de)
AU (1) AU2003287126A1 (de)
DE (1) DE60314301T2 (de)
WO (1) WO2005057786A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7636803B2 (en) * 2006-09-28 2009-12-22 Advanced Micro Devices, Inc. Device and method for transferring data between devices
KR100811276B1 (ko) * 2006-12-29 2008-03-07 주식회사 하이닉스반도체 지연고정루프회로
JP2008192106A (ja) * 2007-02-08 2008-08-21 Ricoh Co Ltd インタフェース回路
US8014485B2 (en) * 2007-05-17 2011-09-06 Advanced Micro Devices, Inc. Techniques for integrated circuit clock management using multiple clock generators
JP2009021870A (ja) * 2007-07-12 2009-01-29 Sony Corp 信号生成装置、フィルタ装置、信号生成方法およびフィルタ方法
US7741885B1 (en) 2009-03-04 2010-06-22 Yazaki North America Frequency multiplier
US8575972B2 (en) * 2009-03-23 2013-11-05 Advanced Micro Devices, Inc. Digital frequency synthesizer device and method thereof
CN102664608B (zh) * 2010-12-28 2015-03-11 博通集成电路（上海）有限公司 频率倍增器及频率倍增的方法
KR101169059B1 (ko) * 2012-03-30 2012-07-31 주식회사 빅솔론 휴대용 단말기를 이용한 포스 단말기 및 그 시스템
JP2015149669A (ja) * 2014-02-07 2015-08-20 富士通株式会社 クロック制御回路，受信器および通信装置
US10439623B2 (en) 2017-05-30 2019-10-08 Globalfoundries Inc. Injection locked oscillator system and processes
CN110113009B (zh) * 2018-02-01 2023-05-23 长鑫存储技术有限公司 倍频电路及倍频器
US20240072829A1 (en) * 2022-08-30 2024-02-29 Apple Inc. Digital-to-analog converter with localized frequency multiplication circuits

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
JP2861465B2 (ja) * 1991-05-16 1999-02-24 日本電気株式会社 周波数逓倍回路
US5475322A (en) * 1993-10-12 1995-12-12 Wang Laboratories, Inc. Clock frequency multiplying and squaring circuit and method
KR960009965B1 (ko) * 1994-04-14 1996-07-25 금성일렉트론 주식회사 주파수 배수 회로
US5721501A (en) * 1995-07-26 1998-02-24 Kabushiki Kaisha Toshiba Frequency multiplier and semiconductor integrated circuit employing the same
US5786732A (en) * 1995-10-24 1998-07-28 Vlsi Technology, Inc. Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit
US5786715A (en) * 1996-06-21 1998-07-28 Sun Microsystems, Inc. Programmable digital frequency multiplier
JPH11163690A (ja) 1997-11-26 1999-06-18 Toshiba Corp 周波数逓倍回路
US6037812A (en) * 1998-05-18 2000-03-14 National Semiconductor Corporation Delay locked loop (DLL) based clock synthesis
US6229358B1 (en) 1999-12-15 2001-05-08 International Business Machines Corporation Delayed matching signal generator and frequency multiplier using scaled delay networks

Also Published As

Publication number Publication date
US20070159220A1 (en) 2007-07-12
EP1692765A1 (de) 2006-08-23
US7414443B2 (en) 2008-08-19
EP1692765B1 (de) 2007-06-06
DE60314301T2 (de) 2008-02-07
WO2005057786A1 (en) 2005-06-23
ATE364259T1 (de) 2007-06-15
JP2007521703A (ja) 2007-08-02
AU2003287126A1 (en) 2005-06-29
CN1879303B (zh) 2010-06-23
CN1879303A (zh) 2006-12-13

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