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DE60311138D1 - Pll mit symmetrischem quadrikorrelator - Google Patents

Pll mit symmetrischem quadrikorrelator

Info

Publication number
DE60311138D1
DE60311138D1 DE60311138T DE60311138T DE60311138D1 DE 60311138 D1 DE60311138 D1 DE 60311138D1 DE 60311138 T DE60311138 T DE 60311138T DE 60311138 T DE60311138 T DE 60311138T DE 60311138 D1 DE60311138 D1 DE 60311138D1
Authority
DE
Germany
Prior art keywords
quadrikorrelator
pll
symmetrical
symmetrical quadrikorrelator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60311138T
Other languages
English (en)
Other versions
DE60311138T2 (de
Inventor
A Sanduleanu
M Leenaerts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE60311138D1 publication Critical patent/DE60311138D1/de
Application granted granted Critical
Publication of DE60311138T2 publication Critical patent/DE60311138T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H04L7/0274—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit with Costas loop
DE60311138T 2002-11-05 2003-10-08 Pll mit symmetrischem quadrikorrelator Expired - Lifetime DE60311138T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02079608 2002-11-05
EP02079608 2002-11-05
PCT/IB2003/004467 WO2004042925A1 (en) 2002-11-05 2003-10-08 Pll with balanced quadricorrelator

Publications (2)

Publication Number Publication Date
DE60311138D1 true DE60311138D1 (de) 2007-02-22
DE60311138T2 DE60311138T2 (de) 2007-10-31

Family

ID=32309398

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60311138T Expired - Lifetime DE60311138T2 (de) 2002-11-05 2003-10-08 Pll mit symmetrischem quadrikorrelator

Country Status (7)

Country Link
US (1) US7466785B2 (de)
EP (1) EP1563605B1 (de)
JP (1) JP4549861B2 (de)
CN (1) CN1711691B (de)
AU (1) AU2003264813A1 (de)
DE (1) DE60311138T2 (de)
WO (1) WO2004042925A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497708B2 (en) * 2011-05-06 2013-07-30 National Semiconductor Corporation Fractional-rate phase frequency detector
TWI525999B (zh) * 2013-11-12 2016-03-11 智原科技股份有限公司 頻率鎖定裝置及方法
KR102222449B1 (ko) * 2015-02-16 2021-03-03 삼성전자주식회사 탭이 내장된 데이터 수신기 및 이를 포함하는 데이터 전송 시스템
US9673847B1 (en) * 2015-11-25 2017-06-06 Analog Devices, Inc. Apparatus and methods for transceiver calibration
US9979408B2 (en) 2016-05-05 2018-05-22 Analog Devices, Inc. Apparatus and methods for phase synchronization of phase-locked loops
US10439851B2 (en) * 2016-09-20 2019-10-08 Ohio State Innovation Foundation Frequency-independent receiver and beamforming technique
US11082051B2 (en) 2018-05-11 2021-08-03 Analog Devices Global Unlimited Company Apparatus and methods for timing offset compensation in frequency synthesizers
KR102817517B1 (ko) * 2020-04-20 2025-06-10 주식회사 엘엑스세미콘 데이터구동장치 및 이의 구동 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3201043B2 (ja) * 1993-01-13 2001-08-20 住友電気工業株式会社 位相周波数比較回路
US5757857A (en) * 1994-07-21 1998-05-26 The Regents Of The University Of California High speed self-adjusting clock recovery circuit with frequency detection
JPH11308097A (ja) * 1998-04-24 1999-11-05 Sony Corp 周波数比較器およびこれを用いたｐｌｌ回路
JP3209188B2 (ja) * 1998-10-14 2001-09-17 日本電気株式会社 Ｐｌｌ回路
US6853696B1 (en) * 1999-12-20 2005-02-08 Nortel Networks Limited Method and apparatus for clock recovery and data qualification
US6914953B2 (en) * 2000-12-28 2005-07-05 International Business Machines Corporation Multiphase clock recovery using D-type phase detector

Also Published As

Publication number Publication date
CN1711691A (zh) 2005-12-21
EP1563605A1 (de) 2005-08-17
CN1711691B (zh) 2010-06-02
US20060034410A1 (en) 2006-02-16
WO2004042925A1 (en) 2004-05-21
JP2006505986A (ja) 2006-02-16
EP1563605B1 (de) 2007-01-10
US7466785B2 (en) 2008-12-16
AU2003264813A1 (en) 2004-06-07
DE60311138T2 (de) 2007-10-31
JP4549861B2 (ja) 2010-09-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN