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DE60020193D1 - Mehrschichtige Leiterplatte - Google Patents

Mehrschichtige Leiterplatte

Info

Publication number
DE60020193D1
DE60020193D1 DE60020193T DE60020193T DE60020193D1 DE 60020193 D1 DE60020193 D1 DE 60020193D1 DE 60020193 T DE60020193 T DE 60020193T DE 60020193 T DE60020193 T DE 60020193T DE 60020193 D1 DE60020193 D1 DE 60020193D1
Authority
DE
Germany
Prior art keywords
circuit board
printed circuit
multilayer printed
multilayer
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60020193T
Other languages
English (en)
Other versions
DE60020193T2 (de
Inventor
Michio Horiuchi
Shigeru Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of DE60020193D1 publication Critical patent/DE60020193D1/de
Application granted granted Critical
Publication of DE60020193T2 publication Critical patent/DE60020193T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H10W70/65—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H10W70/655—
    • H10W72/07251—
    • H10W72/20—
    • H10W90/724—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE60020193T 1999-07-22 2000-07-14 Mehrschichtige Leiterplatte Expired - Lifetime DE60020193T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20742999A JP3610262B2 (ja) 1999-07-22 1999-07-22 多層回路基板及び半導体装置
JP20742999 1999-07-22

Publications (2)

Publication Number Publication Date
DE60020193D1 true DE60020193D1 (de) 2005-06-23
DE60020193T2 DE60020193T2 (de) 2006-01-19

Family

ID=16539620

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60020193T Expired - Lifetime DE60020193T2 (de) 1999-07-22 2000-07-14 Mehrschichtige Leiterplatte

Country Status (4)

Country Link
US (1) US6407460B1 (de)
EP (1) EP1071316B1 (de)
JP (1) JP3610262B2 (de)
DE (1) DE60020193T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664483B2 (en) * 2001-05-15 2003-12-16 Intel Corporation Electronic package with high density interconnect and associated methods
US6762505B2 (en) * 2001-11-29 2004-07-13 Sun Microsystems 150 degree bump placement layout for an integrated circuit power grid
JP4613590B2 (ja) * 2004-11-16 2011-01-19 セイコーエプソン株式会社 実装基板及び電子機器
JP5085296B2 (ja) 2007-12-03 2012-11-28 新光電気工業株式会社 多層配線基板および半導体装置
US9001522B2 (en) * 2011-11-15 2015-04-07 Apple Inc. Printed circuits with staggered contact pads and compact component mounting arrangements
JP5946370B2 (ja) * 2012-08-28 2016-07-06 ルネサスエレクトロニクス株式会社 電子装置
US9560741B2 (en) 2013-10-10 2017-01-31 Curtiss-Wright Controls, Inc. Circuit board via configurations for high frequency signaling
US10710509B2 (en) 2015-09-16 2020-07-14 Ford Global Technologies, Llc Collapsible storage bin for a motor vehicle
CN112528505B (zh) * 2020-12-14 2022-03-25 西南交通大学 一种指数分布型产品可靠性评估方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100194130B1 (ko) * 1994-03-30 1999-06-15 니시무로 타이죠 반도체 패키지
US5444303A (en) * 1994-08-10 1995-08-22 Motorola, Inc. Wire bond pad arrangement having improved pad density
JP3362545B2 (ja) * 1995-03-09 2003-01-07 ソニー株式会社 半導体装置の製造方法
US5784262A (en) 1995-11-06 1998-07-21 Symbios, Inc. Arrangement of pads and through-holes for semiconductor packages
US6215184B1 (en) * 1998-02-19 2001-04-10 Texas Instruments Incorporated Optimized circuit design layout for high performance ball grid array packages
JP3386977B2 (ja) * 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
JPH1167960A (ja) 1997-08-20 1999-03-09 Nec Corp 半導体パッケージとその実装基板
JP3380151B2 (ja) * 1997-12-22 2003-02-24 新光電気工業株式会社 多層回路基板
JP2000100851A (ja) * 1998-09-25 2000-04-07 Sony Corp 半導体部品及びその製造方法、半導体部品の実装構造及びその実装方法
US6242815B1 (en) * 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package

Also Published As

Publication number Publication date
JP3610262B2 (ja) 2005-01-12
EP1071316A3 (de) 2001-10-17
US6407460B1 (en) 2002-06-18
EP1071316A2 (de) 2001-01-24
EP1071316B1 (de) 2005-05-18
JP2001035950A (ja) 2001-02-09
DE60020193T2 (de) 2006-01-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition