[go: up one dir, main page]

DE3884282D1 - Makro-Struktur und Verfahren zum Herstellen von Makros für VLSI-Halbleiterschaltungen. - Google Patents

Makro-Struktur und Verfahren zum Herstellen von Makros für VLSI-Halbleiterschaltungen.

Info

Publication number
DE3884282D1
DE3884282D1 DE88107077T DE3884282T DE3884282D1 DE 3884282 D1 DE3884282 D1 DE 3884282D1 DE 88107077 T DE88107077 T DE 88107077T DE 3884282 T DE3884282 T DE 3884282T DE 3884282 D1 DE3884282 D1 DE 3884282D1
Authority
DE
Germany
Prior art keywords
macros
producing
semiconductor circuits
macro structure
vlsi semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88107077T
Other languages
English (en)
Other versions
DE3884282T2 (de
Inventor
Anthony Gus Aipperspach
Douglas Michael Dewanz
Joseph Michael Fitzgerald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3884282D1 publication Critical patent/DE3884282D1/de
Application granted granted Critical
Publication of DE3884282T2 publication Critical patent/DE3884282T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE88107077T 1987-06-19 1988-05-03 Makro-Struktur und Verfahren zum Herstellen von Makros für VLSI-Halbleiterschaltungen. Expired - Fee Related DE3884282T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/064,030 US4849904A (en) 1987-06-19 1987-06-19 Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices

Publications (2)

Publication Number Publication Date
DE3884282D1 true DE3884282D1 (de) 1993-10-28
DE3884282T2 DE3884282T2 (de) 1994-04-21

Family

ID=22053113

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88107077T Expired - Fee Related DE3884282T2 (de) 1987-06-19 1988-05-03 Makro-Struktur und Verfahren zum Herstellen von Makros für VLSI-Halbleiterschaltungen.

Country Status (4)

Country Link
US (1) US4849904A (de)
EP (1) EP0295410B1 (de)
JP (1) JPH0760442B2 (de)
DE (1) DE3884282T2 (de)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182719A (en) * 1988-06-09 1993-01-26 Hitachi, Ltd. Method of fabricating a second semiconductor integrated circuit device from a first semiconductor integrated circuit device
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5210701A (en) * 1989-05-15 1993-05-11 Cascade Design Automation Corporation Apparatus and method for designing integrated circuit modules
US5369593A (en) 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
JP2575564B2 (ja) * 1991-03-05 1997-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 自動マクロ最適順序化方法
US5225991A (en) * 1991-04-11 1993-07-06 International Business Machines Corporation Optimized automated macro embedding for standard cell blocks
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5638288A (en) * 1994-08-24 1997-06-10 Lsi Logic Corporation Separable cells having wiring channels for routing signals between surrounding cells
US5587923A (en) * 1994-09-07 1996-12-24 Lsi Logic Corporation Method for estimating routability and congestion in a cell placement for integrated circuit chip
US5798541A (en) * 1994-12-02 1998-08-25 Intel Corporation Standard semiconductor cell with contoured cell boundary to increase device density
US5631842A (en) * 1995-03-07 1997-05-20 International Business Machines Corporation Parallel approach to chip wiring
US5768146A (en) * 1995-03-28 1998-06-16 Intel Corporation Method of cell contouring to increase device density
US5764954A (en) * 1995-08-23 1998-06-09 International Business Machines Corporation Method and system for optimizing a critical path in a field programmable gate array configuration
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
JP3938220B2 (ja) * 1996-11-29 2007-06-27 富士通株式会社 大規模集積回路装置の製造方法及び大規模集積回路装置
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
JP3597706B2 (ja) * 1997-07-25 2004-12-08 株式会社東芝 ロジック混載メモリ
US6018622A (en) * 1997-09-24 2000-01-25 Sun Microsystems, Inc. Method for reducing circuit area by grouping compatible storage devices
US6247166B1 (en) 1998-06-25 2001-06-12 International Business Machines Corporation Method and apparatus for assembling array and datapath macros
JP4601737B2 (ja) * 1998-10-28 2010-12-22 株式会社東芝 メモリ混載ロジックｌｓｉ
US6301695B1 (en) * 1999-01-14 2001-10-09 Xilinx, Inc. Methods to securely configure an FPGA using macro markers
US6324676B1 (en) * 1999-01-14 2001-11-27 Xilinx, Inc. FPGA customizable to accept selected macros
US6305005B1 (en) * 1999-01-14 2001-10-16 Xilinx, Inc. Methods to securely configure an FPGA using encrypted macros
US6539533B1 (en) * 2000-06-20 2003-03-25 Bae Systems Information And Electronic Systems Integration, Inc. Tool suite for the rapid development of advanced standard cell libraries
US7024653B1 (en) * 2000-10-30 2006-04-04 Cypress Semiconductor Corporation Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD)
US6658544B2 (en) 2000-12-27 2003-12-02 Koninklijke Philips Electronics N.V. Techniques to asynchronously operate a synchronous memory
US6768684B2 (en) * 2002-01-25 2004-07-27 Sun Microsystems, Inc. System and method for small read only data
JP3741053B2 (ja) * 2002-02-18 2006-02-01 ソニー株式会社 画像処理装置
US7062740B2 (en) * 2003-05-22 2006-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for reducing design cycle time for designing input/output cells
JP2006049782A (ja) * 2004-08-09 2006-02-16 Matsushita Electric Ind Co Ltd 半導体集積回路装置のレイアウト方法
US8856704B2 (en) * 2010-11-22 2014-10-07 Industry-University Cooperation Foundation Hanyang University Layout library of flip-flop circuit
US9305905B2 (en) * 2013-09-06 2016-04-05 Micron Technology, Inc. Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
DE102021109480A1 (de) 2020-12-14 2022-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Speichervorrichtung
CN114388018B (zh) 2020-12-14 2025-09-19 台湾积体电路制造股份有限公司 存储装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961944A (ja) * 1982-09-30 1984-04-09 Fujitsu Ltd マスタスライス集積回路の製造方法
JPS59155954A (ja) * 1983-02-24 1984-09-05 Mitsubishi Electric Corp 半導体メモリ装置
US4598386A (en) * 1984-04-18 1986-07-01 Roesner Bruce B Reduced-area, read-only memory
EP0162934B1 (de) * 1984-05-14 1989-11-08 Ibm Deutschland Gmbh Halbleiterspeicher
US4724531A (en) * 1984-07-18 1988-02-09 Hughes Aircraft Company Gate array with bidirectional symmetry

Also Published As

Publication number Publication date
JPH0760442B2 (ja) 1995-06-28
EP0295410A2 (de) 1988-12-21
US4849904A (en) 1989-07-18
DE3884282T2 (de) 1994-04-21
EP0295410A3 (en) 1989-08-09
EP0295410B1 (de) 1993-09-22
JPS6481075A (en) 1989-03-27

Similar Documents

Publication Publication Date Title
DE3884282D1 (de) Makro-Struktur und Verfahren zum Herstellen von Makros für VLSI-Halbleiterschaltungen.
DE3883792D1 (de) Verfahren zum Herstellen integrierter Halbleiterschaltungen mit polykristallinen Schichten und Kontakten.
DE3861889D1 (de) Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen.
DE3575241D1 (de) Halbleiteranordnung und verfahren zum herstellen derselben.
DE3587985D1 (de) Herstellungsverfahren für integrierte Schaltungen und Anordnung.
DE3381215D1 (de) Integrierte halbleiterschaltungen und verfahren zur herstellung.
DE3381509D1 (de) Verfahren zum herstellen von halbleiteranordnungen.
DE69030843D1 (de) Verfahren zum Herstellen von Kondensatoren für integrierte Schaltungen
DE69130205D1 (de) Heizungsapparat für eine Halbleiterscheibe und Verfahren zum Herstellen desselben
DE3888937D1 (de) Verfahren zum Herstellen von integrierten Schaltungen mit FET.
DE3751920D1 (de) Isolationsverfahren für integrierte Schaltungen
DE3850624D1 (de) Verfahren zum Herstellen von Halbleiterkontakten.
DE69020802D1 (de) Verfahren zum Ausheilen von Halbleitern.
DE69030738D1 (de) Induktive Strukturen für halbleitende integrierte Schaltungen
DE68907782D1 (de) Verfahren zum herstellen von grossen halbleiterschaltungen.
DE69012611D1 (de) Verfahren zum Herstellen bipolarer vertikaler Transistoren und von Hochspannungs-CMOS-Transistoren in einer einzigen integrierten Schaltung.
ATA143383A (de) Verfahren und einrichtung zum herstellen von werkstuecken
DE3482523D1 (de) Verfahren zum herstellen eines elektrets und anordnungen.
DE69130624D1 (de) Verfahren zum Herstellen von Feldeffekt-Transistoren für integrierte Schaltungen
DE3772490D1 (de) Halbleiteranordnung sowie verfahren zum herstellen und testen derselben.
DE3579977D1 (de) Methode zum entwurf logisch integrierter schaltungen.
DE68916165D1 (de) Verfahren zum Herstellen von selbstjustierenden Metallhalbleiterkontakten in integrierten MISFET-Strukturen.
DE69012647D1 (de) Halbleiterbehandlungsvorrichtung und Verfahren.
DE3784605D1 (de) Verfahren zum herstellen einer halbleitervorrichtung und halbleitervorrichtung.
DE3886062D1 (de) Verfahren zum Herstellen integrierter Strukturen aus bipolaren und CMOS-Transistoren.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee