DE3315372A1 - Arrangement for converting an anisochronous binary input signal into an isochronous binary output signal - Google Patents

Abstract

The circuit arrangement described is used as clock adapter in the demultiplexing in plesiochronous time-division multiplex systems. The essential components of the arrangement are an elastic memory and a phase control loop, by means of which the reading of bits of the input signal out of the elastic memory is controlled. The storage space required for error-free conversion of the binary input signal into the desired output signal is reduced by inserting a controller with integrating characteristic into the phase control loop and by adding a fixed voltage to the output voltage of the comparator.

Description

Arrangement for the implementation of an anisochronous binary

Input signal into an isochronous binary output signal.

The invention relates to an arrangement for implementing an anisochronous binary input signal into an isochronous binary output signal with the others Features listed in the preamble of the claim.

Such an arrangement is used, for example, in the case of demultiplexing in plesiochronous Time division multiplex systems are used. As in an article by R. Baschke and W. Leinweber (Baschke, R. and Leinweber, W .: DSMX 2/8 - The realization of a plesiochronous Digital-Multiplexers, TEKADE Techniches Mitteilungen (1980) pp. 43-49) is, in these systems, the aforementioned arrangement has the task of a demultiplexer generated intermediate multiplex signals for further transmission to work through subsystem-compatible. In the following it is explained in more detail, what is meant by this.

When decomposing a multiplex signal with a nominal bit rate of e.g. 8448 kbit / s (this signal should be called the signal of the upper system) into four multiplex signals with the nominal bit rate of 2048 kbit / s (each of these Signals should be called the signal of a subsystem) occur at the output of the demultiplexer four intermediate multiplex signals.

A subsystem signal is obtained from each inter-multiplexed signal. Distinguish an inter-multiplexed signal and the associated subsystem signal characterized in that the multiplex signal still contains bits that are only for the Transmission in the upper system is erIcrclcrl. Such bits siritl Z.l.s.

Synchronization bits, stuffing information bits and stuffing bits. For the further Transmission in a sub-system must therefore be an inter-multiplexed signal first from the now no longer required and therefore unwanted bits are freed.

The deletion of these bits is done so that in the clock that a ZwischenmultiplexsicTn2 'is assigned, at the points a clock pulse is suppressed at which an unwanted bit occurs; then we will deal with this incomplete Clock an elastic memory clocked, at whose input the intermediate multiplex signal is created. This leaves only the desired bits of the inter-multiplexed signal transferred to the memory locations of the elastic store. This process is equivalent to a process in which an anisochronous binary signal is connected to this Signal adapted clock is written in the elastic memory.

Now to get out of the bits that are written into the elastic memory are to receive the associated subsystem signal, they are smoothed with a Smooth out the beat. The gapped clock and the smoothed clock have the same average clock frequency, namely 2048 kHz, in the numerical example given above to stay.

Further details necessary to understand the below.

specified tasks are required, should be based on the Fig. 1 will be explained. The upper part of the figure shows schematically an elastic one Binary memory BS, at whose input terminals an intermediate multiplex signal DE and a gap-filled clock TS are created. With each clock pulse of the clock TS becomes a so-called write pointer SZ advanced by one position. About the writing pointer SZ will be the desired bits of the signal DB cyclically e.g. in eight Speicherstcllen 1 to 8 of the memory BS written.

The writing pointer SZ is realized with the memory parts 1 to 8 by a Johnson counter with eight outputs, each output with the clock input a flip-flop is connected and the counter is clocked with the write clock TS.

With each pulse of the clock TS the counter gives at one of its outputs a pulse from, in such a way that successive pulses also on successive Outputs occur. In this way, the desired bits of the inter-multiplexed signal become DE is transferred to the Q outputs of the flip-flops in cyclical order.

The so-called read pointer LZ with which the States at the Q outputs of the flip-flops are queried cyclically and with a reading pulse TL can be read out and as a serial output signal DA at an output terminal of the memory BS are present.

The two measures (for reading in and out) with which each individual Storage location of the memory BS is controlled have clock frequencies that are 1/8 the clock frequency of the write clock TS or the read clock TL.

A clock TUS is used to check the status of the write pointer SZ is used, with which the bits e.g.

be written into the first memory location while checking of the read pointer LZ a clock TUL is used, with which the bits e.g. from the fifth memory location can be read out.

To the frequency ratio between the write control clock TUS and To indicate the write clock, there is a frequency divider between the two clocks in FIG Tl with the division ratio 8: 1. The same applies to the reading control cycle TUL, the reading clock TL and a divider T2.

Are the write clock TS and read clock TL as well as the two control clocks TUS and TUL are the same in terms of frequency and phase, so you can be sure that the temporal The distance between the write pointer SZ and the read pointer LZ remains unchanged. The time interval here means the time between the two points in time elapses, to which first the read pointer LZ and then the write pointer SZ or conversely, be switched to the same memory location.

In the following, the period duration is intended as the unit of measurement for this distance of the reading clock TL are used; This is equivalent to the specification in bit.

If the phase position changes between writing clock TS and reading clock TL and thus the phase position between the control clocks TUS and TUL changes also as a consequence of this the time interval between read and write pointer. Of the The distance must not assume any values if the implementation of the signal is DE in the signal DA should take place without errors. Are e.g.

Read and write pointer simultaneously with the same memory location connected, the output signal DA contains errors.

Two important parameters of the elastic store BS are therefore the Details of how far a clock edge of the write control clock TUS extends in both time directions the corresponding clock edge of the read control clock may remove TUL without Errors occur in the implementation. In the case of a memory BS, the one indicated above Type of construction is inert, signal transit times can initially be neglected - a rJaktflanke of the write control clock rlllS up to 4 bits before and up to 4 bit behind the corresponding edge of the read control clock TUL.

These maximum permitted phase deviations are a consequence of the specific internal structure of the elastic store BS, e.g. as an integrated module is available and its internal circuit features have therefore not been changed can be. The information on the maximum permitted phase deviations are therefore to be regarded as given. Due to differences in runtime and required holding times can determine the maximum permissible deviations for a memory with eight memory locations e.g. 4.24 bits in one direction and 3.19 bits in the other time direction. The permitted deviations become larger, the more storage locations in the memory BS contains. The phase deviations that actually occur may exceed the permitted limits do not exceed if the implementation is to remain error-free.

Elastic storage can have different numbers of storage locations getting produced. In a specific application, the choice must be made for reasons of cost or to limit the power loss to a memory with the smallest number of storage locations fall in which there is still an error-free conversion of a clock to a broken one TL bound signal DE into an isochronous output signal DA is possible. To the Making a well-founded choice for a certain number of storage locations must first be estimated which actual phase deviations are maximum between the write control clock TUS and the read control clock TUL can occur.

It must then be checked whether the estimated deviations are smaller than the maximum permitted deviations between Write and read control clock.

As FIG. 1 shows, the reading clock TL is set with the aid of a phase-locked loop PLL obtained from the Schr Dtak.t TS. The phase locked loop, whose comparator V the two control clocks TUS and TUL are supplied, regulates the read control clock TUL in such a way that its edges largely coincide with the edges of the write control clock TUS match. An exact match cannot be made for a number of reasons achieve how the following considerations should make plausible: The control loop PLL 1 is a first approximation of a linear control loop with a proportional controller.

Such control loops never regulate their deviations to zero, i.e. there is always a phase difference between the two control clocks TUL and TUS. This phase difference cannot be specified precisely from the outset because he of the working frequency and the manufacturing tolerances of the oscillator VCO depends; however, its maximum value can be estimated. To this one, among other things phase deviation dependent on the oscillator / CO, there is a further deviation, which result in general from the intended effect of the phase-locked loop PLL results and only depends on the write clock TS or the write control clock TUS. The phase-locked loop PLL should namely with an irregular sequence of the clock edges of the Write control clock TUS a read clock TL and thus a read control clock TUL with the most regular possible edge sequence. The desired beat with the regular The edge sequence results from the (irregular) write control clock TUS through Averaging over the flank positions. This averaging is used by the phase-locked loop PLL appropriate measurement of its time constant. The through the The read control clock TUL generated by the phase-locked loop PLL according to FIG. 1 accordingly consists of the middle write control clock TUS, shifted by one from the oscillator, among other things VCO dependent phase. Therefore, the actual deviation of an edge is cies Write control clock TUS from the corresponding edge of the read control clock TUL from the current deviation of the write control clock TUS from its mean value TUS and from the above-mentioned deviation that is dependent on the oscillator VCO, among other things.

The overall result is that the actual phase shift between The write and read control clock will be less than four bits in both directions, for example, a memory with eight memory locations can be used if it has the maximum permitted deviations in both directions are 4 bits.

However, the actual displacement in one direction is a maximum E.g. 5 bits and in the other direction a maximum of 3 bits, the mentioned memory can no longer be used in the manner outlined above, as cases occur in which read and write pointers overtake each other, the output signal so it will contain errors.

One therefore has to go to a memory BS with a larger number of memory locations grab in order to be able to absorb the 5-bit large deviation to one side.

For the compensation of the phase deviation to the other side stands however, in the example, more memory space is available than is required. One Such incomplete utilization of the elastic store BS always occurs before, if the sum of the actually occurring in the positive and negative time direction, maximum phase deviations is smaller than the corresponding sum of the maximum permitted deviations, but the actual deviations to one side are larger than the left.

To the actual deviations between the edges of the write control clock TUS and the read control clock TUL also carry the previously unmentioned phase jitter of the write clock TS. The jitter increases the actual maximum deviations in both directions by the same amount. Therefore the memory utilization is optimal, if - initially without taking the jitter into account - the distances between the actually occurring, maximum deviations and the maximum allowed in both directions are the same, because the then still unused memory space is completely for the collection of the jitter is available. As a rule, the conditions for full However, the available memory is not used.

The invention is based on the object of an arrangement of the above to change said type so that the elastic memory as few memory locations as possible and the available memory ram can be fully used.

In an arrangement mentioned at the outset, this task is achieved by the Measures solved, which can be found in the characterizing part of the claim.

The invention is based on the figures and an exemplary embodiment are explained in more detail.

It shows: FIG. 1 a known arrangement for the cen ci ings mentioned Purpose, Figure 2 shows the structure according to the invention of a phase-locked loop of an initially mentioned arrangement, Figure 3 and Figure 4 diagrams to clarify the oil operation of the execution example.

The embodiment of the invention differs from that known circuit according to FIG. 1 by components in the phase-locked loop PLL (Fio. 2). A voltage adder AU becomes the output voltage of the comparator V des Phase-locked loop PLL adds a constant voltage U; an integrating controller I generates the control voltage for the oscillator VCO from the sum voltage. on the value of the voltage U will be discussed further below. First of all, the phase-locked loop gets - as far as it can be viewed as linear - by inserting the integrating Controller I has a different control behavior.

As is well known, such a control loop regulates the system deviation to zero, if the reference variable is constant. According to the above, the reading control clock is therefore correct TUL coincides with the middle write control clock TÜS. The one mentioned above, below other phase shift between these two clocks that is dependent on the oscillator VCO not applicable. This means that it is also not required when assessing the actual occurring Phase differences between corresponding edges of the write and read control clock. This in turn has the consequence that the maximum permitted phase deviation and thus the required storage space may be smaller.

The voltage U makes the read control clock 1UL compared to the write control clock TUS postponed by a fixed phase dependent on U.

To make it clearer what factors determine the value of the tension U depends, through which the full memory utilization is achieved, the Weo should be closer are described, the from the gap-laden write clock TS to a statement about carries the value of the voltage U.

As already mentioned, the gaps appear in the write clock TS on the Places at which the associated intermediate multiplex signal DE bits of the upper system signal which should no longer occur in the subsystem signal. It follows from this, that the distribution of the gaps in the write clock from the frame structure of the upper system signal depends and repeats itself periodically with the frame duration. The periodicity will interrupted by an additional gap that occurs exactly when the intermultiplexed signal DE contains a stuff bit. If the frame structure is known, the Specify the write clock TS with gaps exactly. In the numerical example mentioned at the beginning the clock TS has 205 or 206 clock edges per frame duration, depending on whether the associated Intermediate multiplex signal contains a stuffing bit or not.

With the write clock TS, aeT write control clock TUS can also be specified, i.e., the edge positions of the write control clock TUS are also a consequence of the frame structure. In order to determine the phase deviations between aem write control clock TUS and the read control clock TUL can occur solely on the basis of the frame structure, only the mean write control clock TUS needs to be calculated.

If the jitter is neglected, the mean write control clock is correct TÜS matches the read control clock TUL if a control loop with an integrating Controller is used and the voltage U assumes the value O volts.

In this calculation, the mode of operation of a phase-locked loop is used simulated with an integrating controller.

Fig. 3 serves to clarify the calculation process.

Diagram a in FIG. 3 shows the course with solid lines of the phase angle # for an excerpt from the write control clock TUS. The associated Clock edges of the write control clock TUS are entered in diagram b. To the Phase angle of the read control clock TUL under the conditions given above To get this, the polygon in diagram a is to be approximated by a straight line that successive patches of area between the polygon and the searched Straight lines are the same size.

From this straight line drawn as a broken line in diagram a is, the position of the clock edges of the read control clock TUL can be read. These Clock edges are shown in diagram c; their location is indicated by the points on the Determines straight lines of diagram a, the ordinates of which are a multiple of 2mt.

By comparing the diagrams b L 'and c, the Phase difference between the flar! Ke.

of the read control clock TUS and the write control clock TUL in bit determine.

What is the maximum phase difference between the edges of these two Cycles occur solely due to the frame structure at a voltage value of U = 0 volts karl. , shows diagram a of FIG. 4. A multislex signal was used for the calculations based on the nominal bit rate of 139264 kbit / s as the main system signal, namely with a frame structure as defined in the CCITT recommendation G. 751 is.

In diagram a of FIG. 4, the upper part shows a section the read control clock TUL calculated without the influence of jitter. The cutout has the approximate length of a period of this clock. Starting with the one drawn The (positive) clock edge is an area under the cutout for both time directions entered in which the clock edges of the write control clock TUS according to the calculation can lie; the numbers entered are in bits.

A maximum of one edge of the write control clock TUS can only be due to the frame structure of the corresponding edge of the read control clock TUL by yl = Lead 2.67 bits or follow it at a distance of y2 = 2.35 bits.

Diagram b of FIG. 4 shows a clock edge of the read control clock TUL the maximum permitted deviation of the write control clock TUS for both time directions. In the negative direction this deviation is xl = 4.24 bits and in the positive direction x2 = 3.19 bits. Come to the framework-related softening after If the jitter-related deviations are added to diagram a, these may - like a A comparison of diagrams a and b shows - highest: s 3.19 bit - z ,, 5 bit = 0.84 bit in both directions, because the permitted deviations for larger jitte would be exceeded in the positive direction. In the negative time direction, however, would exist an unused difference between the actual deviations and the permitted ones of 0.7 bit.

If the value of the voltage U is now selected in such a way that the read control clock TUL compared to the write control clock TUS by Z - x2 + y2 y2 -y1) bit = 4.24 - 3.19 + 2.35 - 2.67 bit 2 is shifted, the maximum frame-related deviations have the same distance from the maximum permitted deviations in both directions, namely 1.21 bit. Instead of ü, 84 bits are now used - when using the same Memory - 1.21 bits per time direction available to absorb phase jitter. The relations that arise after the phase shift of the read control clock TUL by 0.37 bits are shown in diagram c of FIG. The upper part shows again an excerpt from the read control clock TUL, its positive edge compared to the point in time, which is the middle position of the edges of the write control clock TUS indicates that it is shifted by 0.37 bits. The lower part of diagram c gives again indicate the areas within which the egg-permitted deviations between corresponding There are edges of the clocks TUS and TUL. After the phase shift of the read control clock TUL is around 0.37 bit the entire range of framework-related deviations in the middle of the area that is determined by all e @@ autte deviations.

The exact value of the voltage C, which is the phase shift of C, 37 bit, depends on the properties of the phase comparator V. For Phase shifts of the type described here are the necessary voltages in terms of amount in the order of 0.5 volts.

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Claims (1)

Claim notification for the implementation of an anisochronous binary Input signal es (dz) into an isochronous binary output signal (DA) where A) the binary values of the input signal (DE) with one adapted to this signal (DE) Write clock (TS) written cyclically in n storage locations of a binary memory (BS) B) the binary values written into the binary memory (BS) are cyclically included a reading clock (TL) can be read out, C) the reading clock (TL) from the writing clock (TS) is obtained by smoothing with the aid of a phase-locked loop (PLL), D) dem Phase comparator (V) of the control loop (PLL) the write clock reduced in the ratio n: 1 as the write control clock (TUS) and the read clock, which is reduced in the same ratio is supplied as a read control clock (TUL) and with the write control clock (TUS) written into a first predetermined memory location of the binary memory (BS) and with the read control clock (TUL) a second predetermined memory location is read out, whereby, due to the structure of the memory (BS), the clock edges of the write control clock (TUS) those of the read control clock (TUL) by a maximum of xl bit ahead or lag behind by x2 bits without errors in the implementation of the input signal (DE) occur in the output signal (DA), and the edges of the write control clock (TUS), due to the non-periodic position of the clock edge of the write clock (TS), from its middle edge lsoe in negative Time direction maximally un yl bit and ir. Positive time direction maximally by y2 bit different, characterized in that E) that at the output of the phase comparator (V) an adder (AU) is provided to I output voltage of the comparator (V) a constant voltage (U) added, F) that between the adder (AU) and the voltage-controlled The oscillator (VCO) of the phase-locked loop (PLL) is a controller with I behavior (I), with which the output voltage of the comparator, which is dependent on the control deviation (V) and the constant voltage (U) are integrated, G) that the value of the constant Voltage (U) is dimensioned so that the read control clock (TUL) compared to the write control clock (TUS) experiences a phase shift of the size (xl - x2 + y2 - yl) bit er-2, where the time direction of the phase shift by the sign of this quantity is determined.