DE3033351A1 - CMI coder for digital transmission system - uses flip=flops and NOR and OR logic gates - Google Patents

Abstract

The CMI coder for a digital transmission system uses a D-type flip-flop with its D input coupled to the coder input and its Q output coupled to the J and K inputs of a JK type flip-flop. The second output of the first flip-flop is coupled to a NOR gate also receiving the Q output of the second flip-flp. A second D type flip-flop receives the output of the NOR gate with its Q output fed to a second NOR gate coupled to the coder output via an OR gate. A further gating logic comprising NOR and OR gates is used to supply clock pulses fed to the coder clock input to the clock inputs of the previous flip-flops and logic gates. The coder can be used for pulse code modulation in a digital transmission system.

Description

CMI encoder

The invention relates to a CMI encoder having a first D flip-flop, the D input of which is connected to the encoder input, and with a JK flip-flop, its J input and its K input with the Q output of the first D flip-flops are connected.

Such an encoder is from the Preliminary Service Manual, 3762A, Data Generator, Hewlett Packard, pp. 8-16 and 8-51.

In the case of digital transmission systems, the implementation becomes more uniform Interconnection and distribution levels from the International Telegraph and Telephone Consultative Committee for the individual hierarchy levels in the CCITT Orange Book, Vol. III-2, International Telecommunication Union, Geneva, 1977 recommended very specific interfaces. the Signal type or coding and the signal form of these interface signals are in corresponding CCITT recommendations. For the 140 Mbit / s interface, The CMI code (coded mark inversion) is specified in Recommendation G.703 (pages 402 up to 405).

The CMI code is a two-stage NRZ code (non-return to zero), at which a binary zero independent of the previous bit through a negative state in the first half and a positive state in the second half of the bit interval is pictured. A binary one is alternated by a positive and a negative state shown. This coding law Fig. 1 shows. In this, B denotes a binary code, A1 and A2 the level of the CMI code and t denotes the Duration of a bit interval.

An essential property of the CMI code is that after a negative edge occurs at the latest three binary characters in the CMl-coded signal.

The above-mentioned recommendation G.703 gives the results from FIGS. 2 and 3 apparent tolerance conditions for the pulse shape of the output signal. These leave for the negative edges of the CMI signal - because of the derived from it Clock signal - only a very small temporal jitter (maximum + 100ps). For the positive edges this jitter can take on larger values (max. + 350ps or + 500 ps). The dashed lines show the nominal impulses.

The object of the invention is to implement a CMI encoder that fulfills this tolerance scheme and also does not require any adjustment work in the test field.

Starting from the CMI encoder of the type described in the introduction this object is achieved according to the invention in that a first NOR gate is provided whose first input is connected to the Q output of the JK flip-flop and its second The input is connected to the output of the first D-flip-flop, that a second D-flip-flop is provided whose D input is connected to the output of the first NOR gate is that a second NOR gate is provided, whose first input to the Q output of the second D flip-flop is connected so that a first OR gate is provided, its first input to the output of the second NOR gate and its output are connected to the encoder output that a third NOR gate is provided, its first entrance with a clock input and the dynamic Inputs of the first D flip-flop and the JK flip-flop and its output with the dynamic input of the other D flip-flop and the second input of the second NOR gate are connected and the second input is open that a second OR gate is provided, the first input of which with the first input of the third NOR gate is connected and the second input is open that a third OR gate is provided, the first input of which with the second input of the first NOR gate and its second input connected to the Q output of the JE flip-flop are that a fourth NOR gate is provided, the first input to the output of the second OR gate, whose second input is connected to the output of the third OR gate and whose output is connected to the second input of the first OR gate, that a fourth OR gate is provided, the inputs of which correspond to the inputs of the fourth NOR gate are connected in parallel and that a fifth NOR gate is provided, its first input with the output of the fourth OR gate and its output wired or to the output of the fourth NOR gate and to the second input of the first OR gate are connected and the second input is open.

It is advantageous if the third NOR gate and the second OR gate on the one hand and the fourth NOR gate and the fourth OR gate on the other hand are realized by OR gates in ECL technology, which have an additional inverting Output and have the same transit times between the inputs and outputs.

The invention is explained in more detail below with the aid of an exemplary embodiment explained.

FIG. 4 shows a CMI encoder according to the invention, FIG. 5 shows a Pulse diagram for the encoder of Figures 4 and 6 shows a summary of one NOR gate and an OR gate to an OR gate with an inverting and a non-inverting output.

The inventive CMI encoder according to FIG. 4 contains between the Input E and the output A D flip-flops D7 and D2, a JK flip-flop JE, NOR gate N1, N2, N4 and N5 and. OR gates 01, 03 and 04. The clock supply contains one Clock input T, a NOR gate N3 and an OR gate 02.

al to a6 show the circuit points in FIG. 4 and the circuit points in FIG. 5 impulses occurring at these switching points.

A binary signal E is applied to input E and with a 140 MHz clock T taken over by the D flip-flop D1.

The pulse a1 appears at its Q output. When this signal is on logic "1" is, the signal changes a2 at the Q output of the JK flip-flop JK. his logical state with every positive clock edge. As long as the signal a1 is logical "0" is, the signal a2 retains its logical state. Every second Even one-bit of the signal a1 occurs at the output of the NOR gate Nl in the pulse a3 a positive pulse. For every odd-numbered Sins bit of the signal al becomes at the output of the OR gate 03 a negative pulse im Pulse a4 delivered. The signal a3 appears at the output of the D flip-flop D2 in the pulse aS by half a clock period delayed and is linked to the inverted clock T in the NOR gate N2. That The output signal of the NOR gate N4 is matched with the output signal of the OR gate 04 wired-or-linked, which is additionally delayed by, the NOR gate N5. By the latter is avoided that after the OR operation of the two signals a6 and a7 in output signal A at output A pulse peaks occur.

As can be seen from the timing diagram in FIG. 5, all negative edges of the CMI signal at output A due to the link with the inverted Clock T generated in NOR gate N2. If the negative edges of the clock signal T are jitter-free are offered, the negative edges of the CMI signal are also jitter-free, since it is assumed that the propagation time of the signals through the NOR gate N3, through the NOR gate N2 and through the OR gate 01 is constant. The positive flanks of the CMI-coded 11Einsen1, are also affected by the negative edges of the clock signal T derived, so that these are also in a rigid phase relation to the negative There are edges of the CMI signal. The positive edges of the CMI-coded "zeros" however, are derived from the positive edge of the clock. By varying the duty cycle of the clock can thus determine the position of the positive edge of the Shift CMI encoded zeros. In the test field, therefore, only the duty cycle has to be of the clock T are set such that the pulse schemes according to FIGS. 2 and 3 are fulfilled. Further adjustment work does not occur.

6 shows an OR gate G1 with one inverted and one non-inverted Output, as it replaces the NOR gate N3 and the OR gate 02 as an ECL component can.

3 claims 6 figures

Claims (3)

Claims 1. CMI encoder with a first D flip-flop whose D input is connected to the encoder input and to a JK flip-flop whose J input and its K input connected to the Q output of the first D flip-flop are, characterized in that a first NOR gate (N1) is provided, whose first input with the Q output of the JE flip-flop (JK) and its second input are connected to the output of the first D flip-flop (D1) that a second D flip-flop (D2) is provided, the D input of which is connected to the output of the first NOR gate (N1) is connected that a second NOR gate (N2) is provided, the first input of which is connected to the 'Q output of the second D flip-flop (22) that a first OR gate (01) is provided, the first input of which is connected to the output of the second NOR gate (N2) and its output are connected to the encoder output (A) that a third NOR gate (N3) is provided, the first input of which is connected to a clock input (T) and the dynamic inputs of the first D flip-flop (D1) and the JK flip-flop (JK) and its output (T) with the dynamic input of the second D flip-flop (D2) and connected to the second input of the second NOR gate (N2) and its second input is open, that a second OR gate (02) is provided, whose first input is connected to the first input of the third NQR gate (N3) and whose second entrance is open, that a third OR gate (03) is provided, the first input of which is connected to the second input of the first NOR gate (N1) and its second input connected to the: output of the JK flip-flop (JK) are that a fourth NOR gate (N4) is provided, the first input with the output of the second OR gate (02), the second input of which with the output of the third OR gate (03) and its output with the second input of the first OR gate (01) are connected so that a fourth OR gate (04) is provided, whose inputs are connected in parallel to the inputs of the fourth NOR gate (N4) and that a fifth NOR gate (N5) is provided, the first input of which with the Output of the fourth OR gate (04) and its output wired or with the output of the fourth NOR gate and to the second input of the first OR gate (01) are connected and the second input is open (Fig. 4). 2. CMI encoder according to claim 1, characterized in that the third NOR gate (N3) and the second OR gate (02) on the one hand and the fourth NOR gate (N4) and the fourth OR gate (04) on the other hand by OR gates (G1, G2) in ECL technology are implemented, which have an additional inverting output and the same Have transit times between the inputs and outputs (Fig. 6). 3. CMI encoder according to claim 1 or 2, g e k e n n e 1 c h n e t is used in a 140 Mbit / s interface of a message transmission system for pulse code modulation.