DE2811032A1 - Tuning circuit for radio receiver - has microcomputer and two memories holding tuning words and binary addresses - Google Patents

Abstract

The tuning circuit, for a radio receiver, has a first memory retaining digital tuning words depending on a binary address and a second memory retaining the selected tuning words and the addresses from the first memory. A microcomputer selectively changes the tuning words stored in both memories. A converter converts the tuning words held in the second memory into analog voltages which are then used to set the receiver's frequency.

Description

Arrangement for tuning a radio receiver

The invention relates generally to tuning a radio receiver and in particular to tune a television receiver using a Permanent memory for storing binary tuning words with the help of a control circuit be electrically updated with the construction of a microcomputer0 Developed so far electronic channel tuning systems were not so flexible that they could be used for a variety different types of televisions could be applied, for example Certain previously developed systems required extremely uniform capacitance tuning diodes for the channel tuning, which is insufficient tolerances with the conventional Variations between individual capacitance diodes allowed. More so far developed Systems were not modular enough to allow the selection of different ones Channel access types or from channel displays.

Furthermore, there were previously developed electronic channel tuning systems not sufficiently economical to manufacture and they required wasteful ones printed circuit boards or other inefficient manufacturing processes to build. For example, certain known systems have required expensive potentiometers for each channel that should be tuned to. In addition, previously developed electronic television voting systems do not adequately newer regulations, according to which a television tuner has comparable skills and quality when tuning must have on VHF stations and on UHF stations. In particular, made such possible known tuning systems do not select exact UHF channels, and even the simple one It was not possible to change selected UHF channels.

A major disadvantage of the channel tuning units in television receivers, was the inability to electronically program and save tuning voltages under all operating and non-operating conditions without the use of an auxiliary power source or a mechanically programmed memory. Existing electronically tunable Tuners made use of special electronic circuitry to provide tuning voltage information program in non-persistent memories, these being non-persistent memories Batteries as supply energy in the event that the main energy source is disconnected required. The batteries are undesirable as they are additional for the manufacturer Mean costs, and they pose a long-term risk to the tuning voltage, if they fail with the main energy source disconnected. The loss of memory contents because of a Battery failure can occur when bad Battery connections are in place if the batteries are corroded or if the battery drain is too high.

Other tuning systems make use of potentiometers for maintenance The channel tuning voltage is used but these systems are also undesirable because they cannot be changed electronically and for each channel to be tuned need a potentiometer, According to the invention, the undesirable properties by using a permanent memory matrix in DIFMOS technology for storage of the channel tuning voltages eliminated 0 Die. Permanent storage matrix in DIFMOS technology (MOS technology with double injection and gate electrodes that are not fixed in terms of potential) can be changed electronically, and it is for a storage time of over a hundred Years with disconnected supply energy. The control circuit for the System makes use of a microcomputer structure to allow user input Control variables are integrated and the signals are generated that are required for access to the DIFMOS permanent storage matrix and for changing its content are required0 A main advantage of this type of control circuit compared to the solution with a special control circuit, the simplicity with the system requirements is different Manufacturer by simple reprogramming of the algorithm of the instruction memory calculation can be worn.

With the help of the invention, an electronically programmable Television tuning arrangement with a permanent memory matrix for Save on computer binary voting words are created. The one to be created with the help of the invention electronically variable tuning arrangement for a radio receiver should be from make use of a microcomputer, eliminating the need for a special control circuit is needed.

Furthermore, devices for electronic updating of binary Tuning words for a selected channel when tuning a television receiver and for storing the updated binary voting words in a persistent storage matrix be created. The arrangement to be created should be a binary voting word accordingly a selected UHF or VHF channel within the limits of a binary minimum and generate maximum words stored in a memory array.

A television tuning system is described which has a permanent memory with direct access for storing digital voting words that are created using a Control circuit can be electronically updated with the construction of a microcomputer. To update a 15-bit binary word in a persistent storage matrix, a 5-bit binary address word is generated. The 15-bit binary word contains 14 bits, the correspond to a voting word for the selected channel, as well as the most significant 15th bit that serves as a jump indicator. The 20 bits are in three shift registers stored in the data input / output circuit, namely in a 5-bit address buffer, a 1-bit jump buffer and a 14-bit data buffer register.

The 14-bit tuning word is used in a data hold comparator for the Pulse duration modulator generator entered.

An analog circuit results in the voltage conversion of the digital output signal of the pulse duration modulator generator proportional to the tuning word for the application to the varactor diode l'uner of the television set to a selected frequency.

The binary voting word is used during the voting of the arrangement of a microcomputer to obtain an updated voting word or scaled down. The binary voting word is made using the same microcomputer written to or read from permanent memory.

The binary 14-bit voting word is either due to an external Control by the user or on the basis of a vote by the automatic Frequency control (AFC) updated. The voting word is used in every operating mode enlarged within the limits of a binary minimum and maximum tuning word or scaled down, which is stored in a permanent storage array, In the fixed storage array incremental values and coordination time limits are also saved 0 An arithmetic unit with a random access cache file, two 1 4-bit working registers, and a 1-bit full adder forms the device for performing calculations for the voting arrangement.

An 8-bit program counter supplies the binary address for commands in the 8x256 instruction read-only memory9 that addresses the PLA decoding unit, which is a Command generator results. The PLA decoding unit results in 26 AND operations and 12 OR linkage In addition, a 12-to-1 Status entry switch provides the required status display for 12 external control elements. These Input signals are detected by a 1-bit status hold circuit.

The tuning arrangement is divided into two main components: the Permanent memory as well as the digital-to-analog converter with control circuits. The channel addressing and varactor band selection is made using a rotary switch arrangement causes. A rotary switch arrangement was used for the construction of the exemplary embodiment used, but designs with permanent storage for addressing and band selection were also used which could also be easily assembled. The tuning voltage interface between the digital-to-analog converter and the varactor diodes makes for achieving the summation for the frequency control (AFC) and for the UHF tuning of conventional oscillator and amplifier buffer circuits use.

The invention will now be explained by way of example with reference to the drawing. 1 shows a functional block diagram to illustrate the invention in a television receiver, Fig.2a and 2b are detailed circuit diagrams of the input buffer register in the data input / data output circuit, Fig.3a and 3b are the exact circuit diagrams ROM constant file and the associated addressing circuit, Fig. 4 a detailed circuit diagram of the coding unit for the automatic channel shift, Fig. 5a to 5d are precise circuit diagrams of the command memory of the program counter and of the microprogram counter Fig.6a to 6d exact circuit diagrams of the programmable Logic field (PLA) for the commands, Fig. 7a and 7b, detailed circuit diagrams of the status input switch Fig. 8a to 8d are precise circuit diagrams of the arithmetic unit, Fig. 9a and 9b are precise circuit diagrams of the pulse duration modulator generator, Fig. 10a and 10b exact circuit diagrams of the analog circuit, Fig. 11a to 11h precise structural diagrams of the microcomputer arrangement, Fig.12 Circuit diagram of the tuning voltage amplifier and equations for calculating Binary words corresponding to the tuning voltages and Fig. 13A to 13L flow charts to illustrate the command algorithm for the persistent memory tuning arrangement.

An embodiment of a tuning arrangement can be better understood, if the requirements placed on such an arrangement are briefly described.

Fine tuning up or down is done with the help of a Rocker switch achieved, which has an off position in the middle. A closed one Position of the switch leads to an incremental switching of the tuning voltage with a Speed from 2 to 8 steps per second. The fine-tuning control works on the coordination in VHF operation and in UHF operation.

UHF programming is achieved by pressing the control button of a Potentiometer is pressed and the pointer on the button points to the desired number of channels is rotated.

When the button is pressed, a contact is made to ground. Of the Button is spring biased to the outer position; he can not be rotated when it smells is pushed inwards. That about UHF programming The potentiometer used has about 30 turns. The user can use this potentiometer and also fine-tune a UHF station with a fine-tuning rocker switch make.

The UHF fine-tuning limit should be at + 128 steps from the in the permanent memory matrix with direct access stored binary word are what only applies if the fine-tuning rocker switch is used. If the user keep the rocker switch in the same position after these 128 steps holds, then the tuning voltage reverses its direction of change and takes in the other direction by 256 steps until it reaches its other limit value, in which a new direction reversal takes place 0 The storage and the memory require about 240 milliseconds. The binary tuning voltage word and a jump signal are stored when the device is switched off. if a tuning control for the channel jump button has been operated while the channel is addressed, the tuning voltage and the jump signal are also stored in memory when a channel change occurs An AFC shutdown inter-channel pulse occurs between two adjacent channel positions, the pulse occurs, when a switch contact is briefly connected to ground The duty cycle of the The pulse is approximately constant against the speed of rotation of the channel selection button. The duty cycle is made up of a proportion of 25% with the contact closed and from a share of 75% with an open contact together 0 The binary input address is sent at the end of a write time or 48 to 68 milliseconds after receiving the last interchannel pulseD whichever occurs later9 sampled and held0 A user-programmable channel jump ° output signal is used. The user makes use of a push button to change the state of this signal0 Die The arrangement has been designed for a capacity of 20 channels. These channels contain 12 dedicated VHF channels and eight unassigned UHF channels. In VHF = operation is of a solution with a permanent storage and a permanent storage with random access used to limit fine-tuning. The read only memory and the random access memory result in a 14-bit tuning word and a 1-bit jump identifier.

The random access memory contains 8-bit tuning words with jump flags. The arrangement is designed so that the least significant bit of the 8-bit tuning word for each VHF channel can be reprogrammed so that it is somewhere from the least significant bit position to the seventh bit of a 14-bit tuning word appears. In UHF operation, the random access memory should have a capacity of 14 bits for the tuning words plus 1 bit for the jump identifier.

The block diagram of Figure 1 shows the use of a microcomputer executed solution of a tuning arrangement for a television receiver. The television receiver 2 includes a selector switch 26 for generating an address for that in the microprocessor circuit 4 included permanent storage matrix. A more detailed block diagram of the structure of the Permanent storage matrix and the addressing arrangement is given in F.11a. In a Embodiment, the permanent memory consists of a memory matrix in DIFMOS technology (MOS technology with double injection and gate electrodes that are not fixed in terms of potential). The retention of data without supply energy is achieved by storing charge achieved in a field of gate electrodes which are not fixed in terms of potential. Every in terms of potential not fixed gate electrode in the memory matrix can through Injection of electrons or holes from an avalanche plasma charged or discharged formed in two special injector structures in each bit.

When such a non-pinned gate electrode is charged once it stays charged almost indefinitely if not on purpose is discharged by reprogramming. The decay rate of a charge on a potential non-pinned gate electrode was given a value less than 1% of the initial value per Time decade at Measured at 85 ° C. In the described embodiment becomes a 32-bit solid-state non-volatile memory with random access of the X-929 A of the Texas Instruments company used.

however, other permanent storage devices can also be used here Descriptive arrangement can be used via a data input / data output circuit become digital tuning words corresponding to the UHF and VHF channels from memory read and written to memory. This data input / output circuit Contains temporary storage registers for the 5-bit channel address, the 1-bit jump indicator and the 14-bit voting word. The tuning word is used in the pulse width modulator comparator loaded, in which a pulse width modulator counter and a pulse width modulator generator Generate digital output signals that are proportional to the binary tuning word. These digital output signals are fed into an analog circuit from an operational amplifier for conversion into the analog voltage supplied, which is to be applied to the Kapazitäsdioden tuner of the television receiver is required to tune to the selected channel.

The channel shift encoder is used to normalize the bit weighting of the incremental value for the selected VHF channels. The normalized binary word is fed to the micro program counter so that shift control signals for the various Shift register of the tuning circuit can be generated in VHF mode.

Commands given by the user are entered into the arrangement with the aid of the Input logic and the status hold circuit read. This is a device for Detecting a status change at the input switches during a voting function, so that the arrangement can be changed to the last command entered. the Change of state is determined with the help of a status holding circuit, the one loads new address from the instruction memory into the program counter.

The program counter supplies one of 256 instruction addresses to the instruction read-only memory. The instruction read-only memory addresses the constant memory matrix, the upper and lower ones Limit values for the VHF and UHF channels, incremental values for the VHF and UHF coordination, time incremental values, Contains write time values and maximum time values. The instruction read-only memory also addresses the command decoder formed by a programmable logic array (PLA), the contains a decoding option for 26 AND functions and for 12 OR functions.

The constant memory matrix transfers the data to an arithmetic unit, the two working registers, a 1-bit full adder and one from a random access memory contains formed cache file. The arithmetic unit enables the implementation the enlargement and reduction of the voting words, it ensures writing times and gives time-out functions. The new binary tuning word from the arithmetic unit is loaded into or read from the data input / output circuit. at all operating options of the arrangement to be described here are the individual selected channels both in VHF mode and in UHF mode binary tuning words in the permanent memory matrix with direct access for addressing saved when selecting a channel.

In Figures 2a and 2b is that formed by the input buffer registers Data input / data output circuit shown in more detail. As an address buffer is a 5-bit serial register 230 is provided in addition to two D flip-flops 232 and 254. A 3-to-1 encoder 236 serves to transfer data into the as an input data buffer Acting 14-bit serial registers 234a - 234b. The ones stored in the input data buffer Data are stored in parallel in the 14-bit serial register serving as a data holding circuit 238a-238b loaded, its output signal in parallel in a 14-bit serial register is loaded, which serves as a pulse duration modulated hold circuit. The D flip-flop 232 acts as a 1-bit jump buffer for the most significant bit of the tuning word.

Am an exact circuit diagram of the address decoder and that of a read-only memory The constant file formed is shown in FIGS. 3a and 3b. For addressing the 32x14-bit constant file 264a-264b formed from read-only memory decoded five bits from the address generator and four bits from the instruction read only memory. The output of the constant file is loaded into a 14-bit B working register.

The encoder for automatic channel shifting for normalization the VHF tuning is shown in more detail in the circuit diagram of FIG. The four Least significant output bits are fed to an encoder of the microprogram counter. There are two series shift registers for transferring data in the decoding operation 100 and 102 are provided.

The instruction permanent memory, the program counter and the microprogram counter are shown in more detail in Figures 5a to 5d. The 8x256-bit instruction memory 286a -286b is addressed by the 8-bit program counter 290a-290b.

The 8-bit = program counter is divided into two series registers, the contain the four most significant bits and the four least significant bits. the Least significant bits are taken directly from the 8-bit instruction program word from the instruction read-only memory loaded. The four most significant bits are saved using the 4-bit page hold circuit 294 loaded into the program counter. There are also six bits of the command program word fed to a decoder formed by a programmable logic field, and the least significant four bits of the instruction program word become a 9x32 address decoder supplied to a constant file formed by a read-only memory.

The 8 to 4 encoders 302a and 302b are the least significant of the four Bits from the 8-bit command word and from four bits from an encoder for automatic Addressed channel shift. These eight bits are encoded in four bits, addressing the 4-bit microprogram counter 400. The four least significant bits from the instruction read-only memory also address a 4-to-12 fleece encoder for one Status input switch. Two of the four least significant bits address a 2 to 4 decoder a buffer file with direct access in the arithmetic unit.

In Figures 6a and 6b is a more detailed circuit diagram of one programmable logic field (PLA) formed command decoder shown. six Address bits from the instruction memory are used to address the 6x28x12-bit decoder used. The output of this decoder comprises 26 AND functions and 12 OR functions.

Figures 7a and 7b show a more detailed circuit diagram of the status input switch. The 12 inputs of the status input switch are made by decoding the four least significant Bits of a command word read from the command read-only memory. A match indicator between the decoding result and the 1-of-12 singing signals is set by setting a status hold circuit 282 is displayed.

This status holding circuit is set to the "1" state when a of the 12 input functions and a compliance indicator are available.

Figures 8a to 8d show a more detailed circuit diagram of the arithmetic unit and the random access cache file. The 14-bit word from one of one Read-only constant file is stored in parallel in the 14-bit B working series register 274a- 274b read. For intermediate storage of the data from the constant file and of the work series registers is one formed by a random access memory 4x14-bit cache files 276a to 276h provided. The cache file contains four memory locations selected by the 4-to-1 decoder 308. The working register B is accessed via a 2-to-1 encoder 304, and the 14-bit A working shift register 266a-266b is accessed using of the 4-to-1 encoder 270. Access to the one formed by a random access memory The 3-to-1 "encoder 278 is used to cache the file. For adding and subtracting A 1-bit full adder 288 is provided for the A and B working registers. The two Least significant bits of the command word are used to address the cache file used.

FIGS. 9a and 9b show a more detailed circuit diagram of the pulse duration modulator generator (PWM generator).

A 214 PWM counter 250a-250b is provided. The output binary word is loaded in parallel into a 14-bit PWM hold circuit. If the 14-bit binary word from the PWM counter matches the 14-bit tuning word that is in the 14-bit data holding circuit is stored, the PWM hold circuit is triggered and the digital PWM output signal is generated.

Figures 10a and 10b show a more detailed circuit diagram of the analog circuit for converting the digital output signal of the PWM generator into one sent to the varactor diode tuner analog voltage to be applied to the television receiver. There are also circuits for Achievement of the PWM containment deletion for AFC shutdown, for the receipt of an interchannel pulse and UHF up / down tuning provided.

In the circuit diagram of Fig.11a to 11h, the microprocessor structure is the Television tuning arrangement more precisely than shown in the block diagram of FIG. the binary 5-bit channel address is generated with the aid of the address generator 204 in FIG the 20 position selector switch 202 read. The binary channel address corresponds to one of 20 channels, of which 12 are VHF channels and 8 are UHF channels In addition to channel addressing, the selector switch is provided with a device 224 for selecting a channel interruption, a device 226 for selecting the varactor diode area the television tuner and a device 228 for programming the bias for the automatic Verse frequency control. The channel address is directly into the 5-bit address hold circuit 206 in the persistent storage circuit read with direct access. The information in the 5-bit address holding circuit 206 is used to address the addressable 32-bit permanent memory matrix with direct access is used, and it also provides a parallel input to a 5-bit address shift register 208. The 5-bit address on a trunk from the selector switch becomes used to address one of the 20 memory locations in the permanent memory circuit, which are used to store the binary voting word. In the permanent storage circuit contains 12 binary VHF tuning words and 8 binary UHF tuning words.

In series with shift register 208 is a 15-bit data output shift register 210 switched. These two shift registers 208 and 210 are in read mode, if they are not programmed for an ejection process. Hence they are always for reading the address hold circuit 206 and the 15 bits from the persistent storage matrix 212 ready. 14 bits from the permanent storage matrix are used to represent the binary Voting word is used, and the fifteenth bit, namely the most significant bit, becomes used as a jump indicator.

The 20 bits from 5 bits of the address register and 15 bits of the data output register are shifted out serially when the persistent storage array 212 is read. At the If the bits are shifted out serially, they are serially again by means of the loop 222 returned to the stack so that the 5-bit address and the 15-bit voting word stored in the registers again0 The address and that Vote words become a 20-bit input data buffer when shifted out of the registers into the control chip which consists of a 5-bit address buffer 230, a 1-bit jump indication buffer 232 and one? 14-bit input data buffer register 234, as shown in Figure 11b. The address buffer register 230 contains the last bits taken from the persistent storage matrix are shifted and form the five address bits. The one in sixth place Bit is the jump bit, which is located in the jump buffer register 232 immediately afterwards to the address buffer. The voting word consisting of 14 data bits is into the 14-bit input data buffer register 234 through a selector encoder 236 directed. The selector switch encoder 236 has three selected states, viz for loading the input data buffer (LIB), for reading the permanent memory matrix (RNVM) and for reading the input data buffer (RIDB). The 14-bit voting word is read into the data buffer register 234 by the selector encoder 236 the operating mode for reading the permanent memory matrix is selected.

The binary vote word in data buffer register 234 is written in parallel in the 14 = bit PWM hold circuit 248 read when on the 14 bit data hold circuit 238 a PWM load signal (LPwM) is available. The 14-bit tuning word in the PWM hold circuit 248 is used as a comparison word for the 14-bit PWM counter 250. The pulse duration modulator (abbreviated PWN) works with an input clock frequency of 1 NHz from the PWM buffer and oscillator circuit 252 supplied to the 2 PWM counter 250 and continuously is in operation.

The PWM counter 250 counts from the binary number O until it reaches a reached by two states. The first condition is that when that Binary word of counter 250 with the 14-bit tuning word in PWM hold circuit 248 agrees, this holding circuit performing a size comparison has an output signal emits, and triggers a flip-flop, which then remains in this triggered state, until the counter completes its counting cycle. The second state is that if the PWM hold circuit 248 has a content with only the values 1, the PWM counter counts up to a state with only the values 1 " which also corresponds to the overflow point of the counter. The PWM counter therefore counts always up to the value 214, and it then overflows, with the number 214 at an input signal of 1 MHz corresponds to a signal output at 16 milliseconds.

In the PWM generator, a size comparison is therefore made between the status of the PWM counter and the 14-bit tuning word carried out in the 14-bit PWM hold circuit 248 is stored, and if for the first time there is a match between the count and the binary quantity occurs, the PWM hold circuit 48 becomes an output signal obtained which is proportional to the voting word. For tuning the television receiver the pulse width modulated signal from the PWM hold circuit 248 is changed. That The pulse width modulated signal is changed by the fact that the in the PWM hold circuit contained bit value of the binary tuning word is changed, so that a modulated Pulse duration with a working period of 16 milliseconds results in 0 The jump bit in the jump buffer register 232 can be accessed via the jump input via the NAND gate 256 can be changed. In the program algorithm, when changing the channel switch, the Information read and written to memory when the function is finished.

The change of the jump information is obtained by first the state of the jump buffer 232 is read, which contains a most significant bit, that was read from memory that this bit is then loaded into a D register 254 and that this information is then changed when a program entry for There is a change in the state of the channel skip switch.

For giving an indication that the sewer appraisal holder * - ~ changed and is for the display of the current program status of the channel skip switch a jump output 258 is provided. The channel jump switch is in a mechanical Rotary selector switch as in this embodiment, in which the selector switch 202 is on Rotary switch is not applicable. By replacing the rotary selector switch with a electronically addressable circuitry as described in the US patent 3 968 443 could be a jump function to the one to be described here Tuning circuitry can be applied.

After loading the address buffer 230 with the five address bits the address generator 204 receives these five address bits in parallel with the 9xD2 address decoder 260 and to the 5 to 4 encoder 262 for automatic channel shifting (only for VHF) as in Fig. 11c is specified. The encoder automatic channel shifting is used to determine whether the Arrangement in UHF operation or in VHF operation works. If the arrangement is in VHF operation works, the encoder gives one of four for automatic channel shifting possible code groups to enlarge the VHF tuning word. The four code groups correspond to the specific increment bit value for the from the address generator 204 selected VHF channel applies. Since only four incremental speed values and There are 12 VHF tuning words, encoder 262 selects which one is on the arrangement is set, one of the four incremental speed values for the application to the given voting word.

The 5-bit address from the address buffer 230 is also sent in parallel the 9x32 address decoder 260 is applied to it in that of a read only memory 14-bit data word stored in the property file 264 formed is selected. the 5-bit address that determines the VHF or UHF channel is determined by the 9x32 address decoder decoded into a 32-bit address word so that the one formed by a read-only memory 32x14 constant file is addressed. The four least significant bits of the opcode group determine which of the 32 words are addressed.

These thirty-two 14-bit words in the constant file are top and lower limit values for the VHF channels, UHF channel limits, incremental values for the VHF and UHF coordination, time increment values, maximum time values and write time values.

When a tuning word has been read into dsn input data buffer 234 and a voting function is to be performed with it, the fourteen become Data bits from the input data buffer register into the 14-bit A work register 266 by means of a command to read the input data buffer (command RIBD) on the 4-to-1 coding switch 270 Transfer. The 14-bit word is also serialized back across the loop 272 transferred back to its starting point. After loading the A working register with the 14-bit tuning word, the tuning limit value and the incremental value are selected of the 14-bit constant file is output and loaded into the 14-bit B working register 274. These values are now stored in the cache file created by a direct access 276 is loaded by selecting the LBMX command on selector encoder 278. The cache file forms a random access memory with a capacity of 4x14 bitsa The tuning process is now carried out by placing a in the B working register Stored incremental value for the 14-bit tuning word stored in the A working register is added when the arrangement is operating in the up-tuning mode, during the Incremental value is subtracted from the tuning word when the arrangement is in downward tuning mode is working. The enlarged or reduced tuning word is made using the "A" normalization instruction transferred back to the A working register at the selector switch encoder 270 of FIG. 11d.

After the retransmission process, the updated 14-bit voting word will be in the input data buffer 234, in which a selector switch encoder 236 Existing command to load the input data buffer (LIDB command) is executed. The updated voting word is now stored in the input data buffer, and it is also stored again in the A working register. The updated vote is now loaded into the 14-bit PWM hold circuit 248 so that the output signal of the PWM counter 250 can be compared with the updated tuning word.

When executing a voting function, the voting arrangement goes through a sequence in which an addition and time-out routine in the arithmetic unit is reduced by reducing the size of the time control word is executed until a negative number is reached. In each In this case, information is read from the ROM constant file and stored in the RAM cache file saved. This information depends on the particular channel and on whether the channel is a UHF or VHF channel. The arrangement runs through this sequence always a read operation of the input switch so that when there is a change of state this change of state was detected at the input switches during a tuning function and the system function is changed to the last command entered 0 This Input control functions are performed using the 12-to-1 state input switch 280 read into the system which has 12 inputs as shown in Fig.11f.

A slow clock signal with a frequency of 61 kHz will is supplied so that a write function is carried out, which in the case of persistent storage cells in DIFMOS technology, a time on the order of 100 ms for writing of the data value 0 takes up into the memory, so that a clock signal with lower frequency than the normally used control or processing clock is needed. The slow clock signal is also used to achieve buffering in the Switch-on mode after the complete execution of a write command to the Write to memory is used so that the device does not read a new word while it still adjusts itself.

Another input is made via the UHF / VHF control power; these Entry depends on the particular address detected by selector switch 202 has been.

A third input signal is the selection signal for a high AFC value, and a fourth input signal is a low AFC select signal. The job of the high and low AFC values is for a digital frequency control function (AFC function).

The devices for achieving digital frequency control are not shown in the figures and also not indicated in the algorithm. The digital one Frequency control system could be incorporated into the arrangement with the help of several comparison windows and a corresponding addition of control logic to the present algorithm inserted.

A fifth input signal is a UHF up / down control signal, which comes from a comparator 282 which determines whether the tuning voltage is above or below under the corresponding potentiometer setting of the coarse tuning potentiometer 284 for the UHF channel. Another input signal is the counting signal for switching on or off the supply energy. When there is an input signal to switch off the supply energy, the value stored in the input data buffer 234 is used 14-bit tuning word written into the addressable permanent memory.

The seventh input signal is a step input signal that goes into the The arrangement to be described here is not included. If this jump function would be available, it would allow selected channels to be skipped, but it is this is not possible with a mechanical rotary switch, as stated above.

The eighth input signal is the one that can be entered using the rocker switch Upward fine-tuning signal for the control voltage, and the ninth input signal is the downward fine-tuning signal for the control voltage, the control signal for switching the UHF tuning on and off puts the tuning function in a UHF coarse tuning mode. The on / off switch for frequency control (AFC), the internal AFC tuning function is used to activate or to allow an external, manual tuning operation. The last switching signal at the status input switch is the inter-channel pulse, the is input from the selector switch 202 via the channel interrupt line 224. Of the The inter-channel pulse indicates that the selector switch is in switching mode is located between channels, and it is also used for fixing of completed switching process.

The 12 input signals are input to the state input switch. If one of the 12 inputs on the status input switch is activated, it is activated with a specific selection code group is compared, and the status holding flip-flop 282 is set, if the indication of a match in the read command of the given command for the specific switch, which is closed or open depending on the case. The status switch inputs are decoded by the 4 to 12 decoder 284, which is supplied by the four least significant bits of the instruction from instruction read-only memory 286 are addressed will. Status hold flip-flop 282 provides an indication that the arrangement is on Has received an input signal corresponding to one in the command table of the decoder 284 contained signal corresponds.

The second input to status hold flip-flop 282 is the carry input from the 1-bit full adder when the system is operating in a subtraction routine, and when this subtraction routine results in a negative number. The ad the negative number is used to perform benchmark tests that determine whether an upper or lower voting limit or a time limit has been reached, The setting of the status hold flip-flop 282 results in an entry into the instruction read only memory 286 for loading the program counter with a new instruction address page.

The 8-bit program counter 290 shown in FIG. 11c receives Counting clock signal from the 250 kHz clock generator 292, the frequency of which is a quarter of the value of the 1 MHz clock from the PWM-ZShler 250 is. The program counter delivers a of 256 instruction addresses for instruction read-only memory 286e The location of the program counter its counting sequence can be changed by adding a new 8-bit word is loaded into the program counter. The four least significant bits from instruction read-only memory are moved in parallel to the four lowest-value positions of the 8-bit program counter and they are also loaded into a 4-bit page hold circuit 294 in parallel When the status hold flip-flop by a subtraction operation when reading an input signal is set by the status input switch, then with a page load command (LPD-Bßfehl) at NAND gate 296 the four least significant bits of the address from the page hold circuit loaded into the most significant bit positions of the program counter.

The output of the permanent instruction memory: s286 leads to one of one Programmable logic field formed instruction decoder 298, the 26 AND functions and outputs 12 OR functions, as indicated in FIG. 11e. The instruction decoder consists of a 6x28x12-bit memory. These AND and OR functions correspond the instruction set used to program the arrangement.

The 4-bit microprogram counter 300 is used to generate shift control signals for the various shift registers of the tuning circuit. In particular the microprogram counter enables the 14-bit data word to be shifted out of the A working register into the data input buffer register.

It also enables the addition and subtraction of the contents of the A and B working registers, and it allows data to be transferred to persistent storage.

The maximum number of serial shifts through the program counter is 14 bits. When the shifting operation effected by the microprogram counter ends system operation is returned to the 8-bit program counter where it is switched to the next program address. The 8-bit microprogram instruction is selected by microprogram address selection encoder 302. Four bits from encoder 262 for an automatic channel shift and four least significant bits from the Instruction read-only memories are loaded in parallel into the address dialing encoder so that four instruction address bits for the microprogram counter 300 can be provided.

In FIG. 11d, a switch encoder 304 is indicated which has a restore process enables the 14-bit word in the B working register to be returned to this register can be pushed back. In addition, the switch encoder enables shifting of the 14-bit word from RAM cache file 276 into the working register. Of the Switch encoder 270 allows a 14-bit word to be extracted from the RAM cache file and from the data input buffer register 234 and a sum product of the addition the contents of the working registers A and B by means of the 1-bit full adder 288 into the A working register and it also allows the word in the A working register to be saved again in this register.

The RAM cache file 276 is made up of two bits from instruction read only memory addressed via a 2 to 4 encoder 306. The 4-bit word from the encoder will be is used to use the 4-uf-1 dial encoder 308 to use one of four 14-bit spelcher files in RAM cache file 276. The pulse width modulated signal at the output 310 of the PWM hold circuit is entered into the PWM buffer 252. That PWM signal from the PWM ° buffer is input into a driver buffer 312, which is at a reference voltage of + 5V is applied, as indicated in Figo11h, the PWM output signal goes through a three-stage PWM filter to determine the resolution and the Ripple voltage required IC filtering results in that for a pulse duration modulated Signal with the next duration to achieve a usable level in UHF operation are needed. VHF operation does not require such strong filtering for generation a pulse width modulated signal with an acceptable ripple value. For UHF operation, however, requires at least three filter stages. The output signal of the three-stage filter is a DC voltage, which is the pulse duration modulated Signal is proportional, the pulse width modulated signal in turn to the 14-bit tuning word is proportional to that in the 14-bit data input buffer register and in the PWM hold circuit has been loaded. The tuning voltage is generated by means of an inverting voltage amplifier 316 and then filtered through another single stage filter 318. the The resulting analogue tuning DC voltage is fed to the varactor diode tuner of the remote receiver to achieve the tuning to the desired channel.

A second comparator 282 forms a UHF up / down comparator, an input signal from the three-stage PWM filter and an input signal from the UHF coarse tuning potentiometer 284 receives. The potentiometer is at the same voltage of + 5V as the driver buffer 312 laid. The comparator 282 provides an indication of whether the arrangement is in UHF coarse tuning mode or not and whether the arrangement is on a value above or below the desired tuning voltage for the particular channel setting lies; it also supplies a coarse tuning signal for the control unit.

In Fig.11g is the power supply unit for operating the tuning arrangement shown. The voltage of + 35V is used as the upper voltage value of the tuning amplifier used for the varactor diode tuning voltage.

The voltage of + 17V is used as the bias voltage of the MOS circuit of the permanent storage used. The voltage of + 10V is used to bias the CMOS logic of the arrangement The voltage of + 5V is used as the supply voltage for the TTL and I2L circuits the arrangement. The switching voltage from OV to -35V is finally used for programming of the persistent storage is used when the arrangement is in a write mode.

In a voting process using the microcomputer solution in VHF operation becomes a binary tuning word stored in the input data buffer register within the limit values for the minimum and maximum tuning voltages for the selected channel stored in the ROM constant file or scaled down. The ROM constants file contains one for each of the 12 VHF channels Binary word for the maximum Tuning voltage value and for the minimum Tuning voltage value. These limit values form those permitted by the voting arrangement Tuning range. The values are selected individually for each of the VHF channels. In the In the same way, minimum and maximum limit values are also formed for the UHF channels. Due to the large number of UHF channels, the minimum and maximum limits are however formed so that they encompass all 72 UHF channels, with the tuning on the selected UHF channel falls within the range in between.

The circuit diagram shown in FIG. 12 shows an arrangement for calculating the minimum and maximum tuning voltages; furthermore are the equations used for this specified. Equation 3 gives the input voltage as a function of the output tuning voltage. Given the tuning voltage Eg, the input voltage Ei can be calculated. In addition, using equation 4, those corresponding to the input voltage can be calculated Bits are calculated, resulting in that corresponding to the calculated input voltage binary voting word results.

In this context there are those added at the end of the description Table I shows the VHF read-only memory constants for the minimum limits that are result from equations 3 and 4. Each of the VHF channels has its own binary word according to the minimum voltage limit. In the same way there are too Table II at the end of the description shows the VHF read only memory constants for the maximum tuning voltage. As can be seen, the nominal value is the tuning voltage for tuning the television receiver anywhere between them both defined limit values. The binary words contain 14 bits of data, and they will addressed by the five-bit binary address from the selector switch.

The data including the minimum and maximum limits for the VHF channels are in the ROM constant file as appended at the end of the description Table III saved.

As indicated, 32 data values are stored in the ROM constant file. The VHF and UHF incremental values are also stored in the ROM constant file. The maximum time value for VHF and UHF voting is also stored therein. The time incremental value is also saved in this file. Furthermore are also in this file the minimum tuning word and the maximum tuning word for the UHF channels and the writing time are saved.

Table IV at the end of the description gives the decoding logic for an automatic right shift addressing of the microprogram counter (only for VHF).

As can be seen from Table III, the VHF incremental value is on of the seventh bit position, the data "1n. During enlargement or reduction of the VHF word, it is desirable to increase a certain bit weighting value or to reduce, which is uniquely assigned to each of the VHF channels. So this is achieved, the encoder takes care of the automatic channel shifting for a Shift to the right of the incremental value so that it is normalized in such a way that results in a different bit weighting for each of the 12 VH? channels.

The number of right shifts in VHF operation for each of the selected Channels is in Table IV in addition to the code word for the microprogram counter presetting specified. Since the UHF tuning takes place in a process that increases the bit weighting in the incremental value is a normalization of the incremental value by shifting to the right not mandatory.

The command logic from the one formed by a programmable logic field The decoder is given in Tables V and VI at the end of the description. Table V shows the decoded output variables from the instruction read-only memory 12 NOR element outputs. These 12 outputs are the OR functions for the microcomputer program.

Table V gives the 28 output signals of the programmable Logic field formed decoder for the read-only memory instructions. These output signals are the 28 AND functions for microcomputer programming.

In Table VII at the end of the description are the opcode groups for the commands executed with a clock signal, including their addresses specified.

The 4-bit and 6-bit opcode groups for the microprogram control instructions and their addresses are given in Table VIII at the end of the description.

The code groups for reading the input control line are in the am Table IX attached at the end of the description. The input functions have the same four most significant bits (0100); they just differ in the four least significant bits.

Table X, which is added at the end of the description, shows the address code groups for the ROM constants.

It should be noted that the 12 VHF channels have 12 minimum limits and are coded to 12 maximum limit values and from the first 24 ROM addresses (00000 up to 10111). The remaining eight words are in the last eight ROM addresses (11000 to 11111), making a 32 word read-only memory structure to 14 bits is applied.

The voting arrangement and the information contained in Tables I to X. can be better recognized with reference to the instruction set algorithm.

The instruction set algorithm for the voting system with a station permanent memory is indicated in Figures 13A to 13L. The algorithm can be in a sequence of four operating modes can be divided. The first mode of operation includes the mode of operation without vote; it is indicated in Figures 13A to 13C. The second mode of operation is the start of the AFC shutdown loop, the selection of the tuning mode and initialization includes; this mode of operation is indicated in Figures 13D to 13F. The third mode of operation comprises the start of one carried out by means of the rocker switch Tuning process, that is, the channel fine-tuning; this operating mode is in the Figures 13G through 13H. The fourth mode of operation is UHF tuning by means of a potentiometer including the UHF coarse tuning; this operating mode is in indicated in Figures 13I to 13L.

The tuning arrangement is activated by a switch-on input 0 according to FIG. 13A activated, followed by a Page Load Command (LDP) that uses a 4-bit address code group in the page hold circuit 294 for addressing one of the 16 pages of instruction read-only memory 286 is loaded. A write erase (SWRO) operation is performed on the scan line to the integrated memory circuit is reset and the memory cells from a Write operation can be switched to read operation. Then a Channel read interrupt loop executed in which the tuning arrangement sets the channel interrupt switch reads until the channel interrupt display is no longer present.

A channel break indicator 224 from selector switch 202 is displayed on the Status input switch 280 applied. When the input signal with the 12 bits in the binary decoder 284 matches, the status holding circuit 282 is set.

The loop for reading the channel interrupt signal reads continuously the status hold circuit to determine whether or not it has been set not. As long as the status hold circuit is set by a channel interruption indicator is, the tuning arrangement jumps back to the reading mode and continues with it continues until the signal in the status holding circuit due to the termination of a Channel selection on selector switch 202 is no longer available. The purpose of the read the channel break indicator is to use the tuning arrangement on reading the To prevent channel tuning when the selector switch from one channel to another Channel is switched.

bach exiting the read loop for the channel interruption indicator a read operation of the channel code group switch (RCCS) is performed in which the 5-bit address from the selector switch and from the address generator in parallel in the address holding buffer 206 of the integrated permanent storage circuit is loaded. The release signal for the slow cycle ensures buffering, so that an electromechanical bouncing is eliminated, which occurs in the course of the switching process can occur. An additional buffering results from the shift to the right of the content of the B working register 274 (RSB3), in which due to an unconditional Branch instruction (UBRN) to the next address in the instruction read-only memory this B working register fourteen times at the slow clock speed is shifted to the right and returned to this register.

With the next command (SNVM) the permanent memory is scanned, wherein the 15-bit word stored in memory in the course of a clock pulse is loaded into the data output buffer register 210 in parallel. At the same time, the 5-bit address from the address holding circuit 206 in parallel into the 5-bit address register 208 loaded. From registers 208 and 210, the read command (RNVM) is sent to Read persistent storage buffera two consecutive right shift operations performed with 10 bits each.

When the 20-bit right shift is complete the 14-bit vote word in the 14-bit data input buffer register 234, and the 15th The bit representing the jump indicator is in jump buffer 232; the 5-bit dial address code group is in address buffer 230.

The PWM load command (LPWM) causes the binary to be loaded in parallel 14-bit tuning word from the 14-bit data hold circuit 238 into the 14-bit PWM hold circuit 248. This gives a binary word proportional to the analog voltage, and it becomes a binary comparison word for the continuously counting PWM counter set. When the status of the PWM counter reaches the binary 14-bit word, that matches the content of the 14-3it PWM hold circuit triggers a signal this hold circuit off, so that the output signal to the PWM buffer and oscillator 252 is transmitted.

The digital signal is generated with the aid of the control buffer 312, the three-stage PWM filter 314, tuning voltage amplifier 316 and the final PWM filter 318 converted into an analog voltage. The analog output signal forms the channel tuning voltage, which is fed to the varactor diode tuner of the television receiver.

If the supply energy to the tuning arrangement is switched off, becomes the 14-bit vote word in data input buffer register 234 into persistent storage 212 written. After reading the on / off switch, the side hold switch is activated 294 is loaded a 4-bit page address indicating the instruction page to which the voting device jumps when it detects the switch-off state of the supply energy. In the algorithm this is the command page 7. The display signal for the switch-on or switch-off status the supply energy is read into the status input switch 280, and if so if it is present in the status holding circuit of the voting arrangement, an Branch to the switch-off write routine # in the algorithm at address 70. The Branch instruction causes the Data value 'ow' in the first four bits are loaded which result in a command of page 7 with the address 0.

To load the 14-bit tuning word, the one from a Bit and the five-bit dialing address in the permanent storage consists of two consecutive shift processes with 10 bits each necessary. With two consecutive right shift operations become the 14-bit voting word and the 1-bit jump indicator in the 15-bit data input register 216 and the 5-bit selection address are loaded into the 5-bit shift register 218. An order to write the data value nO "(WRO) sets the voltages in the permanent memory for the subsequent write operation. The permanent memory retains the write mode at, until the reconciliation order receives a command to change it by means of a delete command (CWRO) is given. The system is activated by a Read Only Read (RROM) command for the The time programmed during which it should remain in the right shift mode. 14th Data bits constituting the right shift time are obtained from the ROM constant file 264 is read and loaded into 14-bit B working register 274 in parallel. At the next Operation becomes the 14-bit word forming the write time serially from the B working register into the RAM cache file into the third file storage location by means of a LBM3 command loaded. This command then causes the data to be restored in the working register. The binary write time word consisting of 14 bits is now from the RAM cache file to the 14-bit A working register using an RM3A instruction 226 read. The binary word consisting of 14 bits for the right shift time is now stored in the A and B working registers.

The command read-only memory 264 is activated again by means of a read-only memory command (RROM) read, whereby the 14-bit word forming the UHF / time increment value is parallel is loaded into the B work register 274 from the ROM file. At the next operation the incremental value stored in the B working register is different from that in the A working register stored magnitude word subtracted. The incremental value is used in a loop routine subtracted in the B working register from the reduced size word in the A working register, until a test condition is reached in which the word in the B working register is larger than the word is in the A register. This state is confirmed by reading the status hold circuit 282 is determined, and if the condition is present, the signal value B1 is determined. If the signal value "1" is determined in the status hold circuit, jumps the arrangement out of the loop and it performs a write-erase (CWRO) operation which takes it out of the write mode after the time-out operation has elapsed.

The tuning arrangement now runs a loop routine for reading the Channel interruption indicator by; when displaying a signal value "O" or "1" in the status holding circuit, the voting arrangement goes back into the loop for Read the channel interruption indicator back. This gives a tight loop, which prevents the tuning arrangement in the course of a shutdown routine to a other part of the algorithm jumps. When the voting arrangement is turned on again the algorithm starts at the switch-on input point with a page load command is started at address 00.

The writing routine was entered by displaying a Shutdown signal, which is represented by the signal value n1 "in the status holding circuit will.

If the supply energy remains switched on, the tuning arrangement operates continue reading the channel skip input in status input switch 280.

A page load instruction (LDP) loads a new page address into the page hold circuit 294. If a channel jump indication is detected, the status hold circuit the signal value? "is entered, where it triggers the page hold circuit and for input of the new address in the 8-bit program counter 290, which is a branch operation to the new page address. The branch operation does a Release of the slow cycle with a second reading of the channel jump indicator and another page load.

If the channel jump indicator is no longer available, the voting arrangement loads a new page in the program counter, and it makes an unconditional jump (UBRN) to the point of the algorithm at address 12. This branch operation checks the channel jump indicator to ensure that no random entry was made. If the channel skip indicator is still present, the tuning arrangement reads the channel skip switch off again, and a loop operation is carried out, until the channel jump signal is no longer available. If the channel jump signal is not is more available, the program jumps to point 03 at address 87, at which the channel jump write routine is located. The now executed Write operation corresponds to the power-up write routine at point # at address 70. Of the Persistent storage is scanned using an SNVM command, followed by two commands for a right shift of 10 bits each time when loading the permanent memory (LNVM). A write command (WRO) sets the voltages for a write operation in the persistent storage matrix. A 14-bit binary word constituting the write time is placed in the B working register 274 is read, and it is then put into di6 RAM cache file at the memory location 3 read.

It is then read into the 14-bit A working register 266. The ROM constant file 264 is read again for the UHF / time increment value, which is loaded into the 14-bit B working register. When reducing by subtraction a loop operation is performed until the content of the A working register becomes smaller than the incremental value stored in the B working register. At this point it jumps the arrangement for command 0 on side O at the switch-on input point of the algorithm return.

If no channel jump input was detected with the command O F is, the program at instruction 12 performs a read of the channel interrupt signal and a page load operation is performed with page 0. If a channel break determined by the presence of the signal value 1 in the status holding circuit the algorithm branches to point #, which is the switch-on entry point at the beginning of the algorithm at address 00. If no channel interruption has been determined, the arrangement reads the AFC on / off switch on the status input switch 280 and branches to Dot # at address 04 what the switch related to reading the channel code group when the AFC on / off indicator is detected has been. If there is no AFC on / off indicator, the arrangement branches to the point at address 18 which marks the start of the AFC loop for selecting the tuning mode and represents the initialization.

When the AFC switch is in the off position, the TV can be tuned by hand. Since the arrangement is only programmed for 8 UHF channels and only one storage capacity for these 8 channels, while 72 UHF channels may exist, the minimum and maximum adjustment limits must be set in this way that they can be used with any of the possible 72 UHF channels. In order to this is achieved, a UHF channel boundary is created from the read-only memory at instruction address 5B read and loaded into the B working register 274. In UHF mode you can fixed channel limits can be set around each of the 72 possible channels, since the varactor diode tuning curve has a linear conversion characteristic. This allows fixed limits around everyone desired channel can be set.

The vote word from data input buffer 234 is put into the A working register 266 read. The UHF tuning limit in the B working register becomes the tuning word is added in the A working register and the result is stored in the RA cache file 276 stored in memory location 1. The original data word is off again the data input buffer 234 and stored in the A working register. The UHF channel limit The B working register now becomes the reconciliation word in the A working register subtracted and loaded into RAM cache file 276 in location 0. This episode of options results in a lower voting word limit in the RAM cache file and an upper tuning word limit value is stored for the specific UHF channel, who has been selected.

The UHF / time incremental value is taken from the command address 62 Read Read Only Memory and Loaded into Working B register 274. This 14-bit binary word has a bit with the value "1" in the least significant position, and it is used to to advance the UHF and also the time. This incremental value is stored in the memory location 2 of the RAM cache file 276 is stored.

In the RAM buffer file are now at the storage locations 0, 1 and 2 contain the information necessary to carry out the UHF voting, if this is desired. The arrangement now reads whether the channel selector is on a UHF channel or a VHF channel has been set by the input signal of the status input switch 280 is read. The UHF / VHF input signal is through routed the encoder of the 5-bit address at address decoder 260. The side hold circuit 294 is loaded with page E, and after the reading process the arrangement starts up continues to address EB at which the UHF on / off input is read when a UHF signal has been determined by the signal value rlr in the status hold circuit. if the UHF tuning mode has been determined, the arrangement branches to a Page load operation to the point at address 94 at which the voting loop started using the UEIF potentiometer in UHF coarse tuning mode lies. If the UHF switch is in the off position, then the arrangement works at address EE, and it branches to instruction 22.

This loop is in both VHF and UHF tuning applicable. If VHF operation was detected at command 64, then would branch the arrangement to page 1 of command B, in which the VHF continuation; chaltwert read from the .ROM constant file and read into the B working register 274 would.

In VHF mode, each channel has one of four possible incremental values. The incremental value that has been read into the B working register is through normalizes a NOR-B instruction in which a shift right operation increases the VHF increment value shifts in a serial way until the evaluated bit value for the VHF channel that has been selected. The VHF incremental value is taken from the B working register loaded into RAM cache file 276 at location 2.

The ROM constant file 264 is read and the VHF maximum tuning word is in work B register 274 and then in the RAM cache file at location 1 loaded. The ROM constants file is reread to make the VHF minimum tuning word which is obtained into the B working register and then into the RAM cache file is read at memory location 0. There are in the RAM cache file Now at storage location 1 the VHF maximum tuning word, at storage location 2 the evaluated one VHF incremental value and at memory location O the VHF minimum tuning word. In contrast Each of the 12 VHF channels has its own minimum tuning value for the UHF channel limit value and its own maximum tuning value.

At address 22, the arrangement now works either in UHF mode or in VHF operation. The incremental value is taken from memory location 2 of the RAM buffer file read into the B working register 274. The match word in data input buffer 234 becomes read into the A working register 266. Before updating the voting word, will carried out a series of reading operations.

First the AFC on / off switch is read. If the AFC on / off switch is on, the program jumps to point at at address 88 by where a normal write routine to write the tuning word from the data input buffer is carried out in the permanent memory. When the AFC on / off switch is in the Off position, the arrangement reads the switch for the supply energy away. When the supply energy is switched off, the arrangement jumps to the point of address 70 to execute a utility shutdown write routine with which the word in the data input buffer is written back to the permanent memory will. If the supply energy is switched on, the arrangement reads the channel jump signal, and if this is present, the arrangement enters a channel hopping loop, which is similar to the loop discussed earlier. If no channel jump is displayed, the arrangement reads the channel interrupt signal; if this channel interrupt signal is available, there is a jump to point 6 at address 30, where a rocker switch voting panel is carried out.

If there is a channel break signal, the arrangement jumps to point Q2 at address 88 to perform a normal write routine with the the tuning word from the data input buffer 234 in the permanent memory 212 is written.

Address 30 forms the start of the rocker switch tuning loop for fine-tuning in UHF operation or in VHF operation. A command to read the tuning up position is used to determine whether the assembly is is in an up-tuning mode or in a down-tuning mode. in the Up-tuning mode branches the arrangement to address 4B, at which the contents of the A and B working registers, the tuning word and the incremental value and the result is stored in data input buffer 234. the end of the RAM cache file, the maximum tuning limit is read and stored in the B working register entered. A subtract operation at address 4E subtracts the updated incremented voting word from the maximum voting threshold. if this subtraction operation results in a positive number, the arrangement branches to Address 3E and loads the updated tuning word into PWM hold circuit 248. This address is also determined by reading the down tuning indicator at the address 33 and upon displaying a down tuning input which is the PWM tuning word checked against the lower tuning limit. The PWM hold circuit 248 is charged, if the subtraction of the lower voting limit from the voting word to a positive one Number at address 3D leads.

A timing routine is executed after the PWM hold circuit is charged. This time control routine results in a fixed time sequence for switching the Voting word. The arrangement described here is for eight pulses designed per second. However, other timing sequences can also be used be, for example 16 pulses per second or 32 pulses per second. The time control changes depending on how quickly the tuning word is updated in fine-tuning mode should be carried out.

The maximum time limit is stored in the ROM constant file in the B working register 274 and also in memory location 3 of the RAM buffer file 276 loaded.

The RAM constant file is read again so that the UHF / time incremental value which is loaded into the B working register. The the maximum time limit Location 3 containing memory is read and its contents are written to the A working register 266 entered. The contents of the B working register are looped through subtracted from the contents of the A working register until the contents of the A working register has been reduced to a negative number. At this point the arrangement jumps to the point at address 22 where the increment value is again from the RAM 2 latch file is read into the B working register and the most recently updated tuning words from the input data buffer 234 to the A working register 0 The A working register now contains the last enlarged or reduced voting word.

The arrangement would also then one over the course of the timing cycle Jump out of the loop if there is a channel interrupt display at address 4A would exist, in which case the system would jump to point 0 at address 88 would allow a normal write routine to write the updated voting word is carried out in the permanent memory.

The program continues with the enlargement or reduction of the voting word away. In addition, in the up-tuning operation at address 50, the updated Tuning word with the upper tuning limit and in downward tuning mode on the Address 3D compared to the lower tuning limit. If the arrangement is the upper Tuning limit exceeded or falling below the lower tuning limit a branch operation is performed on these addresses, thus dependent whether the arrangement is in an up-tuning mode or in a down-tuning mode worked, the up tuning signal at address 53 or the down tuning signal is read at address 57. In any case, the arrangement leads to an unconditional one Branch to point to at address 22 through.

During the sequence of operations, the tuning up indicator or the Down tuning indicator read twice.

The purpose of this double read operation is the function of the input switch. If the arrangement has an up tuning indicator read it should vote down while then if a downward tuning indicator has been read, should perform an upward vote. This results in an automatic reversal of direction during the tuning of the television receiver with frequency control switched off.

If during a tuning process with frequency control switched off the up vote or the down vote to exceeding the upper one or lower tuning limit values, the arrangement results in an automatic reversal of direction with a vote in the other direction.

If the UHF tuning switch in the Switch-on position is read at address EB, the arrangement branches at the Address ED to the point of the beginning of the performed by means of the potentiometer UHF tuning loop at the address at the beginning of the UHF coarse tuning operation. The RAM constant file is read in order to obtain the UHF / time incremental value which is then put into the B working register 274 and into the RAM cache file 276 at storage location O is read. The RAM constants file is used again to achieve of the maximum time limit, which is read into the B working register and into the RAM cache file is loaded at memory location 3. The ROM constants file is used again to achieve of the UHF / time increment value, which is read in the B working register and in the memory location 2 of the RAM cache file is loaded.

In the UHF tuning mode, the arrangement has a different tuning speed programmed. The arrangement starts with a slow tuning speed, and it then accelerates the tuning speed depending on the time so a vote from one end of the voting ribbon to the other within an acceptable one Time is preserved, with the possibility of tuning with initially slower Speed is provided if the desired tuning voltage is close to Starting point is. The UHF / time incremental value is taken from memory location 2 of the RAM latch file read and entered into working A register; aside from that the UIIF time increment value is read from the RAM constant file and stored in the B working register entered. These two UHF / time incremental values in the A working register and in the B working register are added and the result becomes stored in memory location 2 of the RAM buffer file. The maximum time value for UHF tuning, memory location 3 becomes the RAM buffer file read and entered into the B working register. After subtracting the updated UHF / time incremental value from the maximum time value in the B working register is transferred to the address Al performed a test operation. When the maximum time value is greater than the elapsed time Time, the arrangement reads the data input buffer 234 which contains the tuning word to be entered into the A working register for update. The data input buffer acts as a buffer file during the reconciliation process becomes the UHF / time increment value from memory location 0 of the RAM buffer file read and entered into the B working register. The UHF / time incremental value has at the least significant place a bit with the value now and bits with the value IIO " in all other places. This is used to put the voting word at the least significant Digit to increase the value "1".

The UHF up / down controller is read to indicate the direction the UHF vote is determined.

The UHF up / down input signal is taken from a comparator 282 entered. The output signal of the comparator is the actual tuning voltage compared in the voting arrangement. If the arrangement is at address 86 in is in an up-tuning operation, it performs an addition function that the content of the B- Working register to the content of the A working register is added and it loads the result into the data input buffer 234, which is now an enlarged Contains UHF voting word. The UHF maximum tuning value is taken from the ROM constant file read and entered into the B working register, and the updated reconciliation word in the A working register is subtracted from the content of the B working register, thus determining whether the updated tuning word exceeds the UHF tuning limit. has exceeded. At this point it would be desirable to stop the upward tuning and the tuning direction to reverse. If the test condition at address BF indicates that the maximum UHF tuning limit has been reached, the voting arrangement branches off to the point QSan Address 04, which represents an operation without coordination.

When the maximum time limit of UHF voting has not yet been reached has been, the tuning arrangement at address CO loads the updated UHF tuning word into PWM hold circuit 248. The next operation is a time-out operation for the UHF tuning process. The maximum time limit is taken from the ROM constant file and read into the B working register and into memory location 1 of the RAM buffer file entered 0 The UHF / time incremental value is obtained from the ROM constant memory file read, which is then stored in the B working register. The maximum time limit is read from memory location 1 of the RAM buffer file and into the A working register 266 entered. The UHF / time incremental value from the B working register is transferred from Maximum time limit subtracted in the A working register.

At address C5, the subtraction operation of the UHF / time increment value from the maximum time limit value, a test loop routine is carried out, until a decrease to a negative number has occurred. During the loop operation the timeout, the channel interruption selector is read to determine whether a positive input signal is present, whereby the tuning arrangement to point # would branch at address 88, where a normal write routine takes place. If no channel break signal is detected, the tuning arrangement remains in the operation loop to in the course of the subtraction operation a negative one Value is reached, whereupon the arrangement all branches to point 0 at the address E6, which represents the start of upward tuning by means of the potentiometer 0 In a similar routine, the arrangement carries out the UHF tuning in the downward direction at address A7.

Here the arrangement checks the PWM value in relation to the minimum tuning limit value , which is read from the ROM constant file and at address A9 in the B working register has been saved.

A time-out routine is carried out at address AE, which the The time-out routine performed during the UHF up-tuning process is equivalent to. At the end of the time-out, the UHF vote goes down for the arrangement a branch to point # at the address DB through which the beginning represents the down-tuning loop performed by means of the potentiometer.

At address E6, the tuning arrangement reads the UHF up / down tuning switch, thus it is determined whether the arrangement the tuning process in the upward direction or performs in the downward direction. If the order determines that the vote occurs in the downward direction, it branches to the dot at the address 18, which represents the beginning of the loop with the frequency control switched off the voting arrangement continues to carry out the UHF voting in the upward direction, it reads the AFC on / off switch and branches off to the point at Address 8A for performing a normal write routine when the AFC switch is in the on position. When the AFC switch is in the switch-off position is, the arrangement reads the switch for the on and Turn off the utility power, and it branches off to the point the address 70 for a write routine when the power supply is switched off, when the supply energy has been switched off. When the supply energy remains on, the arrangement branches off to the point the address 9A, which is the start of an elapsed time counter.

Similarly, the device reads at address DB for a downward tuning loop carried out by means of the potentiometer determines the position of the UHF up / down switch and it branches to the point at the Address 18 when an up tuning operation is detected. When the arrangement continues to tune in the downward direction, then it travels with continue the sequence at address DE.

When this loop ends, there is a branch back to Address 9A a full cycle word update for UHF tuning in the upward direction or in the downward direction.

ii Continuing a second loop at address 9A becomes the UHF / time incremental value increased by its own size, thus creating a new UHF / time incremental value which is twice as large as the initial value is obtained. This new UHF / time incremental value is added to the previously updated UHF vote word that is in the data input buffer 234 is stored. Before the addition process, a test condition is used to check whether the updated UHF / time incremental value exceeded the UHF maximum time value Has. If the maximum time value has not yet been reached, the arrangement leads continue another update of the voting word in a closed loop, starting at address 9A. The updated voting word is in the course each loop is increased by an increasing UHF / time increment until the Maximum time value has been reached. If the UHF maximum time value in the test operation has been reached at address A1, the arrangement branches to Address CD through. This new loop routine carries out a continued increase in size or shrinking the UHF tuning word first at a slow speed and then on each subsequent loop at an increased rate by changing the size of the UHF / time increment value in the ROM constant file is enlarged.

Once the UHF maximum time limit has been reached, the tuning arrangement changes the UHF tuning speed, starting at address CD. A subsequent routine results in a quick update of the bit weighting of the UHF / time incremental value for an increase in the tuning speed. Besides, the value of the maximum tuning time increased. The UHF / time incremental value is taken from the memory location 0 of the RAM cache file is read and entered into the A working register. An RSA-14 operation is performed at address CD. This causes a right shift operation in the A working register by one bit. The UHF / time incremental value is taken from the memory location 0 of the RAM cache file read and entered into the B working register; it is also shifted to the right by 1 bit. The content of the A working register and the contents of the B working register are added and the result is stored in memory 0 of the RAM buffer file. This addition operation leads to an increase in the UHF / time incremental value by a factor of 2. This operation gives a quick update of the bit weighting by using the magnified UHF / time incremental value.

The maximum time value is taken from memory location 3 of the RAM buffer file read and entered into the A working register. The contents of the A working register and the B working register are 14 bits behind with a store operation shifted to the right. The contents of the two Arbettsregister are added and am Storage location 3 of the RAM buffer file is saved. This adding the The contents of the two working registers lead to a doubling of the UHF maximum time limit. After doubling the UHF / time incremental value and the UHF maximum time limit the voting arrangement branches back to point 0 at address 98 of the program. At this point the voting takes place with doubled size of the UHF / time incremental value and with doubled maximum adjustment time.

The arrangement continues voting by at the address 86 it is checked whether the tuning up direction or the tuning down direction is present, and by the PWM word during an up tuning operation with the UHF maximum tuning limit and compared to the UHF minimum tuning limit during a down tuning operation will. If none of the limits has been exceeded, the voting arrangement loads the PWM hold circuit with the updated tuning word, and it times out through which a branch to the potentiometer up-tuning loop to achieve up tuning or potentiometer down tuning loop to achieve followed by a down vote. In either case, the loop represents a change in Voting direction is fixed, and if this is determined, a branch is made to the point to at address 18. If the voting arrangement does not indicate a change of direction it continues to control the on / off controls for frequency regulation and read the supply energy, branching to point 0 at the Address 98 occurs when none of these controls have been operated.

At this point the tuning assembly continues the loop routine taking into account the elapsed time counter, and it increases or reduces the updated voting word until the content of the counter for the elapsed time has been decreased to a negative number is, whereupon the device then branches to address CD. In this the UHF / time incremental value and the maximum time value for the Reconciliation doubled again, i.e. with respect to that originally in the ROM constant file saved values quadrupled; the order then enforces the vote Branch to point Qi at address 98. The same sequence of operations then occurs one that has been described above, in which the inclusion of the counter for the elapsed time running routine with a new UHF / time increment value and a new maximum time value for voting is performed; these two Values are doubled with respect to the previous value.

This gives a quick update of the bit weighting when voting of the UHF channel.

tom manufacturer of the tuning assembly can be given to anyone before it is sold of the individual selected VHF and UHF channels corresponding binary word into the permanent memory matrix be programmed. The binary tuning word would be the nominal tuning voltage of the corresponding channel. However, the manufacturer can also provide the user leave the implementation of this function. In this case the user would go first cycle through the tuning mode for each selected channel until the tuning voltage has been achieved that meets its requirements. At that point it would Tuning word using one of the write modes specified in the instruction set are stored in permanent memory.

The invention is here in connection with a specific embodiment has been described, but those skilled in the art will recognize that within the scope of the invention further modifications and changes are also possible.

Table I VHF ROM constants (minimum values) Channel EAFC Eo (max) Ei (min) Bits no. (Nominal value) 2 1,549 2,149 1,442 4725 0 1 0 0 1 0 0 1 1 1 0 1 0 1 3 1,814 4,320 1,367 4479 0 1 0 0 0 1 0 1 1 1 1 1 1 1 4 2,318 7,158 1,444 4731 0 1 0 0 1 0 0 1 1 1 1 0 1 1 5 4,589 23,000 1,301 4263 0 1 0 0 0 0 1 0 1 0 0 1 1 1 6 4,528 29,885 -0- -0- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 2,299 7,550 1,361 4459 0 1 0 0 0 1 0 1 1 0 1 0 1 1 8 2,490 9,440 1,249 4092 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 9 2,726 11,790 1.107 3627 0 0 1 1 1 0 0 0 1 0 1 0 1 1 10 3.021 14.710 0.934 3060 0 0 1 0 1 1 1 1 1 1 0 1 0 0 11 3,594 18,370 0.955 3129 0 0 1 1 0 0 0 0 1 1 1 0 0 1 12 4,049 23,000 0.665 2179 0 0 1 0 0 0 1 0 0 0 0 0 1 1 13 4.621 29.920 0.103 337 0 0 0 0 0 1 0 1 0 1 0 0 0 1 Table II VHF ROM Constants (Maximum Values) Channel EAFC Eo (min) Ei (max) Bits No. (nominal value) 2 1,549 0,400 1,754 5747 0 1 0 1 1 0 0 1 1 1 0 0 1 1 3 1,814 0,888 1,979 6484 0 1 1 0 0 1 0 1 0 1 0 1 0 0 4 2,310 2,149 2,339 7664 0 1 1 1 0 1 1 1 1 1 0 0 0 0 5 4,589 4,682 4,572 14.980 1 1 1 0 1 0 1 0 0 0 0 1 0 0 6 4,528 12,260 3,147 10.311 1 0 1 0 0 0 0 1 0 0 0 1 1 1 7 2,299 4,624 1,884 6173 0 1 1 0 0 0 0 0 0 1 1 1 0 1 8 2,490 6,010 1,861 6098 0 1 0 1 1 1 1 1 0 1 0 0 1 0 9 2,726 7,550 1,865 6111 0 1 0 1 1 1 1 1 0 1 1 1 1 1 10 3,021 9,440 1,875 6144 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 11 3,594 11,790 2,130 6979 0 1 1 0 1 1 0 1 0 0 0 0 1 1 12 4,049 14,710 2,145 7028 0 1 1 0 1 1 0 1 1 1 0 1 0 0 13 4,621 18,370 2,166 7097 0 1 1 0 1 1 1 0 1 1 1 0 0 1 Table III ROM constants file binary code group PROM command no.MSB address LSB # 2 VHF MIN 0 00000 0 010 0100 0 111 0101 # 2 VHF MAX 1 00001 0 010 1100 0 111 0011 # 3 VhF MIN 2 00010 0 010 0010 0 111 1111 # 3 VHF MAX 3 00011 0 011 0010 0 101 0100 * 4 VHF MIN 4 00100 0 010 0100 0 111 1011 # 4 VHF MAX 5 00101 0 011 1011 0 111 0000 # 5 VHF MIN 6 00110 0 010 0001 0 010 0111 # 5 VHF MAX 7 00111 0 111 0101 0 000 0100 # 6 VHF MIN 8 01000 0 000 0000 0 000 0000 $ 6 VHF MAX 9 01001 0 101 0000 0 100 0111 # 7 VHF MIN 10 01010 0 010 0010 0 110 1011 # 7 VHF MAX 11 01011 0 011 0000 0 001 1101 # 8 VHF MIN 12 01 100 0 001 1111 0 111 1100 # 8 VEF MAX 13 01 101 0 010 1111 0 101 0010 t 9 VF MIN 14 01 110 0 001 1100 0 010 1011 t 9 VHF MAX 15 01111 0 010 1111 0 101 1111 # 10 VHF MIN 16 10000 0 001 0111 0 111 0100 # 10 VHF MAX 17 10001 0 011 0000 0 000 0000 # 11 VHF MIN 18 10010 0 01 1000 0 011 1001 # 11 VHF MAX 19 10011 0 011 0110 0 100 0011 # 12 12 VHF MIN 20 10 100 0 001 0001 0 000 0011 # 12 VHF MAX 21 10 101 0 011 0110 0 111 0100 * 13 VHF MIN 22 10110 0 000 0010 0 101 0001 # 13 VHF MAX 23 10111 0 011 0111 0 011 1001 VHF incremental value 24 11000 0 000 0000 0 100 0000 Time incremental value 25 11001 0 000 0000 0 000 0001 maximum side (rocker stop.) 26 11010 0 000 0101 0 000 1100 UHF incremental value 27 11011 0 000 0001 0 001 0101 UHF minimum value 28 11 100 0 000 0000 0 010 0000 UHF maximum value 29 11 101 0 111 0100 0 101 0110 Write time 30 11110 0 000 1100 0 001 1011 Maximum time (UHF) 31 11111 0 000 0000 0 010 1000 Tabel IV PLA decoding for automatic reverse shift Addressing of the microprogram counter (only VH1?) VHF channel no. binary word number of right coding word offsets for the default setting of the microprogram counter 2 00000 4 1011 3 00001 3 1100 4 00010 2 1101 5 00011 1 1110 6 00100 0 1111 7 00101 3 1100 8 00110 3 1100 9 00111 3 1100 10 01000 3 1100 11 01001 2 1101 12 01 010 2 1101 13 01 011 2 1101 UHF 01 100 10 100 0 N.A.

Table V Commands for output signals of the ROM deodoriser (NOR element output signals) 1. LPC = UBRN + BRN S / L 2. pPC ENABLE = RNVM + LNVM + RSAX + RSBX + ADD + SUBA + SUBB + RMXA + RMXB + LAMX + LBMX + NORA + NORB + RESA + RESB + RIDB + LIDS + WRO + WRI + 27 BIT (OF P.C.) 3. LD µPC = RNVM + LNVM + RSAX + RSBX + NORA + NORB + RESA + RESB 4. DATA IN SEL IDB = SHIFT CONT. IN CODE = RNVM + LNVM 5. SHIFT CONT. IDB = RIDB + RNVM + LNVM + LIDB 6. SHIFT CONT. RAM = RMXA + RMXB + LAMX + LBMX 7. RAM DATA RESTORE SEL = RMXA + RMXB 8. SHIFT CONT. REG A = RMXA + LAMX + RSAX + ADD + SUBA + SUBB + NORA + RESA 9. REG A SEL RESTORE A - RESA + LAMX + LIDB 10. REG A SEL # - ADD + SUBA + SUBB 11. SHIFT CONT. REG B = RMXB + LBMX + RSBX + ADD + SUBA + SUBB + NORB + RESB 12. REG B SEL RESTORE B = RESB + LBMX T a b e l l e VI commands Output signals of the ROM decoder (NAND gate output signals) O. Unconditional branching (UBRN) A. If S / L = 1 or 0 (i.e. irrelevant) 1. Parallel Loading the program counter at the clock signal with the content of the page hold circuit and the four least significant bits of the UBRN code group; 2. Delete S / L at negated clock signal CLK 1st branch (BRN) A. If S / L = 1 1st parallel loading of the program counter at the clock signal with the content of the page hold circuit and the four least significant bits of the BRN code group; 2. Deletion of S / L when negated Clock signal CLK B. If S / L = 0 1. Do nothing; 2. Load page (LDP) A. Load the 4-bit address code group into the page hold circuit (the four most significant bits the address); 3. Read read-only memory (PROM) A. Parallel loading of the B working register with the content of the read-only memory, which is stored on that of the 4-bit address code group and / or the memory location specified for the channel selection code group (IF-VHF) is stored; T a b e 1 1 e VI (continued) 4. Read input signals (RIN) A Enable the from the 4-bit address code group defines inputs for switching through to the S / L flip-flop; if the input signal has the value "O", then the S / L flip-flop is activated when the Clock signal CLK loaded with the signal value "1"; when the input signal has the value Has "1", the S / L-I? Lipflop when the clock signal CLK occurs with the signal value "0" loaded; 5. Read the channel code switch SW (RCCS) A. Set the input scan signal to the value "1'f, so that the channel selector switch code group in parallel in the NVM holding buffer the integrated memory circuit can be loaded; 6. Loading the pulse width modulator (LPWM) A. Load the contents of the data input buffer register into the PWM data register in parallel during the clock signal CLK; 7. Scanning the permanent storage (SNVM) A. Set the Scan line to the value "O", so that the contents of the permanent memory (NVM) during of the clock signal CLK in parallel into the data buffer register on the integrated memory circuit can be loaded; ** The following functions give the microprogram counter fr 8th; Reading the Persistent Storage Buffer (RNVM) A. Select the in the microprogram counter 4-bit address code group to be loaded; T a b e 1 1 e VI (continued) B. Load the 4-bit address code group (0101) into the microprogram counter for reset for 10 right shift functions; loading takes place during the clock signal CLK; C. With the clock signal CLK, the program counter and the microprogram counter are made ineffective is released; D. for the input buffer registers and the permanent storage buffer registers a right shift command is given until the microprogram counter reaches the status 1111 (10 shifts) reached; E. when the microprogram counter reads 1111 has, then the microprogram counter with the next clock pulse (which it on sets the status 0000) by the clock input signal, and the clock input the program counter is resumed; F. Warning: This command sets that Signal on the data selection line to the integrated memory circuit to the value "1", so that data is output from the integrated memory circuit and the digital-to-analog converter (DAC) can be supplied; 9. Loading the permanent storage buffer (LNVM) A. Likewise as when reading the permanent storage buffer, with the exception that the sequence F is: Direction: This command sets the signal on the data selection line to the integrated Memory circuit to the value "O" so that data from the digital-to-analog converter (DAC) can be entered into the integrated memory circuit; T a b e l 1 e VI (continued) 10. Shift to the right A (R, S.A.X) 11. Shift to the right B (R.S.B. X) A. Selecting a mutable 4-bit address code group for loading in the iticro program counter; B. Loading the microprogram counter during the clock signal CLK; C. Switching off the microprogram counter at the negated clock signal CLK D. Enable the microprogram counter when the clock signal is negated; E. Release the move of data in the A register or in the B register; the data in the A register or in the B register have preceding zeros, during the counting time of the microprogram counter, and they are then shifted to the right according to the following shift code group: Tabel VI (continued) Code group right shift operations 0000 14 0001 14 0010 13 0011 12 0100 11 0101 10 0110 9 0111 8 1000 7 1001 6 1010 5 1011 4 1100 3 1101 2 1110 1 1111 0 F. If the microprogram counter is 1111, then will be Clock input blocked and the program counter clock is enabled; 12-1 addition from A and B (ADD) A. The program counter is blocked when the clock signal -LK is negated B. the microprogram counter is released when the clock signal CLK is negated; C. the Shift control signals to registers A and B are enabled; T a b e 1 1 e VI (continued) D. the restore select input of register B becomes Approved; E. The sum selection input of register A is enabled; F. if the microprogram counter has the status 1111, its clock input is blocked and the Program counter is released.

12-2,3 Subtraction (B-A) (SUBA) Subtraction (A-B) (SUBB) A. Release the negator input to the adder (E) from register A or register B; B. Setting the carry bit in E1 to the value "1"; C. the program counter is at Clock signal CLK blocked; D. the microprogram counter is when the clock signal is negated CLK released; E. The shift control input on register A and register B becomes Approved; F. Data is transferred serially from Register A and Register B to the Summing element pushed; T a b e 1 1 e VI (continued) G. Dates from register B are restored to this register without any changes; H. the total output data are stored in register A; I. when the microprogram counter is 1111, then the program counter is released, and the microprogram counter is blocked; 13-1 Reading from the random access memory RAM into the register (RMXA) Reading the random access memory RAM into register B (RMXB) A. Address bits ( 2 bits) select the storage location in the random access memory RAM; B. a control signal enables the RAM reader back memory element; C. a control signal gives RAM A or RAM oB free; D. the program counter is blocked when the clock signal CLK is negated; E. the Microprogram counter is enabled when the clock signal CLK is negated; F. the sliding transmission links the random access memory RAM and registers A or B are released; T a b e 1 1 e VI (continued) G. Data is transferred from the random access memory RAM to register A or register B is shifted until the microprogram counter reads 1111, whereupon the microprogram counter clock is blocked and the program counter clock is released.

13-3 Load the contents of register A into random access memory RAM (LAMX) 1, 2, 3, 4 Load the contents of register B into the random access memory RAM (LBMX) 19 2, 39 4 A. The program counter is blocked when the clock signal CLK is negated; B. the microprogram counter is enabled when the clock signal CLK is negated; C. the Address bits (2 bits) select the RAM memory location; Do the slide control signals for the selected storage space are released; Eo REG ARM SEL. and data recovery to register A; 14-1 Normalize the contents of register A (NORA) 14-2 Normalize the content of register B (NORB) T a b e l l e VI (continued) A. Select the 4 B channel coding address to load into the microprogram counter (normalized code group); B. Load the 4-bit channel coding address into the microprogram counter during the clock signal CLK; C. Blocking the program counter when the clock signal is negated CLK D. Enabling the microprogram counter when the clock signal CLK is negated; Eo control signals enable the shift transferring members of register A or register B; F. Control signals apply the (serial) input signals of registers A and B. the value "O"; G0 data is shifted in register A or register B until the The microprogram counter has the status 1111, whereupon the microprogram counter clock is blocked and the program counter cycle is enabled.

T a b e l l e VI (continued) 14-3 Unused code group 14-4 Das The signal to enable the slow cycle (SLOC) switches the cycle input to the microprogram counter from the T1 clock line to the slow clock line (period 16 ms); 15-1 Reading the data input buffer (RIDB) A. Enabling the buffer data select signal into the Register A; B. Release of the selector transmission link for the data buffer input data into the data buffer; C. Enabling the shift control signals for the data input buffer and the register A; D. Enabling the program counter when the clock signal CLK is negated, E. Enabling the microprogram counter when the clock signal CLK is negated; F. Data will be shifted from the data buffer into register A until the microprogram counter reaches the Has booth 1111; the microprogram counter is then disabled and the program counter is released; Table VI (continued) 15-2 Loading the Data input buffer (LIDB) A. Enabling the transfer link of register A in the data buffer register; B. Enabling the Rückspeioher member in the register A; C. Control signals enter the shift transfer gate of register A and the data input buffer free; D. Blocking the program counter when the clock signal 8t is negated; E. Share of the microprogram counter when the clock signal CLK is negated; F. Data is extracted from the Register A moved into the data buffer until the microprogram counter reads 1111 Has; the microprogram counter is then disabled and the program counter is enabled.

15-3 Clear the write signal (CWRO) Resets the signal on the scanning line to the integrated memory circuit to the value "1"; Switch the memory cells from the write mode to the read mode; T a b e l l e VI (continued) 15-4 Write (WRO) Sets the signal on the scan line to the value "0" for the negated clock signal CLK, whereby data is in the memory cells can be written; 15-5 Blind command (unused) unused code group for Blind operations.

Table VII Operation code groups Single-ended commands Function Operation addresses Godegruppe UBRN 0000 1/0 1/0 1/0 1/0 BRN 0001 1/0 1/0 1/0 1/0 LDP 0010 1/0 1/0 1 / 0 1/0 RROM 0011 1/0 1/0 1/0 1/0 RIN 0100 1/0 1/0 1/0 1/0 RCCS 0101 XX XX LPWM 0110 XXXX SNVM 0111 XXXX Table VIII Operation code groups Microprogram Control commands Function Operation addresses Code groups RNVM 1000 1/0 1/0 1/0 1/0 LNVM 1001 1/0 1/0 1/0 1/0 4-bit Op.- RSAX 1010 1/0 1/0 1/0 1/0 Code gr. RSBX 1011 1/0 1/0 1/0 1/0 LIDB 110000 - - 0 0 ADD 110001 - - XX SUBA (BA) 110010 - - XX SUBB (AB) 110011 - - XX RMXA 110100 - - 1/0 1/0 RMXB 110101 - - 1/0 1/0 LAMX 110 110 - - 1/0 1/0 6-bit LBMX 110111 - - 1/0 1/0 Op.- Code gr. NORA 111000 - - XX NORB 111001 - - XX UNUSED 111010 - - XX SLOC 111011 - - 1 1 RIDB 111 100 - - 0 0 CLR WRO 111101 - - 1 1 WRO 111110 - - XX DUMMY 111111 - - 1 1 Tab 1 1 e IX Read code groups for the input control lines RIN code group Input function 4 most significant 4 least significant bits not used 0100 0000 Channel interruption 0100 0001 AFC on / off 0100 0010 UHF on / off 0100 0011 Fine tuning upwards 0100 0100 Fine tuning downwards 0100 0101 Channel jump switch 0100 0110 UHF / VHF 0100 0111 Supply energy on / off 0100 1000 UHF up / down 0100 1001 AFC high 0100 1010 AFC low 0100 1011 slow cycle 0100 1100 unused 0100 1101 unused 0100 1110 unused 0100 1111 Tables X address code groups of the ROM constants PROM code group stored Word (14 bits) 4 most significant 4 least significant bits VHF minimum limit value 0011 OOXX VHF maximum limit value 0011 01XX VHF increment value 0011 1000 Time / UHF increment value 0011 1001 maximum fine tuning time 0011 1010 UHF channel limit value 0011 1011 UIIF minimum band limit 0011 1100 UHF -Maximum band limit 0011 1101 Write time 0011 1110 Maximum UHF coarse tuning time 0011 1111 Read more

Claims (51)

Claim arrangement for tuning a radio receiver a selected frequency, characterized by a first memory device for Saving of digital tuning words depending on a binary address for output a selected digital voting word, a second memory device for storing of the selected digital voting word and the binary address being the second The storage device is functionally assigned to the first storage device, a microcomputer to achieve a selected change in the digital voting words, which are stored in the two storage devices and a conversion device for converting the digital tuning word stored in the second storage device into an analog voltage for tuning the radio receiver to the selected one Frequency. 2. Arrangement according to claim 1, characterized in that the microcomputer contains the following components: An indexing device for enlarging and reducing of the digital voting word stored in the second storage device at Updating this digital voting word, a device for delivering multiple Operating instructions and logic functions for the microcomputer, a storage device to save binary data depending on the binary address and the commands for Enlarging and reducing that stored in the second storage device digital voting word and an input device for entering control functions, which is assigned to the device for issuing the operating commands. 3. Arrangement according to claim 1, characterized in that the conversion device contains the following components: A pulse duration modulator generator for output a digital signal proportional to the digital tuning word and a Digital-to-analog converter for converting the digital signal into an analog voltage to tune the radio receiver to the selected frequency0 4. Arrangement according to claim 1, characterized in that the radio receiver is a television set is. 5. Arrangement according to claim 1, characterized in that the first Storage device is persistent random access memory. 6. Arrangement according to claim 1, characterized in that the second Storage device is a shift register. 7. Arrangement according to claim 2, characterized in that the device is an arithmetic unit for enlarging and reducing the digital voting word. 8. Arrangement according to claim 7, characterized in that the arithmetic unit contains the following components: several shift registers, a 1-bit full adder, which is assigned to these shift registers and the digital ones stored in them Tuning words and binary data added and subtracted, and a storage device for storing the digital tuning words and the binary data sent to the shift registers and is effectively assigned to the 1-bit full adder. 9. Arrangement according to claim 2, characterized in that the device for the delivery of several work commands and logical functions, the following units contains: a program counter, an instruction memory that depends on the program counter outputs binary commands and a program logic field that depends on the binary commands outputs several logical functions. 10. The arrangement according to claim 9, characterized by the program counter associated microprogram counter. 11. Arrangement for tuning a radio receiver to a selected one Frequency, characterized by a first memory matrix for storing digital Tuning words corresponding to the selected frequency, a device for generating a binary address for addressing the digital tuning word in the first memory matrix, a storage device for storing the binary address and the addressed digital tuning words, those of the first memory array and the device is assigned to generate the binary address, a device for enlarging and reducing the addressed digital voting word when it is updated, an output device, the binary data selected depending on the binary address outputs from a second memory matrix, this binary data for enlarging and downsizing the addressed digital voting word can be used for issuing several work commands and logical functions for updating the digital voting word, one of the devices for issuing multiple work commands Associated input device for entering control functions and a conversion device to convert the addressed digital tuning word into an analog voltage for Tuning the radio receiver to the selected frequency. 12. The arrangement according to claim 11, characterized in that the digital Tuning words also correspond to multiple VHF and UHF television channels. 13. Arrangement according to claim 11, characterized in that the storage device to store the binary address and the addressed digital tuning word Shift register is. 14. Arrangement according to claim 11, characterized in that the device to enlarge and reduce the addressed digital voting word, the following Components contains: Several shift registers, a 1 ~ bit full adder, which this Shift registers is assigned and the digital tuning words stored therein and binary data added and subtracted, and a storage device for storing the digital tuning words and the binary data sent to the shift registers and is effectively assigned to the 1-bit full adder. 15. The arrangement according to claim 11, characterized in that the device for the delivery of several work commands and logical functions, the following units contains: a program counter, an instruction memory that depends on the program counter outputs binary commands and a program logic field that depends on the binary commands outputs several logical functions. 16. The arrangement according to claim 11, characterized in that the input device To enter control functions, there is a switch for digital status input. 17. The arrangement according to claim 11, characterized in that the conversion device contains the following components: A pulse duration modulator generator for output a digital signal proportional to the digital tuning word and a Digital-to-analog converter for converting the digital signal into an analog voltage to tune the radio receiver to the selected frequency. 18. The arrangement according to claim 15, characterized by one of the program counter functionally assigned microprogram counter. 19. The arrangement according to claim 14, characterized by an encoder for automatic channel shifting for the normalization of a binary VHF incremental value which is formed from one of the binary data values9 the one in the second Memory matrix is stored. 20. Arrangement for tuning a television receiver to a selected one VHF or UHF channel, characterized by a first memory matrix for storing digital tuning words corresponding to the VHF and UHF channels, a device for generating a binary address on a multiple line for outputting the digital Tuning words from the first memory matrix, one of the first memory matrix and the Device for generating a binary address associated shift register for Saving the digital tuning word and the binary address, an arithmetic unit for Enlarging and reducing the size stored in the serial shift register digital voting word when it is updated, a device for delivering several Work commands and logic functions for updating the digital voting word, a second, memory array for storing binary data for use in the Enlarging and reducing the digital voting word, this second memory matrix works depending on the binary address and the work commands and also the arithmetic unit is effectively assigned an input switch for a digital status for entering control functions of the device for issuing several work commands is effectively assigned, a pulse duration modulator, which depends on the a digital tuning word stored in the shift register Voting word outputs proportional signal, and a conversion device for converting of the digital signal into an analog voltage for tuning the television receiver on the selected UHF or VHF channel. 21. Arrangement according to claim 20, characterized by an encoder for automatic channel shifting for the normalization of a binary VHF incremental value, which is formed from one of the binary data values9 that in the second memory matrix is stored 0 22. The arrangement according to claim 20, characterized9 that the Device for issuing several work commands and logical functions as follows Components contains: a program counter, an instruction memory9 which depends outputs binary commands from the program counter and a program logic field that depends outputs several logical functions from the binary commands0 23. Arrangement according to Claim 229 characterized by a function assigned to the program counter Microprogram counterO 24. Arrangement for tuning a radio receiver to one selected frequency9 characterized by a permanent memory for storing digital Tuning words corresponding to the frequencies9 an addressing device for addressing a selected digital vote word in the persistent memory and a translator to convert the addressed digital tuning word into an analog voltage for Tuning the radio receiver to the selected frequency0 25. Arrangement according to Claim 249 characterized by a device for selectively changing the addressed digital voting word 0 26. Arrangement according to claim 24, characterized characterized in that the permanent memory consists of a random access memory in DIFMOS technology (MOS technology with double injection and gate electrodes that are not fixed in terms of potential) consists. 27. The arrangement according to claim 24, characterized in that the conversion device contains the following components: a pulse duration modulator generator for outputting a digital signal proportional to the tuned word being addressed, and a digital-to-analog converter for converting the digital signal into the analog voltage. 28. Arrangement according to claim 24, characterized in that the radio receiver is a television set. 29. The arrangement according to claim 24, characterized in that the digital Voting words represent selected UHF and VHF television channels. 30. Arrangement for tuning a television set to a selected one Channel characterized by a permanent memory matrix for storing one of the selected ones Channel corresponding digital voting word, a device for generating a binary address corresponding to the selected channel for the output of the digital Voting word from the permanent storage matrix and a device for delivering a dem output digital tuning word proportional analog voltage for tuning the On a selected channel. 31. Arrangement according to claim 30, characterized by a device to selectively change the output digital voting word. 32. Arrangement according to claim 30, characterized in that the permanent storage matrix consists of a random access memory in DIFMOS technology. 33. Arrangement according to claim 30, characterized in 9 that the preselected Channel is a UHF or VHF frequency. 34. Arrangement for tuning a television set to a selected one UHF or VHF channel, characterized by permanent storage with direct access to the Saving digital tuning words according to the selected UHF or VHF channel, a switch for generating a binary address on a multiple line accordingly the selected channel for outputting the digital tuning word from the permanent memory, a pulse duration modulator for generating digital signals corresponding to the output digital tuning word are proportional, and a digital-to-analog converter for converting convert the digital signals into an analog voltage for tuning the television the selected UHF or VHF channel. 35. Method of tuning a radio receiver to a selected one Frequency using a microcomputer, characterized in that a binary address for the output of a digital tuning word corresponding to the selected one Frequency generated from a memory matrix containing several digital tuning words that the output digital tuning word and the binary address in a shift register saved that the digital tuning word stored in the shift register by enlarging or reduction by an incremental value read from a data storage matrix is updated and that the digital tuning word stored in the shift register into an analog voltage for tuning the radio receiver to the selected one Frequency is implemented. 36. The method according to claim 35, characterized in that several Work commands and logical functions for performing the update are generated that depending on the binary address and the work instructions binary data for Update of the digital voting word can be generated and that several binging control functions can be read to change the work commands. 37. The method according to claim 35, characterized in that the Conversion of the digital tuning word into an analog voltage in the digital tuning word proportional digital signal with the help of a pulse width modulator generator output and converted into the analog voltage with the help of an operational amplifier will. 38. The method according to claim 35, characterized in that when To increase and decrease the size of the digital voting word, follow these steps are: storing the digital tuning word from the shift register in a first Working register, reading the incremental value from the data storage matrix, saving of the incremental value in a second working register, adding and subtracting of the incremental value in the second working register, to or from the digital tuning word in the first working register with the aid of an adder and load of the updated tuning word into shift register0 39. The method according to claim 389 characterized9 that the updated voting word again in the first Working register is saved. 40. The method according to claim 389, characterized9 that the adding in an up-tuning mode and subtracting in a down-tuning mode are executed. 41. The method according to claim 389, characterized9 that the incremental value is cached in a memory 0 42. The method according to claim 38, characterized in that characterized9 that the following steps were carried out when voting in VHF operation read the maximum and minimum VHF tuning limit values from the data storage matrix 9 Storing the limit value in the second working register and comparing the updated one digital voting word with the voting limit value 0 43. The method according to claim 38, characterized9 that by reducing a maimal time value a time locking operation is being performed. 44. The method according to claim 38p, characterized in that the incremental value to achieve a normalized incremental value for updating the digital one Voting word in the course of a vote in VHF operation a right shift is subjected. 45. The method according to claim 38, wherein a vote in VHF operation is carried out, characterized in that the maximum tuning limit in the second working register is stored that the maximum tuning limit to the digital vote word in the first working register is added that out the data storage matrix a UHF channel limit value is read that the channel limit value it is stored in the second working register that the UHF channel limit value is too is added to the digital voting word in the first working register so that a maximum UHF tuning limit results in the UHF channel limit being different from the digital Tuning word is subtracted in the first working register, so that there is a minimum UHF tuning limit gives the maximum and minimum UHF tuning limits stored in a memory, and that the updated digital tuning word is compared with the limit values. 46. The method according to claim 42, characterized in that the maximum and minimum tuning values are stored in a memory. 47. The method according to claim 42, characterized in that for each VHF channel has its own minimum tuning limit and its own maximum tuning limit is stored in the data storage matrix. 48. Method of tuning a radio receiver to a selected one Frequency using a microcomputer, characterized in that at one Multiple management a binary address is generated that one of the selected frequency corresponding digital tuning word in a memory matrix with the help of the binary address is addressed that the binary address and the addressed digital tuning word are stored in a shift register that the stored digital tuning word by enlarging or reducing by means of one of a binary data storage matrix read incremental value is updated that several work commands and logical Functions for updating the digital voting word are generated that several input control functions for changing the sequence of work commands generated are and that the stored in the shift register digital tuning word in a Analog voltage for tuning the radio receiver to the selected frequency is implemented. 49. The method according to claim 48, characterized in that the radio receiver is tuned to multiple UHF and VHF channels. 50. The method according to claim 48, characterized in that the The following steps are carried out to generate the work commands and the logical functions are: outputting a binary address from a program counter, addressing a Command memory with the help of the binary address for the output of a selected work command from the command memory and addressing a program field using the work command for the output of a selected logical function. 51. The method according to claim 48, characterized in that the To generate several input control functions, carry out the following steps: Decoding of the entered control functions with the aid of one of the work commands supplied binary code group, creation of the decoded input control function to a status hold circuit and loading a new instruction address into a program counter with the help of the status hold circuit and the logic function.