DE2365222A1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR SWITCHING ELEMENT WITH A ZONE RELATIVELY LONG MINORITY CARRIER LIFE - Google Patents

Description

A method of manufacturing a semiconductor switching element having a relatively long minority & xager life zone

The present invention relates to semiconductor switching elements like filmed, and hybrid integrated circuits that are constructed from epitaxial silicon layers.

An integrated circuit (IC) is a combination of interconnected switching or components that

an-y separably arranged on or in a continuous substrate that serves as a load-bearing material, on or in the a Integrated circuit produced or to which an integrated circuit is connected. An integrated one Circuitry is generally made in a chip of semiconductor material, usually silicon, with the resistors, Capacitors, diodes, transistors, etc. (as required) incorporated into the chip and / or applied to it. The semiconductor body is either made of single crystal material or single crystal islands formed in a polycrystalline material, depending on the type of electrical insulation of the circuit components.

Epitaxial silicon layers are routinely used during the

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Manufacture of film and hybrid integrated circuits applied to silicon substrates. Purely the application of However, high quality single crystal silicon on an insulator must meet stringent requirements for the insulator. the The choice of spinel and sapphire as film substrates arises naturally, some of these substances have lattice planes, that come very close to those of silicon. However have Such epitaxial silicon layers, regardless of the substrate, have limited applications because of their minority carrier lifetimes.

Silicon layers are used in the manufacture of integrated circuits Epitaxially grown on sapphire substrates (silicon on sapphire) at high speed. However, such silicon layers are because of their very low minority carrier lifetimes (of typically 10 ns) particularly limited in their applications (cf. Allison, Dumin, Beiman, Mueller and Robinson, Proc. IEEE, 52 1490 (1969)). The application of such silicon layers is mainly to step-up type MOS transistors been restricted. However, even with this application the low service life of minority carriers is detrimental to the electrical properties of the switching or component. Though For example, the operation of the step-up type MOS transistors is not dependent on minority carriers, but the minority carrier life is dependent important in that it determines the leakage current of the reverse-biased drain pn junction will. This leakage current is particularly common in complementary MOS transistor circuits essential where the final quiescent .Energy dissipation is determined by the leakage current of the drain diode will. The leakage current is inversely proportional to the life of the minority carrier in the pn junction space charge zone.

Silicon layers applied epitaxially to substrates such as sapphire cannot be used in the manufacture of bipolar transistors be used. Although the basic widths of such components are normally very narrow, the minority carrier lifetime for amplification is more bipolar

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Transistors extremely important. The injection of both hydrogen chloride (HCl) and chlorine (Cl) has been used in the oxidation to increase the service life of such components up to the range of 40-50 ns (cf. Robinson and Heiman, J. Electrochera. Soc . 118 , 141 (1971) and Ronen and Robinson, J. Electrochem. Soc. 119 , 747 (1972)). The mechanism responsible for this is presumably a getter effect on metallic impurities through the formation of volatile metal chlorides. However, even a time of 50 ns, which corresponds to a diffusion length of a few microns, is too short for the production of bipolar transistors.

Nevertheless, the ability to isolate components formed with epitaxially grown silicon layers makes it possible by the Insulation properties of the substrate and those created by pn junctions, how they are formed in such layers, given lower capacitance, such layers, are evaluated during manufacture Integrated circuits extremely desirable. Such movies, would find general use in integrated circuits when minority carrier lifetimes in the ms range are achieved know.

One method of making a semiconductor switching element having a zone of relatively long minority carrier life is according to the invention characterized in that a silicon layer is formed in addition to a main surface of a substrate, which is heavily doped with an impurity selected from phosphorus and boron, so that the surface impurity

19 3
concentration is more than ΐ χ 1Ω / cm, and that at least in partial areas of the heavily doped silicon layer, a silicon layer is grown epitaxially, which is relatively weak

17 3 with a concentration of less than about 1 χ 10 / cm is doped so as to form a zone with a relatively long minority carrier lifetime.

Desirably, the heavily doped silicon layer has one

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20 3 impurity concentration of more than 1 χ 10 / cm.

The heavily doped semiconductor layer can be in a single crystal body made of silicon or in an epitaxial layer made of silicon, which are on an insulator or a semiconductor substrate was applied. In the latter case, the silicon layer is preferably heavily doped in that the selected contamination in the already formed epitaxial layer is diffused.

It can be assumed that the heavy doping with relatively small atoms pull together the lattice structure of silicon and metals like sodium, copper, silver and gold stronger can be soluble in the heavily doped silicon layer. Thus, when the lightly doped silicon layer is grown epitaxially, the heavily doped layer acts as a getter to shorten the concentration of the metals and possibly further the service life To reduce impurities in the weakly doped layer considerably.

The invention proves to be particularly useful in connection with thin-film components which are epitaxially applied to insulating substrates such as spinel (for example MgO: Al ₃ O ₃ ) or sapphire (Al ₃ O ₃ ). These substrates, especially sapphire, are known for their low diffusion coefficients towards heavy metals. This is in contrast to the diffusion coefficient of heavy metals in single crystal bulk silicon. Thus, these insulators are incapable of diffusion reducing the life-shortening impurities that have been introduced into thin ^ epitaxially grown layers using known epitaxial techniques. Using the present invention, the minority carrier lifetime in an active region of such devices can be increased by at least an order of magnitude.

Thin film devices, and particularly devices with silicon deposited on sapphire, can be made using the present invention Using the invention in situations for which the previously

4 0 9 8 2 9/0 7 51

was not possible. In such devices, the thickness of the heavily doped silicon layer is preferably about 3 microns or less, while the thickness of the lightly doped silicon layer is preferably greater than about 1.0 µ.

The invention is explained below on the basis of exemplary embodiments explained in connection with the accompanying drawing. In the drawing show:

1 shows a cross section through a MOS capacitor of an integrated circuit produced according to the invention;

Fig. 2 is a diagram showing the C-V behavior of a MOS capacitor s can be seen with a structure similar to FIG. 1;

3 is a diagram showing the impurity concentration in the lightly doped silicon layer of a MOS capacitor corresponding to FIG. 1 as a function of the distance between the interface and the silicon dioxide layer reveals;

FIG. 4 is a diagram showing the C-t response of a MOS capacitor according to FIG. 1;

Figure 5 is a graph comparing minority carrier lifetimes relatively lightly doped epitaxial silicon layers when manufactured according to the Invention on the one hand and by other known methods on the other hand reproduces;

Prop. Figure 6 is a graph comparing minority carrier lifetimes relatively lightly doped epitaxial silicon layers when manufactured according to the Invention on the one hand and according to known other methods on the other hand reproduces;

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Fig. 7 is a graph showing impurity concentration distribution shows an epoxy-axial layer grown on a heavily doped silicon substrate;

8 is a diagram showing a comparison of the increased

Reverse voltage breakdowns of η-doped silicon layers in hybrid integrated circuits during manufacture according to the invention on the one hand and other known methods on the other hand for different Represents growth temperatures;

Fig. 9 is a graph showing impurity concentration distribution reveals a pn junction that was formed according to the invention;

10 shows a cross section through one produced according to the invention bipolar power transistor;

11 shows a cross section through a further embodiment a bipolar transistor of an integrated circuit manufactured according to the invention;

12 shows a cross section through a further modification of a bipolar transistor of one produced according to the invention Integrated circuit;

Fig. 13 is a graph showing impurity concentration distribution the active zones of a particular bipolar transistor similar to that of FIG. 10 can be seen;

14 is a graph showing gain as a function of the current of the bipolar transistor reveals its impurity concentration distribution with Figure 13 is shown;

15 shows a cross section through a complementary MOS transistor circuit one after the present

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Computer memory circuit made in accordance with the invention;

16 shows a partial section through a modified embodiment of a complementary MOS transistor circuit a computer memory circuit made in accordance with the present invention; and

17 schematically shows a cross section through an image acquisition target of a high resolution produced according to the invention Television camera.

In detail, Fig. 1 shows a series of MOS capacitors in a thin film integrated circuit. The capacitors are formed on an insulator substrate 10 with a main surface 11. The substrate may be as spinel of the formula MgO Magnesiumäluminat ^χ Α 1ο ° 3 ^be "wherein χ values between about 0.64 and 6.7 can have. A single crystal spinel magnesium aluminate is commercially available for which χ is about 3.3. Preferably, however, the substrate 10 is sapphire (Al ₂ O ₃ ), the main surface being mechanically polished in the crystallographic (10 02) orientation.

After suitable treatment in order to remove damaged areas and to clean the main surface 11, the silicon layer 12 is applied epitaxially to the main surface 11. The silicon layer 12 is preferably applied to the sapphire substrate by pyrolysis of monosilanes (SiH ₄ ) in hydrogen carrier gas at temperatures between approximately 1025 and 1100 ° C. at a rate of approximately 2 to 3 rpm. The layer preferably has a thickness between 2 and 3 u.

It is then phosphorus in the silicon layer 12 by standard constant source, preferably diffused open tube method. Preferably the diffusion source is phosphine (PH-). The layer 12 is so heavily doped with phosphorus, preferably up to

20 21 3

a concentration between 1 χ 10 and 1 χ 10 / cm.

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Thereafter, a relatively lightly doped n-type silicon layer 13 is epitaxially applied to the heavily doped silicon layer 12 by standard methods in order to form an nn junction 15 therewith. Pyrolysis of monosilanes in hydrogen carrier gas at a temperature between 1025.degree. And 1100.degree. C. is again preferred. The source of contamination working in the system is preferably phosphine (PH-) or arsine (AsH ₃ ). The epitaxial process again takes place at a rate of about 2 to 3 11 / min until the silicon layer 13 reaches a thickness of more than 1 micron and preferably between 2 and 3 microns.

Immediately after its epitaxial growth, the silicon layer 13 does not yet have any zones of different nature. It is then selectively masked by standard photolithographic processes and also selectively by means of a suitable etchant such as potassium hydroxide (KOH) to form islands in the silicon layer 13, like that with FIG. 1 is shown. .

A silicon dioxide layer 14 is then placed over the exposed areas of the silicon layers 13 and 13. The oxide layer is preferably at
2500 R vapor-deposited.

the oxide layer is at about 750 C to a thickness of about

There are then windows 16 by photolithographic and Standard etching process opened in the silicon dioxide layer 14, in order to expose areas of the silicon layer 12. There are then simultaneously formed metal contacts 17 and 18 to with the Silicon layer 12 to form an ohmic contact or to form the MOS contact with silicon layer 13. This can be done by vapor deposition made of aluminum or other suitable metal over the structure so that the windows 16 closed and one immediately adjacent cover are formed. Is is then made using "reverse" or "negative" photomasking and etching processes worked to remove the metal saw in all places, except in and in the vicinity of windows 16

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as well as at the desired location for the frÖS contact. This in The metal remaining in the contact windows is then connected to the The silicon of the silicon layer 12 is alloyed by heating in order to form ohmic contacts of low resistance.

As a result, a thin film integrated circuit is obtained with a number of MOS capacitors,

With the diagrams according to Fig. 2-4 data are reproduced, as they are in the investigation of MOS capacitors similar to those just described with regard to their impurity concentration distribution and minority carrier lifespans were determined »

The silicon-on-sapphire layers of the components examined were grown in a horizontal reaction device that was heated by an external RF induction coil. Before the two layers 12 and 13 were epitaxially grown, the graphite susceptor was cleaned and coated with pure silicon at about 1500.degree. The sapphire substrates 10 were mechanically polished to give a major surface 11 with a crystallographic (10 02) "orientation. Damage to the major surface 11 would be removed by heat treating some substrates at about 1475 ° C for 4 hours in air. Some substrates were one The substrates were then cleaned by degreasing by boiling in an H.SO.-HNO ₃ mixture and then subjected to a chelation treatment _{with H 3} O _{2 -H SO.}

The MÖS capacitors used in the investigation were otherwise manufactured as described above in connection with FIG. 1, with the exception of contacts 16 and 17. The contacts were formed directly by selective evaporation through a metal mask covering the structure. The switching element was then annealed in hydrogen at 400 ° G for an hour, _w erflächenspannunqen to whether to eliminate and so the lifetime

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measurement easier to carry out.

The doping profiles were measured by means of the expansion resistance and pulsed capacitor methods (cf. * Mazur and Dickey, J. Electrochem. Soc. 113 , 255 (1966) and van Gelder and Nicollian, J. Electrochem. Soc. 118 , 138 (1971)) “The minority carrier lifetimes were measured using the pulsed MOS capacitor method, in which the component is pulse-biased to deep depletion and then released to its quasi-equilibrium state (cf. Schrodeiy and Guldberg, Solid- state Electronics, 14, 1285 (1971)).

In Fig. 2 is the C-V characteristic of the MOS capacitor has been shown. The C-V measurements were carried out at 77 ° K, so that the curve of the doping as a function of the depth changes easy to apply. This was done after a bulk silicon MÖS capacitor was used to verify that the The curve for the doping as a function of depth obtained for 300 ° K-C-V data is identical to that obtained for 77 ° K data was. The doping profile can be calculated from the C-V curve and then plotted according to Fig. 3 »

A typical C-t response for the n-type silicon layer 13 with a Minority carrier lifetime of 2.5 ii s is shown with Fig. 4 * More meaningful results are summarized in the following table I, in which the structure, the growth temperature, Growth rate, impurity concentration and minority carrier lifetime for MOS capacitors are listed are, which were produced on the one hand according to the invention, on the other hand according to the prior art.

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Table I.

construction Growing up
temp. (C) Growing up
speed
(at / nin) Contaminant
inclination
Concentr.
^(N D>
(cm " ^J ) Minority
carrier-Le-
service life
(^ g) n-Laqe
-uf-
sapphire 1050 0.7 7 χ 10 ¹⁵ 0.020 n-position
-jauf-
sapphire 1025 2.3 1 x 10 ¹⁶ 0.045 n-position
-up-
n (+) -
Location-
incidentally
sapphire 1025 2.3 1 χ 10 ¹⁶ 0.25 n-position
-on-
n (+) -
Location-
on-
sapphire 1025 2.3 4 x 10 ¹⁵ 1.5

From Table I it is immediately apparent that the present invention improves the minority carrier life of silicon-on-sapphire devices increased by at least an order of magnitude. Trials 1 and 2 show typical minority carrier lifetimes according to the state of the art of 20 or 45 ns. In contrast, using the present Invention for experiments nos. 3 and 4, with a silicon layer doped with phosphorus between the silicon layer doped with arsenic and the sapphire substrate is brought in, minority carrier lifetimes of 250 and 1500 ns, respectively, are measured.

In other similar studies, minority

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Lifetimes associated with the invention in that with arsenic doped silicon layer measured up to 3 us (3000 ns) were high.

Similar devices were fabricated to demonstrate the usefulness of the invention in fabricating semiconductor devices in hybrid integrated circuits. The results of these investigations are shown in FIG. 5 ^; * to Fig. 9 reproduced.

There were single crystal n-type silicon substrates by the Floating zone and Czochralski process produced. the Substrates were either (i) strong with up to phosphorus

1 χ 10 / cm (0.0009 ohm-cm specific resistance), (ii) light

14 3
doped with phosphorus to 5 χ 10 / cm (10 ohm-cm specific resistance)

1 8 or (iii) heavily doped with antimony to 7 χ 10 (0.008 ohm-cm Specific resistance). The substrates were mechanical and chemical treated so that a major surface thereof each have a crystallographic orientation deviating by 2 from the (111) crystal plane would have.

Every substrate and especially its major surface has been through Degrease in acetone and trichlorethylene, then boil in sulfur-nitric acid (H-SO.: 3.HN0_: 3: 1) cleaned. Some the substrates were then made using ammonium ethylenediamine tetraacetate, a complex active ingredient for removal of metal ions from the substrate surfaces, a chelation treatment subject. After degreasing, boiling, and chelating (if used), each substrate was thoroughly immersed in Super-Q

Water, i.e. continuously circulated deionized water, rinsed. Wake up an in situ hydrogen chloride etch then either n- and / or p-doped silicon layers epitaxially on the main surface of the silicon substrates at different temperatures, d. H. 1100, 1150 and 1250 C. The epitaxial application or growth took place in one horizontal reaction vessel with external EF induction heating elements. The graphite susceptor was used before each experiment

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cleaned and coated with silicon. That. Silicon was applied from silicon tetrachloride (SiCl) in a hydrogen carrier gas. The hydrogen was palladium (pd) purified and all materials were ultra-pure. The impurity was introduced into the system as either arsine (AsH ₃ ) or diborane (B ₂ Hg) gas to achieve an impurity concentration in the lightly doped layer of about 1 to

15 3
2 χ 10 / cm to produce. The epitaxial growth was continued at a rate of about 1 rpm until the sheet reached a thickness of about 30 µ.

The epitaxial layers were limited to their minority carrier lifetime and the pn junctions formed in the epitaxial layers and by them were determined with regard to their current-voltage behavior measured. These pn junctions were of three types, namely (i) flat in the epitaxial layers diffused transitions (boron diffusion into h-doped epitaxial Layers); (ii) substrate epitaxial junctions (used only for boron-doped epitaxial layers on η-doped substrates); (iii) epitaxial-epitaxial junctions formed by growing a layer of opposite conductivity type on a first epitaxially grown layer. With regard to the transition measurements, particular attention was paid to the reverse breakdown voltage the transitions directed.

The minority carrier lifetime measurements for the n-doped epitaxial layers on η-doped substrates are shown with FIG. Each point shown corresponds to a mean value of ten (10) measurements on different components. The impact of the different cleaning treatment is from comparing the one at 1150 C for the three different ones Superstructures measured lifetimes can be seen. The structures in which the substrate is a Chelated treatment had significantly longer lifetimes. It can be assumed that this on the highly pronounced metal complex properties of the chelating agent is due.

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The increase in minority carrier lifetime using the In the present invention, as is clear from Fig. 5, the life was independent of the culture temperature considerably larger for η-doped epitaxial silicon layers on silicon substrates heavily doped with phosphorus. In connection with the present invention, at a growth temperature of 1100 ° C., minority carrier lifetimes of up to

us noted.

It can also be seen from Fig. 5 that the minority carrier lifetime increases with decreasing wake-up temperature. It is believed that this is due to a reduction in the amount due to heavy metals introduced into the epitaxial system at the lower temperature.

6 shows the minority carrier lifetime measurements for p-doped epitaxial silicon layers on η-doped silicon substrates. Each point shown corresponds in turn to an average of ten (10) measurements on different components. After it was found with respect to the η-doped epitaxial silicon layer that the chelation treatment is a had a significant impact on longevity, all substrates were chelated prior to p-epitaxial growth subject. The results were practically identical to the observations on η-epitaxial growth. There were Significantly higher minority carrier lifetimes recorded when heavily doped with phosphorus silicon as the basis for the epitaxially grown layer was used, with best results at lower growth temperatures were achieved.

In contrast to those implemented with n-epitaxial silicon layers Investigations, however, improved a subsequent gettering of the boron-doped epitaxial silicon layers in a two-zone P “0_ oven with a temperature of 250 C located getter source and at a temperature of 95O C silicon substrates (in an argon atmosphere

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for .45 min) the lifespan is considerable. For example increased such a getter process increases the lifetime of a Growing temperature of 1150 C by a factor of over 100, as is inclined with Fig. 6. Similar effects were measured at the other application temperatures, but for these temperatures, only the minority carrier lifetimes after gettering are shown in FIG. 6 '. In contrast, had this getter treatment has practically no effect on the lifetimes in the n-doped epitaxial silicon layers. It is to assume that this difference is due to a difference in terms of heavy metal impurities that enter the System introduced.

Fig. 7 shows a typical impurity concentration profile of the investigated η-doped silicon layers on silicon substrates heavily doped with phosphorus. The layer thickness was

14 about 3On- and the doping varied between 5x10 to 2 χ 10 / cm, so that for all but the lowest impurity concentrations a bulk rather than the punch-through breakdown voltage was ensured.

The diodes were either made by a flat board diffusion into the silicon layer or by growing a p-doped epitaxial silicon layer on the η-doped epitaxial Silicon layer formed. It was then made by selective etching Mesa diodes with a diameter of 1 mm are generated and then passivated by applying an oxide layer, such as which is illustrated by the illustration drawn in FIG is. The results of the stress rupture measurements are shown in Figure 8 and Tables II and below III reproduced. The ratio of the measured breakthrough values to the theoretical bulk breakthrough values (corresponding to the layer doping) has been plotted as a function of the application temperature. The open points refer to diffused diodes, while the full dots refer to epitaxial-epitaxial H diodes.

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The numbers next to the dots are the theoretical breakdown voltages, the values marked with an asterisk indicate that the breakthrough is through reaching through the space charge zone to the η · (· +) - doped substrate is determined.

The treatment and growth conditions as well as the doping concentrations of the silicon layers are shown in Table II. The reverse voltage values are for two current values, namely less than 20 η Α and 5 mA specified. The 5 mA value was used as the breakdown voltage measurement. The theoretical breakdown voltages are also shown. Same dates for the epitaxial-epitaxial diodes are shown in Table III.

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Table II Characteristic values of diffused diodes on η-doped epitaxial silicon layers

CO OO l \> CO

Substrate
Doping Growing up
temperature Epitaxial location
Doping Reverse voltage at one
Current from
<20uA 5 mA V ° (V)
BD Heavy endowment
with phosphorus
Specific resistance
O, 0009A-cm 1150
1100
1150
1250
1150 1 χ 1o] j?
1 χ 10 ¹ I.
T χ 10 =
4 X 1θ'ς
1 χ 1O ¹⁵ 250 320
265 300
220 280
260 335
255. 310 320
320
320
700
320 Strong with antimony
endowed
Spec.V.iderst.
0.008Λ-αη 1150
1100
1150
1250
1150 6 x 10 ¹ ^
4 χ loJJ
% ^{Χ 10} 4
χ 10 *
5 χ 10 ^lft 250 400
265 440
250 370
235 300
240 470 490
480 -x)
490
700
580 Easy with Phos
phosphorus doped
Special resistance,
ΙΟΛ-cm 1250 4 χ 10 ¹⁴ 200 275 700.

x) indicates the theoretical punch through breakdown voltage.

Table III

Characteristic values of epitaxial-epitaxial diodes on η-doped epitaxial

Silicon layers

CD OO rs> CD

cn

Substrate
Doping Growing up
temperature Epitaxial location
Doping Reverse voltage at
breakthrough V ° (V)
BD Heavy endowment
with phosphorus
Specific resistance
0.0009 ohm-cm 1150
1250 V / 5 x 10 ^
2 χ 10 ¹⁴ 235 at <1OuA
245 at <10 ^ uA 240
500 x) Strong with antimony
endowed
Specific resistance
0.008 ohm-cm 1150
1250 4 χ 1o] ^
2 x 10 ¹ ^ 350 at 200 JiA
290 at 20 ^ iA 700
500 x) Easy with Phos
phosphorus doped
Specific resistance
50 ohm-cm 1150 1 χ 10 ¹⁵ 24b at 2OuA 325

x) indicates the theoretical punch-through breakdown voltage,

NJ U) CJ)

The general trend of these measurements is consistent with the lifetime data, ie lower growth temperatures resulted in devices with breakdown voltages closer to the theoretical values. Likewise, diodes produced according to the present invention on silicon substrates heavily doped with phosphorus had higher breakdown values than the other two substrates. These diodes also had better IV characteristics, while the others often had a very low breakdown value. The very low ^V _{BD of} the lightly doped silicon layers (2 to 4 χ 1O ¹⁴ 'cm ~ ³ , with the correspondingly high V o) may be partly due to surface

BD effects can be attributed to it.

In contrast to the service life data, the cleaning treatment had little effect on the breakthrough parameters. The chelation treatment and the H ₂ O ₂ cleaning of the silicon substrates did not lead to any results that differed significantly from those of the substrates not cleaned in this way.

It was also observed that the epitaxial-epitaxial diodes behaved largely like the diffused ones. This indicates that such transitions are not inherently bad, but that the transition characteristics are stronger with lower doping depend on the quality of the silicon layer.

With Fig. 9 is a typical impurity concentration profile a p-epitaxial silicon layer on a strong with Phosphorus doped substrate shown. Since a natural pn junction is formed when a p-doped layer is on a η-doped substrate is grown, only the substrate-epitaxial transitions were evaluated for these layers. The results for a growth temperature of 1100 C, with chelation treatment, are shown in Table IV below.

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Table IV Characteristic values of substrate epitaxial diodes on p-doped epitaxial

CD CO (s> CD

Silicon layers for 1 Substrate
Doping Getters 100 C- growing temperature Reverse voltage at one
Current from
<20 left A 5 inA 255 V ° (V)
BD Heavy endowment
with phosphorus no Silicon layer e-dioation
(per cm) 210 280 320 Specific resistance
0.0009 ohm-cm ^P 2 ° 5 250 60 320
I. Strong with antimony
endowed no 50 60 C.
320, Specific resistance
0.008 ohm-cm ^P 2 ° 5 45 265 320 Easy with Phos
phosphorus doped no 250 315 320 Specific resistance
10 ohm-cm ^P 2 ° 5 280 320 1 χ V ⁵ 1 χ 10 ¹⁵ 1 χ 10 ¹⁵ 1 X 10 ¹⁵ 1 χ 10 ¹⁵ 1 χ 10 ¹⁵

Ki CO CD

cn ί-ο

As shown by these measurements, those had on with phosphorus doped SiIi2ium substrates manufactured diodes higher Breakdown voltages than those doped with antimony Silicon substrates, the same as; previously on n-doped Measured silicon layers. As also shown in Table IV, phosphorus gettering had little effect on breakdown voltage.

Similarly, n-epitaxial silicon layers resulted in higher growth temperatures to transitions with less favorable blocking properties.

Similar investigations were carried out on silicon substrates doped with boron, which

20 3
Concentration of about 1 χ 10 / cm. An n- or p-silicon layer was epitaxially applied to each body up to a thickness of 25 ία by means of a silicon tetrachloro

ο
hydrogen system at around 1150 C to form a pn or nn junction with the body. The n-layers

15 were treated with arsenic up to a concentration of about 1 χ 10 / cm doped, while the p-layers with a concentration of about

15 3
3 χ 10 / cm were doped. The MOS capacitors were then formed as described above and the minority carrier lifetimes measured, also as described above. The n-doped epitaxial layer had a minority carrier lifetime of about 100 µs, while the p-doped epitaxial layer "had a lifetime of 0.5 11 s because of the contamination by the diborane doping source. It can be shown that the lifetime of the latter is improved by using the getter technique described above.

To further illustrate the usefulness of the present In the following, reference is made to FIGS. 10-17. Figs. To 14 illustrate the usefulness of the invention for the production of bipolar transistors in hybrid and thin-film integrated circuits. Figures 15 and 16 show the application of the invention in the manufacture of complementary MOS transistors for computer memory circuits. And Fig. 17 shows the

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Utility of the invention in the manufacture of acquisition targets high resolution for television camera tubes.

According to FIG. 10, a bipolar npn power transistor is used made with mesa structure. A single crystal silicon body 20 is provided which has a phosphorus impurity concentration of about 1 10 '° / cm. The single crystal silicon body 20 is mechanically and chemically polished so as to provide the main surface 21 with a crystallographic orientation obtained, which deviates by 2 ° from the (111) crystal plane.

A relatively weakly n-doped silicon layer 22 is epitaxially grown on the main surface 21 in order to form a locally non-delimited layer with a depth of approximately 17 η and an nn junction 23 with the body 20. The silicon layer 22 is preferably applied from a silicon tetrachloride in a hydrogen carrier gas by standard methods.

14 3 The silicon layer 22 is to about 8 χ 10 / cm with a

η-impurity doped by adding arsine (AsE) gas to the Epitaxial system is initiated.

Thereafter, a weakly p-doped silicon layer 24 is applied epitaxially to the silicon layer 22 in order to form a locally non-delimited layer with a depth of approximately 8 η . The same application method is preferably used as when growing the epitaxially grown layer 22. The silicon layer

16 3
, is doped to 1 χ 10 / cm with p-impurity by introducing diborane (BH) gas into the epitaxial system.

The silicon layers 22 and 24 are then selectively etched designed like an island, as shown in FIG. 10. The surface of the epitaxially applied layers is selectively through a standard photolithographic process in which Areas of the epitaxial layers that are to be removed are exposed. The exposed areas are then through windows treated in the masking layer with a suitable etchant such as potassium hydroxide (KOH) in order to make parts of the silicon layers 22 and 24

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remove and leave the islands indicated by FIG. 10 behind. The masking layer is then removed.

The oxide layer 25 is then formed over the exposed areas of the structure to a depth of approximately 2500 Å. The layer 25 is preferably made by vaporising silicon dioxide over the exposed area in a nitrogen atmosphere evaporated from about 700 C.

Windows 26 are then opened in the oxide layer 25 to form the emitter regions 27 of the transistor by standard photolithographic and diffusion techniques. Preferably, a constant diffusion source of phosphine gas is diffused using an open pipe system. The diffusion is preferably carried out with a surface contamination concentration between
1.5

20 21 3

between 1 χ 10 and 1 χ 10 / cm and a depth of about

Windows 28 and 29 are then opened in the oxide layer 25 around patches of the silicon layer 24 or the main surface to uncover and to ensure an ohmic contact with the Easis or collector zones of the transistor. Ground these windows preferably by standard photolithographic and etching processes opened.

Metal contacts 30, 31 and 32 are formed simultaneously to make ohmic contacts with the emitter, base and collector regions of the transistors. This is done by evaporating aluminum or other suitable metal over the structure to close the windows 26, 28 and 29 and form a continuous layer of metal over the oxide layer 25. A "negative ⁿ mask with a standard photolithographic process and a suitable etchant such as 10% sodium hydroxide solution are used to remove the metal layer in all locations except in the closed windows 26, 28 and 29 or in their immediate vicinity. The Metal in the windows is then alloyed with the silicon by heating the body 20,

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so that ohmic contacts with low 'resistance result.

This way a number of npn transistors become in one Hybrid integrated circuit formed.

As shown in FIG. 11, a series of npn transistors are used in the same manner low power in a thin film integrated circuit educated. A sapphire substrate 33 is made in a (1102) crystallographic orientation with a major surface Mistake. The silicon layer 35 is then epitaxially applied to the main surface 34 with a depth of approximately 3 μ by pyrolysis of a monosilane hydrogen carrier gas system is applied at a rate of about 2 to 3 ii / min, with a Self-doping is reduced. The silicon layer 35 is then with phosphorus down to an impurity concentration of

21 3

about 1 χ 10 / cm n-doped by standard diffusion processes. A constant diffusion source made of phosphine (PH ₃ ) is preferably used in an open-pipe system in order to diffuse phosphorus into the silicon layer 35.

Thereafter, the transistors as described in the strongly η-doped silicon layer 35 described above in connection with Figure 1O ^ -. / As for 'the Dicke.der layers - formed. The η-doped silicon layer 22 'has a thickness of about 1.5 11, the η-doped silicon layer 24 ¹ has a thickness of about 0.8 Ai and the emitter zone 27 "has a thickness of 0.4, u. For the sake of simplicity, the reference numbers have each been provided with an apostrophe character C) to denote the corresponding elements as described above.

Fig. 12 shows a series of npn transistors in a thin film integrated circuit similar to that shown with FIG. The structure is identical, with the exception that the one with 27 " designated emitter epitaxially on one designated here with 24 ″ Silicon layer is grown instead of being diffused into it. Preferably, the emitter 27 ″ by selective Lpitaxy grown through cas window 26 "in oxide layer 25"

4098297 075 1

(see Rai-Choudhury and Schroder, J. Electrochem Soc .: Solid State Science, 118 , 107 (1971)). Alternatively, the emitter 27 "can indeir by epitaxial growth on a locally non-limited layer on the layer 24" and by subsequent selective stranding of islands as shown above. layers 22 "and 24" are selectively etched.

13 and 14 are the impurity concentration distribution and the gain of the power transistor of FIG. 10 is shown. In Fig. 13, curves A, B and C show the impurity concentrations of the collector, base and emitter zones of the transistor. In Fig. 14, curve A shows the common emitter current gain of the transistor as a function of the collector current. It shows that the long lifetimes, as they are conveyed by the invention, a large-area transistor a high current gain to lend. From Fig. 14, the minority carrier lifetime of the epitaxially grown layer 24 / with a value of calculate about 1OO .us.

It can thus be seen from FIGS. 11 to 14 that the present Invention makes the use of bipolar transistors possible in applications where a minority carrier lifetime or the equivalent, diffusion length, a parameter of the utmost importance. The invention thus not only opens up the possibility of using bulk silicon transistors, but also of thin-film and especially silicon-on-sapphire transistors.

TIq. Fig. 15 shows a complementary MOS transistor circuit suitable for a computer memory circuit in a thin film integrated circuit. A sapphire substrate 40 is provided with a major surface 41 in the (1102) crystallographic orientation. A silicon layer 42 is preferably applied epitaxially by pyrolysis of monosilanes (Sill) in a hydrogen carrier gas at approximately 100 ° C.. The epitaxial

/ noooo / no / ci

The silicon layer 42 is applied with a; V'ert from about 2 to 3 αϊ per minute to a run of etv / a 3 μ .

The silicon layer 42 is then made by standard diffusion processes heavily doped with phosphorus. For the sake of simplicity, the silicon layer 42 can preferably have a constant diffusion source are doped from phosphine gas in an open-pipe system. The location is preferably set to a surface contaminant concentration doped between -1 10 and 1 χ 10 / cm.

The silicon layer 43 is then epitaxially grown and simultaneously weakly doped, preferably by pyrolysis of monosilanes in hydrogen gas as described above, to a Form nn junction 44 with the silicon layer 42. The silicon layer 43 receives a doping of the η-type with an impurity

14 3 gation concentration of about 5 χ 1.0 / cm by continuous Feed preferably of Ar sin (AsH «) into the epitaxial System from a constant source. The epitaxial application is preferably carried out at a high speed of for example 5 η / min to self-doping of the silicon layer 43 from the silicon layer 42 to reduce. The silicon layer 43 is preferably to a depth of about 2 to 3 η bred.

Thereafter, the silicon layer 43 is selectively masked and etched to remove areas of the layer and pairs of islands 45 and 45 (see Fig. 15) for the MOS transistors. This is preferably done using standard photolithographic processes, using a suitable etchant such as potassium hydroxide, which is crystallographic is sensitive to being used.

It is then the oxide layer 47 over the exposed areas of the silicon layers 42 and 43 with a depth of about 250 S upset. This is preferably done by vapor deposition about 700 ° C. The oxide layer 47 is then of one of the two Islands, d. H. the island 45, removed so that a selective Diffusion of the weakly doped silicon layer 43 can take place.

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It then passes through a suitable "p-type impurity such as boron Standard diffusion method into the exposed islands 45 diffused. A constant diffusion source made of diborane is preferably used. The 'silicon layer 43 in the area of Islands 45 is then compensated and weak with an impurity

15 3 cleaning concentration of about 5 χ 10 / cm p-doped.

The exposed p-doped islands 45 in the weakly doped silicon layer 43 are then made by expanding the oxide layer 47 covered. This is preferably done again by vapor deposition at about 700 ° C.

Windows 48 and 49 are then opened in the oxide layer 47 in the region of the island 46 and the heavily p-doped source and drain regions 50 and 51 diffused into the η-doped island 46. This is preferably done by photolithographic and Diffusion standard procedure as explained above. Preferably, a constant diffusion source with diborane in one Open pipe system used. The impurity is preferably

17 3 cleaning concentration about 5 χ 10 / cm to a diffusion to be obtained by the heavily η-doped silicon layer 42 and for to provide isolation of the n-channel zone 52. The impurity concentration should be kept as low as possible within the limits of the operation of the transistor is in order to obtain and ensure a pn junction with the heavily η-doped silicon layer 42 that is as insulating as possible, that the source and drain zones 50 and 51 do not penetrate the heavily doped silicon layer 42 significantly.

The windows 48 and 49 are then closed by expanding the oxide layer 47 as described above.

There are then 45 windows 53 and 54 in Danish pr-doped islands open and the heavily η-doped iource and drain zones 55

19 'and Ϊ - 6 preferably with a concentration of about 1 χ 10 / cm ~ diffused into the p-doped islands 45. This is done in turn

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by standard photolithographic and diffusion processes. A constant diffusion source with phosphine is preferably used in an open-tube process. However, it has to be on it care must be taken to ensure that the source and drain zones 55 and 56 do not penetrate the silicon layer 43 and short-circuit the switching element. Good isolation of the p-channel region 57 becomes indeterminate because of the foregoing Diffusion of p-impurity into island 45 is provided.

Windows 48 and 49 are reopened and window 58 is opened to view parts or areas of the heavily doped To expose silicon layer 42. Again, this is done using standard photolithographic and etching processes. Preferably v / ground sources 59 and 60 likewise formed in the oxide layer 47 by the etching process being stopped when the windows are formed, another part of the photomask is removed and the etching process is continued again.

Metal contacts 61 ..- 66 are formed at the same time to make ohmic contacts with the silicon layer 42 and the source and drain zones 50, 51, 55 or 56 and MOS contacts with channel 52 or 57 to form.

This is done by vapor deposition of aluminum or another suitable metal on the structure, so that the windows 48, 49, 53, 54 and 58 and the sources or sinks 59 and 60 are closed and a continuous metal layer over the oxide layer 47 is formed. A "negative" mask is then created using a standard photolithographic process and a suitable one Etchants such as 10% sodium hydroxide are used to remove the metal layer to be removed from all places except in the closed windows and sinks and in the areas adjacent to them. The metal in the windows is then alloyed with the silicon by heating the structure to lower ohmic contacts To form resistance. 1-Js it should be noted that the Decrease 59 and 60 the length and spacing of the FOS contacts

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of the channel zones.

The thin-film silicon-on-sapphire switching element thus formed is a complementary MOS transistor circuit that can operate in the boost mode. The contact 61 brings a reverse voltage at the pn junctions with the silicon layer 42, to isolate the transistor. Contact 62 is common to source zones 50 and 55 of the complementary transistor, see above that the circuit can work as a flip-flop. The circuit can thus be used in the memory circuit of a computer.

16, a similar complementary MOS transistor circuit is shown. The difference is that here the ρ (+) η (-) ρ (+) transistor is replaced by a ρ (+) ρ (-) ρ (+) transistor, which is used in the deep-depletion-increase Operating mode can work. This is done by doping the weakly doped silicon layer 43 'with a p-type impurity such as boron instead of phosphorus during the epitaxial growth in order to form a pn junction 44' instead of the nn junction 44. Preferably the impurity concentration is

13 3 kept at about 1x10 / cm in the transition area to allow in of the channel zone to provide the high resistance for operating in the deep depletion / increase mode.

This switching element has the advantage that a number of steps are eliminated that are involved in the manufacture of the complementary MOS transistor circuit are necessary, which was explained above in connection with FIG. Further a better isolation of the circuit is ensured, as there are no isolating pn junctions between the heavily doped Source and drain zone and the heavily doped silicon layer 42 'are necessary.

The present invention thus serves to produce a complementary FOS transistor by silicon-on-sapphire, which has a much lower leakage current and therefore a much lower power loss. So computers can do it

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can be made with larger memory units using CMOS transistor circuits.

Referring to Fig. 17, an express detection target for a High resolution television camera tube using the present Invention made. The sapphire substrate 70 has a major surface 71 in the crystallographic (1102) orientation Mistake. The silicon layer 72 is then applied epitaxially to the main surface 71, preferably through Pyrolysis of monosilanes in a hydrogen carrier gas such as previously described. The epitaxial application is continued until the silicon layer 7O has a thickness of about 1 uhat.

The silicon layer 72 is then made by a standard diffusion system heavily η-doped with phosphorus. Preferably, a "constant diffusion source with phosphine in an open-pipe system" is used used. The impurity concentration of the silicon

20 21 3

position 72 is therefore between 1 10 and 1 χ 10 / cm.

The silicon layer 73 is then epitaxially applied to the silicon layer 72 applied with a thickness of about 5 to 10 u in order to form an nn junction 74 with the silicon layer 72. Preferably the epitaxial application takes place again by means of pyrolysis of monosilanes as explained above. Simultaneously

14 3

the silicon layer 73 is weakly doped to about 5 χ 10 / cm, adding arsine (AsH,) or phosphine (PE) gas into the epitaxial system is initiated.

The silicon dioxide layer 75 is then formed over the silicon layer with a thickness of approximately 0.5 ″. Preferably done

ο
this by vapor deposition at about 700 C.

The micro-windows 76 are then opened in the oxide layer 75. The micro-windows 76 typically have center-to-center spacings of 12.5 to 20 Ai in a checkerboard arrangement, with a window diameter of 6 to 10, and the like. Fs can be up to

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Form 700,000 windows in one 1.2 χ 1.2 cm piece. Preferably v / ground the windows with the help of the electron image pro j ection systems manufactured as described in US patent applications Ser. No. 753 373, 869 229, 40 626 and 78 365 of August 19, 1968, October 24, 1969, May 26, 1970 and October 6, 1970, respectively is described, these applications each going back to the same assignee as the present application.

P-impurity zones 77 are then formed in the η-doped silicon layer 73 by means of diffusion through the windows 76 in the silicon dioxide layer. This is preferably done with the help of standard open-pipe diffusion processes with a constant diffusion source with diborane gas. The contamination zones 77 are preferably diffused to a depth of approximately 1 η. This creates tiny diodes in the silicon layer.

In practical use, the diodes are used as a scanning device Opposite electron beam 78, as shown with FIG. The heavily doped silicon layer 72 is thereby maintained at a positive potential with respect to a cathode 79 by means of an energy source 80, around the surface with reverse bias of the diodes to "download" an "equilibrium" potential. Interested Radiation 81 is incident from the substrate side, so that there is a charge storage in the diodes corresponding to the Distribution and intensity of incident light comes from. The scanning electron beam 78 forms the pattern of the stored charge of the diodes in an electrical input from the television camera tubes un.

The sensitivity of the rapid detection target depends only on the ability of a minority carrier hole, which was caused by electron hole generation by means of incident radiation in the field-free, heavily doped silicon layer 72, to diffuse before recombination into the charge area of the diode. Laughing at that? ^T inority holder hole the

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When it has reached the space charge zone, it becomes the p-doped zone v / pus-moving and stored as a positive charge. The true. probability of this event is called "catching efficiency" (collection efficiency). Thus, as can be seen, the hole "trap efficiency" is directly off the Minority carrier lifetime dependent, which must be in the ms range.

The present invention thus provides a high resolution image capture target made by a silicon-on-sapphire process. This results in a more durable image capture target than has previously been available. So far, such targets have been produced from self-supporting wafers made of n-monocrystalline silicon by typically etching the inner area to a thickness of about 10 to 15 η (cf. Gordon, Trans, of the Ket. Soc. Of AIME, 245 , 517 , 522-23 (1969)). Such switching elements were difficult to manufacture, had a low quantum yield and were sensitive to shock and vibration during operation. The present invention eliminates such difficulties and provides a target which is easily manufactured and which is resistant to both shock and vibration.

Patent claims :

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Claims (4)

Claims; Method of manufacturing a semiconductor switching element having a zone of relatively long minority carrier life, characterized in that in addition to a main surface one A silicon layer is formed on the substrate, which is highly contaminated with an impurity selected from phosphorus and boron is doped so that the surface impurity concentration 19 3
tration is more than 1 χ 10 / cm, and that at least in partial areas of the heavily doped silicon layer, a silicon layer is grown epitaxially, which is relatively weak with a concentration of less than about 17 3 1 χ 10 / cm is doped to form a zone with a relatively long minority carrier life. 2. The method according to claim 1, characterized in that the heavily doped silicon layer by forming the selected Contamination as at least a part of the semiconductor body will be produced. 3. The method according to claim T or 2, characterized in that the heavily doped silicon layer by diffusion of the selected impurity up to a surface impurity!
is formed. 20 3 Impurity concentration of more than 1 χ 10 / cm 4. The method according to .Anspruch 1, characterized in that the heavily doped silicon layer by epitaxial growth of a silicon layer on an insulator substrate and then diffusing the selected impurity into at least parts of the epitaxially grown silicon layer is formed. 5. The method according to claim 4, characterized in that the insulator substrate is formed from sapphire. 409829/0751 6. The method according to claim 4 or 5, characterized in that that the surface contaminant concentration of the selected contamination of the epitaxial layer is greater than 1 χ 10 / cm. KN / nb 3 4 09829/0751 Blank page