DE2362365A1 - PROCEDURE AND ARRANGEMENT FOR THE TRANSMISSION OF DIGITAL INFORMATION - Google Patents

Description

lelefonaktiebolaget IM Ericsson,

Stockholm / Sweden. .

Method and arrangement for the transmission of digital

information

The invention "relates to a method and an arrangement for the transmission of digital information, which is converted into character signals with each U- information-carrying signal elements is divided, whereby the occurrence of certain, undesired characters or character combinations in the transmission is suppressed. -

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For example, teletype and data transmission Character signals with 5, 6 or 7 bits are sent that carry information. Some of these characters or combinations of characters are used the production or handling of cable routes. For example, in telex, the character combination ZGZC means that the following text is to be interpreted as address information is, while the character combination IiNNlT is the end of, Connection indicates whereupon it is automatically interrupted »In the data transmission in 7-code (CGITT alphabet Kr. 5) individual character signals have a corresponding function.

In certain cases a text has to be spelled, whereby the text should only contain character signals, i.e. o characters that follow the instructions "Carriage Return", "New Line "," Character Shift "," Letter Shift "," Digit Shift "and so on.

In other cases, on the other hand, such binary information "may have to be transmitted via the connection of the 3-typewriter, which when subdivided ±. Characters for the transmission can cause random combinations of characters or letter letters that create line paths which, for example, cause the Connection is automatically switched off during the transmission of a message. Such binary information can consist, for example, of binary measured values.

In order to take into account all of these cases, one had to do so up to now randomly occurring "no-sign signals" in the transmitter by others Character combinations, e.g. replace double letters or characters. In the receiver, the double characters had to be returned to the original individual characters are converted back »

The equipment required for character conversion was relatively large and expensive. In addition, there was a dated

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Randomly dependent processing speed of the information. This disadvantage also made it necessary to take into account coincidences with "a large number close" together double sign of Zwiscl9 = higher to be oversized: that is necessary for the transmission in order to achieve sufficient security. "

The method according to the invention for the transmission of information, which is in character signals each with $ .Informationführend en character elements is divided, whereby the occurrence of certain, undesired characters or character combinations in the transmission is suppressed, avoids these disadvantages. The method is characterized in that in the transmitter a sequence information-carrying signal elements is generated, which are in parts is subdivided with N-n signal elements, whereby new character signals are formed by completing each part with n signal elements and are selected in such a way that only permitted characters arise and are transmitted to the recipient, and that im Receiver restored the parts with N-n signal elements by removing the η signal elements for each, character signal are, so that a sequence of signal elements arises that the .original information and which is divided into the original character signals from n, information elements.

The arrangement according to the invention for carrying out this method, is characterized by a transmitter with a first buffer for information-carrying signal elements a second buffer for the simultaneous storage of N-n signal elements read from the first buffer, by a logic circuit which, depending on the N-n signal elements, generate η signal elements necessary to achieve of a permissible character signal from N signal elements are added to the signal blocks present in the second buffer memory by means of extracting the character signals

■ 409825 / 09-05

from the transmitter, through one located in the receiver, with N-n levels and at the rate of the incoming signal elements indexable counter while it is at a standstill in η steps, through a buffer with N stages in which the rows the incoming signal elements are initiated and the is switched on by the counting pulses of the counter so that those arriving while the counter is in standstill position Signal elements disappear, and by a clock pulse source to restore the original, N-signal elements "Existing character signals always use the buffer then empties when its IT positions are filled with signal elements.

For a more detailed explanation of the invention, reference is made to the in Reference is made to the embodiments shown in the drawing. It shows:

Pig. 1 the principle according to the invention with binary series of signal elements,

Pig * 2 a transmission arrangement with a transmitter and a receiver for carrying out the invention Procedure,

Pig. 3 the series of signal elements in the transmitter at different points in the transmitter arrangement,

Pig. 4 the series of signal elements at different Points of the recipient,

Pig. 5 shows the series of signal elements in a further embodiment of the invention and

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6 shows the series of signal elements when the start and stop signals are omitted. *

The line a in Pig. 1 shows off consecutive characters existing series or series according to CGITT Alphabet No. 2, where each character consists of five bits of information carrying information. When transmitting a signal element series in which "1" and "0" alternate randomly or at will, e.g. B. in the transmission of a measurement result or tables with figures, it can happen that such combinations of signal elements occur, for example, an undesired carriage return or cause an undesirable gap. To avoid such undesired character combinations, the The invention combines the binary signal elements in groups with four bits per group (1, 2, 3, etc.) according to line b in FIG. After each group of four bits, a space is left for an extra bit to be added to form a new group with five bits according to line c that are sent. These groups now have one whole telex other meaning how out. the line d in Fig. 1 emerges.

By added to each group of four bits "1" or ¹¹ O "selects according _t you can specify the character may occur in the transmitted text the following · table shows examples of characters that should not occur in random combinations.:

00010 carriage return

01000 New line

11111 character shift

11011 number shift

00100 space

00000 character no.32

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It is assumed that the additional bit in FIG. 1 as last is added. If this extra bit is selected as "1" in the alphabet Kr. 2, for example, with the exception that bits 1, 2, 4 are a "1" can be those mentioned above Carriage Return Characters, New Line, Shift Characters, Shift Numbers, Space, character no. 32 never appear during transmission * Other characters with a "0" are also used does not appear as the last bit in the transmission. Among these characters are N and C, so that the character combinations ZCZC and MNN (address information or end of transmission) cannot occur randomly.

In the receiver, every fifth bit according to line e in FIG. 1 is suppressed. The binary series obtained in this way are subdivided into groups of five bits (line f in FIG. 1) so that the original pulse series is obtained again.

The additional bit was inserted in the transmitter after the four-bit group. Similarly, a paste is at the beginning or between the four bits in question, in which case, the criterion that the additional bit is to be a "1" or "0" is selected so that the unwanted characters can not occur in the transfer ..

The method described can also be used for character lengths with more or less than five bits. In the CCITT-Xode Wr. 5 with seven information-carrying bits, the bit flow in the transmitter is divided into groups of 6 bits, while a 7th additional bit is added and taken away from the receiver.

In principle, a subdivision into groups with Ή-η bits can be carried out in the transmitter, where N is the normal length of a character

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signal ' unä η is any number smaller than I. As a rule, however, η is equal to 1.

The beginning and end of a message can also be transmitted directly, during only part of the transmission according to the invention is processed.

In Pig. 2 shows an arrangement for carrying out the method according to the invention. Their function is based on the Diagrams according to FIGS. 3 and 4 explained. In the transmitter S they go incoming signals from input 8 via gate 11, which through a position counter 13 are controlled in a buffer 12th

The forward switching in the position counter 13 corresponds to the speed of the data pulses and appears on line a in FIG. 3. The gates 11 are controlled in such a way that the first data bit goes to the first position in the buffer, the second Data bit to the second position, etc., until the entire buffer, that in the embodiment four. Has positions, is filled, whereupon the position counter 13 in its starting position is switched back and the introduction of the impulses begins again at the first position. ·

The discharging of the data bits from the buffer memory 1.2 is effected via gate 14, · controlled by a second position counter 16, the indexing speed φ 25 is greater than that of the position counter 13. pus switching pulses for both position counter, the V / come from a clock generator 10, . in which an output a- pulses _s delivers corresponding to the rate it upcoming data pulses in row a in FIG. 3. The output b provides serial pulses in row b in IMg ₀ 3, whose speed is higher by 25 $ than the rate of pulses at the. output a. A pulse-shaped signal 'is generated at output c, which occurs during every 5 = output pulse at output b,

• ■ '■ 409825 / 090.5-

and a duration of approx. a pulse length according to line C in Pig. 3 having. The signals b and c go to the inputs of an AND gate 7, at the output of which one receives series of pulses corresponding to line d in FIG. The series agree with the impulse series b but every 5th pulse b is suppressed.

The data bits read out from the buffer store 12 reach a shift register 15 'which comprises four positions in the exemplary embodiment. According to the invention, the character signals are changed so that the character signals upon introduction, e.g. B. Y / agenretlauf, character shift, cannot occur as a result of a transmission of random binary series. Of the six characters mentioned at the outset, two end with "1", while the other four end with ¹¹ O ". If you therefore replace the 5th bit in the characters" 1 "or ¹¹ O" in the transmission, the Risk of an undesired character appearing. It can be seen that the two characters that end with "1" each have a "1" in the first, second and fourth position, while the other characters that end with ¹¹ O "do not meet these conditions.

To determine whether a "1" or "0" is the one recorded in the shift register If four bits are to be added, an AND gate 17 with three inputs, connected to the first, second, is used and fourth position in the shift register. The AND gate 17 generates a signal "1" when that position contains a "1", i.e. a character signal indicating the transmission of a character shift or a number shift (compare the table on page 5) if the following signal is a "1" should be while no output is generated when this Condition is not fulfilled, i.e. if a randomly occurring "0" for the transmission of an undesired character signal leads. This "1" or "0" is diverted depending on the content of the shift register 15 in series so that a "1"

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or "0" depending on the status of a bistable flip-flop goes to the last position of the shift register and is shifted out onto line 9 together with the recorded four bits. The bistable flip-flop 19 ^V is set to "0" or "1", this position depending on the output signal of the AND gate 17, which goes to one of the inputs of the AND gate 21, whose output signal the flip-flop to the position "0" switches, or via an inverting gate 23 to one of the inputs of an AND gate 22, the output signal of which switches the flip-flop 19 to position "1". The other input of the AND gate 21 and receives an input signal from the clock generator 10 according to line e in FIG depending on the output signals of the AND gate 17 is already set when the shifting out of a group of four bits recorded in the shift register begins. The switching of the shift register 15 and the reading out of the position of the flip-flop 19 via the AND gate 18 to the first stage of the shift register is carried out by pulses from the clock generator according to line f in FIG however, an additional bit E ... follows it. The four subsequent data pulses are then followed by an additional bit Ep, etc. The speed is 25 f * greater than that of the supplied data signal.

In the receiver, the incoming data pulses go into a sliding

30th

register with five positions according to line a in Fig. 4-A clock generator 24 generates series of stepping pulses according to line b in Figure 4. The first pulse arrives simultaneously with the leading edge of the first data pulse. The series of stepping impulses b 'going into a first counter 25§ of the five stages, i.e. e.g. B. is a ring counter with five levels. That The output signal of the counter25 is positive, with the exception when the counter is in position 5 according to line dön Figo 4.

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Pas. Outputs ^ ial ä goes to one of the inputs of an AND gate 26, which receives series of pulses from the clock pulse generator 24 at its other input according to line e in FIG. These pulse series ■ have the same pulse frequency as the pulse series b, but are offset by approximately half a pulse position. The output of the AND gate 26 thus generates pulse series according to line f in FIG. 4, in which the 5 * pulse is suppressed. The pulses go as step switching pulses to a second counter 27 $, a ring counter with five levels. This is "switched on by one step with each incoming data pulse, but not by the additional pulses E ^, E ₂ , etc., since the output pulse from AND gate 26 is blocked during these pulses according to line f in Mg. 4. The counter 27 delivers a stepping pulse to a shift register 30, which also receives the incoming data pulses, when the stepping pulses of the counter 27 are used, but no stepping takes place during the additional pulses E., Ep etc., so that Only the data pulses following the extra pulse go to the shift register according to line g in Fig. 4. The shift register 30 thus contains a group of five bits in their original form one of the inputs of an AND gate 28 according to line h in FIG. 4. The other input of the AND gate 28 receives a pulse l series according to line b in FIG. 4, so that a pulse according to line i in FIG. 4 occurs at the output of the AND gate 28. This pulse is used to control a gate 29 which shifts the content of the shift register 30 in parallel to a shift register 31 with five stages, from which it can be diverted in a manner known per se according to line k in FIG. . ■

Fig. 5 shows an alternative embodiment for delivery of the Data pulses from buffer 12 to shift register 15 in Fig. 2. In this case, the pulses b consist of pulse series with such a high pulse frequency that a transmission of the

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Pulses in series form during part of a data pulse period becomes possible.

The output of the UHD gate, s 7 is normally blocked and only for a short period after the receipt of the first four data pulses according to line c in Pig. 5 fr.ei, so that four step switching pulses according to line d in FIG. 5 go to the position counter 16. The four data pulses recorded first in the buffer memory are successively applied to the shift register 15 at high speed. A test pulse e, which occurs as the 5th pulse after the four pulses according to line d, sets the gate circuit 19, ^as explained above, in the "0" or "1" position. Thereafter, the shift register 15 is switched on by stepping pulses, the speed of which is 25 $ greater than the speed of line f in Pig. 5. Line f in fig. 5 also shows the data pulses fed to the output of the shift register and thus to the transmission line

In a further alternative of the method according to the invention for recording the data signals coming to the buffer store 12 in the transmitter, the signals that are assumed to be available in parallel are fed to the buffer store, specifically via a gate arrangement (not shown) by means of rapid stepping pulses according to "Line a ^! In The recording pulses have such a high frequency that a group of 5 bits can be written in between two readout points.

In the exemplary embodiments described, the data rate at the output of the transmitter is 1.25 times the data rate at the input, of the transmitter. In certain cases, however, the input and. Rejection speed are kept at the same value,

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e.g. in the pail, if the input and output are from a strip reader or a strip punch "consist of the same Motor driven v / earth.

In this case, the arrangement works as explained in Pig. 3 and 4 with the difference that the entry and exit speed is the same with which the buffer must be increased when the output signals with an additional data pulse E are completed. For each character supplied with five data pulses, four data pulses plus one additional data pulse are output, so that the memory must contain as many positions as this corresponds to the maximum number of characters which are supplied during a transmission.

In a start-stop system, in which each character is preceded by a start pulse or followed by a stop pulse, only the information-carrying impulses to the buffer. When escaping the signals from the transmitter on the line will initially be a new one Start signal generated and emitted after four information-carrying pulses together with the additional ones previously mentioned pulse E were emitted, whereupon a stop pulse is generated and emitted. The procedures described are also Applicable here, but with time for the start and stop pulses available and the clock pulse generator must be dimensioned for this purpose. A shift register 15 can for example with 7 positions, of which the first always corresponds to a start pulse and the last to a stop pulse.

Pig, 6 shows how the Pig. 2 can be used to eliminate not only the additional data pulses E ₁ , E ₂ and so on in the receiver, but also the start and stop pulses. Row a in Pig. 6 shows incoming signals with start-stop signals in series form “stepping pulse series according to cell b in FIG. 6, with a stepping pulse at the beginning

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Each incoming: "data impulse,"switch; the counter 25 further, in this case there is a single-disk counter, for example a ring counter. The number position: appears in line-o- in Fig Count * generates a positive output - if its counting position is 1.6 and 7 ", in which position the UHD gate 26 blocks, while" with the pulse positions 2, 3> 4 and .5 <ias UIID -Gate 26 is open so that pulses E can pass according to line d, e or f in FIG explains _r further. The switching takes place only in the signal positions 1, 2, 3 and 4 and then comes to position 5, during the first position of the following character signal, as follows from line g in FIG. In this way both the start and stop signals and the B extra pulse B disappear. As explained in connection with FIG. 4, the position 5 of the counter 27 generates an output h which goes to an input of the AND gate 28, the second input of which receives the pulse series b. The output signal i of the UMD gate 28 is used to control the gate circuit 29, which transmits pulses with five data recorded in parallel in the shift register 30 to the register 31, from which the original character is read in a known manner in serial or parallel form can. ·

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Claims (2)

P a t e η t a η s ρ r ü c h e Method for the transmission of information expressed in character signals elements with each K information-carrying signals is divided, the occurrence of certain undesired characters or character combinations is suppressed in the transmission, characterized in that a sequence in the transmitter information-carrying signal elements is generated, which are in parts is subdivided with N-n signal elements, whereby each part is completed with η signal elements, new signal signals formed and selected in such a way that only permitted characters arise and are transmitted to the recipient, and that in the receiver the parts with N-n signal elements by removing of the η signal elements are restored for each character signal, so that a sequence of signal elements arises, which carries the original information and which in the original character signals from IT information elements is divided. 2. Arrangement for carrying out the method according to claim!, Characterized by a transmitter with a first buffer for information-carrying signal elements by a second buffer for the simultaneous storage of N-n signal elements read from the first buffer, by a logic circuit that depends on I-n signal elements. η generates signal elements that are used to achieve a permissible iSeichensignales from ΪΓ signal elements signal elements present in the second buffer are added by means for extracting the character signals from the memory, through one arranged in the receiver with N-n stages and at the rate of the incoming signal elements switchable counter, while it is in η steps ^ 09825/0305 / s \ -: ■■■ ....; ■ style divides, through, a buffer with N levels, in which initiated the rows of incoming signal elements be, and the by, the counting pulses of the counter so on is switched that the during the standstill position of the Signal elements arriving at the counter disappear, and a clock pulse source is used to restore the original character signals consisting of IT signal elements always empties the buffer when its K Positions are filled with signal elements. 409825/0905 Blank page