DE1762388C - Tactile bistable circuit - Google Patents

Description

1 2 ^

The invention relates to a tasibare bistable switch Fig. 1 is a Blockdarsteiiung of a gate of the in

King with several interconnected thresholds the type used in the present circuits,

werigate. Fig. 2 is a block diagram of a tactile JK

Bd threshold value logic circuitry is the threshold flip-flops according to an embodiment of the

Wertgatter a common structural unit. A 5 finding,

Schwdlwertgutter has several inputs, to which Si- Fig. 3 is a block diagram of another embodiment

signals are supplied, which represent binary form of the invention and

and in each case an effective weight of one or Fig. 4 is a block diagram of a third; Execution

have multiple units. The embodiment of the invention generated by the gate.

The output signal indicates whether the threshold value of the gate io Fig. 1 shows the block diagram of a majority window has been exceeded or not. Majority and minority gates with three inputs, each of which is minority gates are special cases of threshold values with the weighting factor ΐ. An input signal gatterr., Which has proven to be particularly useful in the threshold value logic, the gate with twice the weight, i.e. dopders. An example of a mapped effect that can be supplied by joritäts ^ atters is a threshold value gate to which an odd number η of input signals is applied to two input terminals of the gate at the same time. On the other hand, an input terminal can be those that each have the weight factor 1; have twice the weight factor, if you have the threshold value (n + l) / 2 in the gate and delivers an interior of the not shown in detail sibling output signal, the value of which is equal to the control arrangement of the gate a resistance in the value of the majority of the inputs of the gate 20 Series switches, which has half the effective value is supplied binary input signals. An example, such as the resistance of an input terminal with a minority gate, is a threshold value gate which is connected in series with a weighting factor of 1.
an odd number η of binary input signals to- In F i g. 2 is introduced as an exemplary embodiment of the invention, each having the weight factor 1; A so-called ./-K- flip-floo is shown, which the threshold value gate again has the threshold value 25, four threshold value gates M1 to M 4 (which are connected to each other in the (/ jtl) / 2 and yefen a binary output signal, which is shown The same as the minority of the inputs of the gate inputs of the first gate. Af1 are one of the bi-associated binding signals. A fixed bias voltage corresponding to the majority-minor G with the nority gate delivers two A "sgangr, signals, of weight factor 2 , a key signal T, a first control to which one of the majority and the other of the 30 signal / and the fourth input signal a signal W minority of the input signal "; corresponds to the gate. The inputs of the second gate Af 2 The output signals are therefore complementary . are the preamble corresponding to the binary digit 0

In the construction of digital data processing systems and the like, the voltage signal with the weighting factor 2 is what Tastman strives to use as few different _{signals T 1} as possible, a second control signal K and the fourth circuit units to produce the input signal W. To make the entrances of the dritlung more economical. It is therefore first gate M 3 are 'las c! The minority function wishes to be able to implement both logic circuits and memory-corresponding output signal H of the gate AfI, circuits using the same basic output units corresponding to the majority function. signal Y from the second gate Af 2 and a third input

The present invention is accordingly supplied with 4 ° output signal Z. The gate M 3 delivers a

the task is based on a palpable bistable switching majority aur. output signal W and its complete

specify processing that listed from Schwellwettgattern W. ment are the inputs of the fourth gate Af 4

is built as it is for the realization of logical the majority output signal X of the gate AfI,

Functions can be used. the minority output signal Ύ of the gate Af 2 and

In the present bistable circuit, the 45 can be supplied with the signal Z as a third input signal. This common third input signal Z is the trigger signal, which is fed to inputs of a majority output signal generated by gate M 4, first and a second gate. The bistable circuit contact key signal shown in FIG. 2 can work as follows at different times: If the key sensor, which represents a binary 1 or a binary 0 signal T, has the value 0, the circuit stores it put. If inputs of the first two gates earlier output signal Z is independent of the Wer bias signals as well as a key signal, the den- ten of signals J and K. If key signal T - \ has the same binary value as the bias signals, it causes the gate the values of the signals / are supplied, supply the outputs as gates and K sample. During this scanning process, the signals from constant hosts hang. The information stored in the bistable value of the output signal Z vnn of the respective Wer circuit then retains its ten ier signals J and K. Namely, if Γ - ■ = 1, value at, regardless of which values signals, the circuit according to FIG. 2 works as follows: have the other inputs of the two a) If J ~ \ and KO (in the following briefly: first On the other hand, if the JK = 1-0), the output signal Z is unscrewed and the second gate is a key signal drawn 1.

which leads to the opposite binary value b) If JK = 0 * 1, the output signal Z is un-

has like the bias signals, all Gates conditionally speak to 0.

ter and supply output signals which have the value c) If JK = 1 * 1, the circuit changes and corresponds to further input signals which determine its operating or memory status.
Inputs of the first two gates fed 65 d) Finally, if JK = OO , then T = I occurs. no change in the output signal.

The invention is described below with reference to the details of the work *

Drawing explained in more detail, it shows wisely. If T = O, that has

T ³

Mayontats output signal X of the first gate M 1 ^ .. obviously has the value 0, since the majority of the influence signals, taking their weight factors into account, has the value 0. Correspondingly, if Y = 0, and the acsgangssignul Z remains unaffected or stored, i.e. X = 0. Y = 1 and, accordingly, ZLZ. If 7-K = 0-0 and T becomes 1 (wae should be denoted by T ^ 1), the output signal * desGaltersMl = 0, namely equal to the value of the majority of the weighted input

initially 7. - 1 and W is -I. if / takes the value 1. Y to I. wuhr, ndJ «Jη W ι

keep. Y becomes I, you / - K- '. ^US , ", 'Weight- _{speaking preload B} ss, gnal dus ^ ™" ¹ · factor 2, compensated, so that correspondingly ^co ^ n ^ en Ml T = J = \ and that of the Wu. 0 bias signal so that J-AV ^ now have X = Q and T-J st * we. _that

gangssignaje des % \ lcrsM4denW « The change

cn p ü

ss

- η Y-I and Z = Z are

»5 initially has the value 1

the Wen. dr Vorspannes- and entranc _"6 ssignale / T and G of the ₁₁ Ml KrS _s are facilitated moderately distributed between 0 and 1, so that b) the ninganessigna, IF the Who, of the output.

that of the gate «* H - 0. If now [that! "W ^ ·> the gate M 1 the ™ e,

U.N
ss.gnai λ

ü. Now have Z au,.

it can be seen that X = Y under these circumstances. For example, if Z is initially 0, then the majority of those applied to gate M will have 3

-S and

if it

becomes a, so Z

and

_the circuit arrangement explained above the a, s emem Minon-

has the value 1, it remains 1 because T is also 1. So if / -K = 1-0 and becomes T- * 1, w.rdZ- * 1, regardless of what value Z had before and what other conditions still exist.

The mode of operation of the circuit for J- X = OI and T ^ I is complementary to the above-described functional sequence. Since K = T-1 and the preload to which the weighting factor 2 is assigned has the value 0. the output signal y of the gate M 2 is equal to »f. Since the majority of the input signals fed to the gate MI, taking their weight into account, have the value 0, # = 0. If Z initially has the value 0, Z = JT = O. and the gate MA further supplies the output signal Z = O. However, when the seventh initially had a value of 1, the OAT ^J TERM3 supplies the output signal W = \ because Ύ "benfalb fen is 1. As a result, the output signal Y of the gate M 2 becomes 0. Since both ^ and 7 now have the value 0, Z becomes 0. This influences the output

^{M3hl a} The output gate M

of Fig. 2 ^en «P" cht, _isi e '"

_{mil are jc} .

SgÄS ^ hold. are) zuwe U ^ wei fcingangen * ° P. ^B , _{the weight is} guided so that this _{step corresponds to the}

factor ζ have-Da ^ s Gat H τ M9 ka ^

* two of which have the weight class of the first gate

^ / ^^ ^ ^C bias signal 0 is Ml ι Fig. J ^;} ™ ^ _in ^P _Fig . 3 shown

gj JJj ¹¹ ^ «gj» i ^ Luer signal C supplied. The

* ■ «-1 r« t «? Enters the data signal into the ggnriG controls the input «I S ^ ^^

° ^l5t *,! JS If the weighting factor 1 is used, gates W8 become the third of _{the Wef}

_{G and the} data signal / i assigned

_b ■ _the output gate ^ ^ _{threshold gate} .

_Q
tee U ₁

leads

When O Ji

which is stored by the gate M4, initially has the value 1, Z = TC-I and the majority »- p catch that i

J _abhä depends. If t. B. ^ ₌ ^ 8 _di

In explaining the operations that

and Z - 0,

_{Value def s} , _

then, calculated from left to right, the input = 0, the majority of the input signals of the

signals 1, 0, 0, 75, 75, 1 and 0, so that the output gate M10 has the value 0 and # = 0. Jn corresponds to

signal Z assumes the value D. The output signal, similarly, has the majority of the input signals

of the bistable circuit can from the 2 delivering the second gate MIl the value 0 and Y = O. The

Terminal are removed so that the output 5 has the majority of the inputs of the third gate M12

signal Z = D is available. has the value 0, so that W = - Ü. If now T- * becomes 1, has

In the functional example of the circuit according to the majority of the inputs of the first gate M10

Fig. 3, in which Z initially had the value 1 and the value 1 and X = \. The majority of the entrances

W, as explained, was 1. can with G- * 1 the signal Y of the second gate MIl, however, has the value 0 and

be either 0 or I, depending on which values Γ ίο Y - 0. Since X = 0 and K = O, the majority is the

and K , while X also have either 0 or 1 inputs of the third gate M 12 equal to 0, and W

can be whatever of the values of the signals T and J remains 0. Since X 1 and 7 = 1, the majority has

depends. However, if λ "= (), Y must have the value 0 of the inputs of the fourth gate Λ / 13 the value 1,

there to make X 0 for (7 - = 1 and W ~ {) , and Z becomes 1.

the input signals 15 must be at the first gate M5.If T- * becomes 0, the majority of the inputs have 7 - J - 0, while if T = O at the second gate of the first gate M10 the value 0 and X = Q, Gate, the majority of the input signals and the majority of the inputs of the second gate has the value 0 and Y is 0. The effect of the input MIi has the value 0 and Y1, so that Z- 1 feed signals from the first and second gates M5 and M6, respectively, are cherted. On the other hand, the majority of the inputs on the output gate Λ / 9 consists in the access of the gate M12 the value 1, since ZX- 1, leads to an input signal V which is either 1 and 1. If T becomes 1 again, the majoriodcr can be 0, while the input signal T occurs at the inputs of the first gate M 10 the value 0, neither 1 or 0, if A "= 1, while it and XU Inputs of the second for A " - 0 is always 0. So if Z is initially the gate M11 is 1 and V = I. Since A "- - Y == 0, has the value 1 and G takes the value 1, the 15 * iie majority of the inputs of the third gate M13 receives the lower gate M 9 input signals, the value of which of the value 0, and Z becomes 0. When T becomes 0, the current values of the signals T, J and K majority of the inputs of the gate MIO depends on the value 0, that is (from left to right ) either the and X = Q correspondingly also Y = O. The signals 1. 0, 0, D, D. 1, 1; 1. 0, 0, D, 15, 0.1 or inputs of the third hater are now X - \, Z = 0, 0. 0, 75, 75. 1, 1. In all cases the majority assumes 30 and Y = 0. so that W becomes 0 and the circuit status output Z takes on the value 75. is back to its initial state by

A particularly advantageous property of the signal T described above for a new duty cycle The circuit consists in the fact that this is information.

mation input signal in one duty cycle vcrar- If initially T = Z = O and the set signal is 5

is asked. In other words, when 35 becomes 1, the majority of the input signals has the

Applying the control signal, the information signal, the first gate MIO the value 1, since TF accordingly

can already exist beforehand, immediately before the previously explained initial conditions S-R = T

is working. - 0 has the value 1. X therefore has the value 1. The

FIG. 2 shows, as a modification of the majority of the input signals of the second gate shown in FIG

set circuit a tactile flip-flop with set and 40 MIl is 0, and Y is 1, so that the majority of the input

Reset input. It results when / and K output signalc of fourth gate M 13 has the value 1

can be made equal to 1 and one of the prefixes and Z becomes 1. Since X = O and Y = O, the Ma-

voltage signal c 0 of the gates Ml and M2 (Fig. 2) joritäl the inputs of the third gate M12

compensate. The threshold value gates M1 and M 2 value 0, and W remains equal to 0. When the set signal S

If two majority-minority 45s assume the value 0 in FIG. 4, M 13 is on the fourth gate

Gate MIO or MIl. each of the three inputs to the input signals λ "= 0, Y = I and Z = I, so that

point. The gates are stored in the circuit according to Z = I, while cle inputs of the

FIG. 4 connected to one another as in FIG. 2. The third gate M12 is T = Z = I and W becomes 1.

Inputs of the first gate MIO are the key If Z is initially 1 and the reset signal R

signal T, the signal H 'and as the third signal at point 50 becomes 1, while T = 0, has the majority of the

of the fixed bias signal 0 in FIG. 2 a set input signal of the first gate M10 has the value 0.

signal S is supplied, which normally has the value 0 since 5 - T = WQ, and X is 0 accordingly.

and takes the value 1 when the circuit is set The majority of the input signals of the second gate

shall be. In a corresponding manner, the MIl has the value 1 on the other hand, since T = O and

Inputs of the second gate M 11, the key signal T, 55 R = W = I is. As a result, Y = I. and the ma-

the signal W and a reset signal R supplied, the jority of the input signals of the four'cn gate M12

also normally has the value 0 and for Zu- has the value 0, since X = Y = 0, so that Z becomes 0

Reset the circuit to 1 can be changed. This has no influence on the third gate M12. d;

The circuit shown in Fig. 4 operates as X = Y = I. When the reset signal becomes 0, ha

a tactile flip-flop that sets and resets 60 the majority of the inputs of the first gate M11

can be. In short, since S = T = W = O and X = Q, the state of vom becomes true

Gate M13 generated output signal Z for each the majority of the inputs of the second gate Ml

Supplying a key signal of the value 1 changed, has the value 0, since T = R = O, so that XQ is

when the set and reset signals have the value 0. Since Z = O, the majority of the inputs of the drii have

On the other hand, when R = T = O and S becomes- ^ 1, the 65th gate becomes 0 and W = O. This has none

Z = I, while for S T = O and R - »■ 1 the off influence on the first two gates MIO and MY.

output signal Z assumes the value 0. and Z = O is stored.

If Z initially has the value 0 and S = R = T In summary, the i works

F i g. 4, like a tactile, set and resettable flip-flop, the output signal of which is unconditionally switched by the tactile signal T = I, while the set input signal 5 = 1 sets the output signal to the binary value 1 and the reset signal R - 1 sets the output signal to the Sets binary value 0. Since the in F i g. 4 consists of the same type of gates, it can be easily produced on a large scale as an inief ured circuit. - »o

Claims (4)

Patent claims: i. Bistable circuit for storing a signal with a number of interconnected Schwellwfrtgattern, characterized in, that the storage of new information can be controlled by a key signal (T) that a first and a second gate (Ml, M2; M5, M6; MIO, MIl) is supplied and the di- ao närwert O or 1 represents that all gates (Ml to M13) output signals of constant values deliver bias signals and when corresponding to the inputs of the first two gates the key signal is supplied with the same values ■> "> den, and that all gates supply output signals which correspond to the values of further input signals which are supplied to the first and second gates when the bias signals and the key signal, which are fed to the inputs of the first two gates, have different values to have. 2. Bistable circuit according to claim 1, characterized in that the first gate (Ml) has two outputs (X, Ύ) which deliver output signals corresponding to the majority or minority of the input signals of the gate; that the input signals fed to the inputs of the first gate a bias signal (0) fed with the weight factor 2 as well as the key signal (T), a first control signal (J) and a first signal generated in the circuit (W), each with the weight factor 1 are supplied include; that the signals fed to the inputs of the second gate (M 2) are a bias signal (0) fed with the weight factor 2 and the key signal (T), a second control signal (K) and a second signal (W) generated in the circuit , which are each supplied with the weight factor 1 to ^f assen; that the minority output signal (X) of the first gate (M 1), the majority output signal (Y) of the second gate (M 2) and a third, generated in the circuit signal (Z) the inputs of a third gate (M 3 ) are supplied, which has a minority output and a majority output, the first and second signals generated in the circuit (W, W) , and that the majority output signal (A ") of the first gate, the minority -Output signal (Y) of the second gate and the third signal (Z) generated in the circuit are fed to a fourth gate (M 4) which has a majority output which supplies the third signal (Z) generated in the circuit. 3. bistable circuit according to claim 2, characterized in that the first and the second bias signal consist of the same signal. 4. Bistable circuit according to claim 2, characterized by a fifth threshold value gate (M 8) to which the first bias signal (G), the second bias signal (0) and a data input signal (A) are fed to corresponding inputs, and that additional inputs of the fourth A minority output signal (D ) generated by the fifth gate (MS) and the second bias signal (0) each with the weighting factor 2 are supplied to the gate (M9) (FIG. 3). 1 sheet of drawings i c