DE1474013C - Feeding device consisting of a current means clock pulse generator for several current means flip-flops connected together to form a logical unit - Google Patents

Description

The present invention relates to a fluid timing pulse generator Feed device for several flow medium flip-flops connected together to form a logical unit, which the working flows via a working flow inlet duct and control signals can be supplied via control flow inlet channels.

A plurality of fluid flip-flops are typically used in fluid operated logic circuits with other fluid switching elements, e.g. B. AND, OR elements, inverters and the like, connected together so that in each case a control signal is transmitted to a fluid flip-flop a control flow inlet passage to divert a working flow and so any perform logical functions. To ensure a fluid flip-flop in such a case To be able to switch, a relatively strong control signal is necessary.

In John Roger Greenwood's dissertation, The Design and Development of a Fluid Binary Logic Element, "Massachusetts Institute of Technology, May 1960, are powered by a fluid-timing pulse generator controlled feed devices for bistable flip-flops, which the working currents via a Arbeitsströmiigseinlaßkanal and control signals via control flow inlet channels / u are described. But there are the control signals not introduced in time so that they can have a lower strength than usually for Switching of a flowing working stream from one outlet channel to the other is necessary.

U.S. Patent 3,016,066 discloses a fluid pulse generator described, which essentially consists of a flow amplifier with an input channel and two output channels,

ίο in which the opposing control flow inlet channels are connected to each other. However, this publication does not teach any use of the fluid pulse generator for a feed circuit of the type mentioned at the beginning.

The invention is based on the object of providing a feed device of the type mentioned at the beginning make it possible to use fluid flip-flops with control signals of relatively low intensity get along.

ao This object is achieved in that, according to the invention, the control signals are interposed in the clock pauses two working flow pulses of the fluid clock pulse generator and overlapping with whose use can be entered.

In addition to the advantage that the control signals can have a relatively low intensity, is through the feed device described also achieves that the fluid pulses generated by the logic unit are synchronized.

The advantage of the lower control energy is achieved in that the control signal is not as before a predetermined minimum thickness, which is used to detach the working flow from the wall as a result of the Negative pressure between the wall and the working jet is required, must have. Since the control signal already while the working flow flows during the pulse pauses, the control flow only has to be the Do not determine the direction of the working flow that only begins when a control flow is present however, overcome the adhesive force of the working flow.

Embodiments of the invention are explained in more detail below with reference to the drawings. It represents

F i g. 1 a feed device for several fluid flip-flops interconnected to form a logical unit,

2 shows the waveform of the clock pulses generated by a clock pulse generator at two outputs, F i g. 3 a feed device with a clock pulse generator with four outputs,

4 shows the waveform of a clock pulse generator the feed device of FIG. 3 generated clock pulses,

5 shows a feed device with a clock pulse generator, which has only one output, FIG. 6 shows the waveform of a clock pulse generator the feed device of FIG. 6 generated clock pulses,

Fig. 7/4 for use with the feed device according to the invention suitable fluid flip-flop,

Figure TR shows the logical symbol used in the drawings of a fluid flip-flop.

According to FIG. 7 A, there is a known fluid flip-flop 1, which occurs in the logical

. Schallung is used, essentially from one Body in which a working flow inlet channel 3,

3 4

a first and second control flow inlet channel 5 The logical networks A and B are therefore

or 7 as well as a first and second outlet channel 8 representing any combination of digi-

or 9 are provided. talents, to carry out tax or arithmetic

A flow-actuated flow line provided functions as a pipeline 21 in the drawing is connected to the working flows. For example, the networks can connect the inlet duct 3 in order to supply flow to it from a flow-actuated logic element of a counter-external flow source. Represent in lers or shift registers,
Similarly, the pipelines 23 and 25 are connected to the control flow inlet channels 5 and 7 via provided on the pipelines 27 and 29 to feed this control flow from external flow taps for the detection of the output signals. The outlet channels 8 and 9 of the fluid flip-flops,
are connected to pipes 27, 29 so that the in F i g. The device illustrated in Fig. 1 operates the output signals of the other amplifier as follows: Assume that the clock-operated devices can be supplied with pulse A 'of the fluid clock pulse generator. 15 tors 39 sew to its end. At that time, that flows

In Fig. 7 B is that in FIG. 7 A shown flow fluid from fluid clock pulse

medium flip-flop FF in schematic form generator 39 via the pipeline 40 and the pipeline

shown. lines 21 to the working flow inlet channels

The control flow energy required to switch the fluid flip-fluid flip-flop of the logic network-flop can be 20 factory A. , which simulates periodically interrupts and in the presence of gnale it initiates again at the beginning of the clock pulse A ' from the logic control flow. The tax streams see network B have received. The logical network flow can be initiated as long as the flow system A does not yet receive any working flow 25 27 ·, 29 flow signals from its flow medium via predetermined pipelines. But you can also before the sub-flip-flops. Under the influence of these signals, the working flow can be initiated if the energy of the network A of the control flow inlet channels is less than the energy required to switch the fluid flip-flops of the logical network amplifier. plant B flow signals via predetermined pipe

The in Fig. 1 illustrated block diagram of a 30 lines 23, 25 to. The other fluid supply device for several, to a logical one-flip-flops receive during the clock pulse A 'called interconnected fluid flip-no working flow from the fluid clock-flops consists of a first logic network pulse generator 39 and therefore do not generate any output A and a second logical network B output signals.
like a fluid clock pulse generator 39. 35 At the end of the clock pulse A ' the flow ends

The fluid clock pulse generator 39 generated by the logic network A and the supply of fluid output signals are transmitted via the pipe fluid to the working fluid inlet lines 23 and 25 to the control fluid inlet channels of the fluid flip-flops of the logical channels of the fluid flip-flops Logical network A and starts feeding from Strö network B. In the same way, the fluid flip-flops of the fluid flip-flops of the network fluid output signals generated by the logic network B to the working flow inlet channels via the pipelines 23 and plant B. Fluid flip-flip-flops of the logical network A pull-flops one of their two stable states, ever conducts. 45 after whether the control signal from network A via

Via the pipelines 27 and 29, the pipeline 23 or via the pipeline 25 via output signals of the fluid flip-flops that will carry. As soon as this fluid flip-logic network B is at the inputs of this network-flop in one or the other of its two stabilizers B and the output signals of the fluid states are located, the logical network-fluid flip-flops of logical network A receives about 50 works B in each case a flow signal from these flow inputs of the logic network A. medium flip-flops via their pipelines 27

The fluid clock pulse generator 39 or 29.

alternately generates phase-shifted clock pulses The logical network B leads with the

A ' and B' at two outputs. In Fig. 2, the conducted signals are the desired logical operational

idealized waveforms of the clock pulses A ' and 55 nen and begins after a short period of time with

B ' shown. the generation of output signals that control the

The clock pulses A ' are the working flow flow inlet channels 5 and 7 (F i g. 7 A) of the flow inlet channels of the fluid flip-flops of the medium flip-flops of the logic network A logic network A via the pipe 40 and predetermined pipes 23 and 25 the clock pulses B 'are applied to the working flow inlet 60. The working flow inlet channels of the channels of the fluid flip-flops of the logical fluid flip-flops of the logical network network B via the pipe 42 are supplied. Since plant A , however, receive the clock pulses A ' and B' alternately in time on- ses B ' no fluid is coming from the fluid, so working flows flow alternately clock pulse generator 39, so that the logic in flip-flops of one or the other logic network 65 Network ß generated signals at this time we work A or B. remain unaffected.

The present invention is in its application. At the end of the clock pulse B ' , the ar-

not restricted to a particular logical system. flow inlet channels of the fluid

Logic network A flip-flops from the fluid clock pulse generator 39 fluid while at the same time stopping the supply of fluid to the working flow inlet channels of the other flip-flops.

As soon as the fluid begins to flow in the fluid flip-flops of the logic network A , these are switched to the first or second stable state, depending on whether they receive a control signal via the pipe 23 or via the pipe 25. The output signals of the fluid flip-flops of the logic network A are fed to this, which after a short delay generates output signals which are fed to the control inlet channels of the fluid flip-flops of the network B.

If the working flow ceases to flow in the fluid flip-flops for network B , output signals will no longer be generated by network B after a short period of time.

The sequence of steps described above represents a complete cycle of operation of the feed device This sequence of steps is repeated as long as the working flow inlet channels of the fluid flip-flops Received clock pulses from fluid clock pulse generator 39.

As mentioned above, between the occurrence of a fluid signal at one of the Inputs of the networks and the subsequent occurrence of a fluid signal at one of the Outputs of the networks a delay or runtime, the duration of which depends on numerous factors, such as the length of a particular flow path through the network, from the switching time of the logical elements that a signal passes through on its way through the network etc. The signals generated by a network can therefore occur at different times but re-synchronized by the fluid flip-flops during the other clock pulse, so that they all get into the other network at the same time.

The theoretically maximum permissible runtime between the occurrence of a signal at an input one of the networks and the resulting output signal is half an operating cycle, d. H. a clock pulse. In practice, the maximum permissible transit time of a signal through a network must be however, be smaller than half an operating cycle in order to be able to take further runtimes into account, such as, for example, the transit time of signals transmitted via the pipes 23 and 25 from the output of a logical network to the flip-flops of the other network.

In addition to synchronizing, the transmitted signals from the fluid flip-flops are also used reinforced. This reinforcement is done by changing the direction of the working currents with the help of the relatively weak control signals generated in the networks. Since the control signals also do not have to overcome the forces that cause the working currents to stick in the amplifiers, This results in a greater gain without changing the calculated amplifier properties.

Conventional fluidic flip-flops can thus be used for the synchronization, with the degree of amplification required in the logical networks being reduced at the same time. This is true of both fluid flip-flops of the type illustrated in Figure TA and eddy current controlled amplifiers and other known types of fluid amplifiers.

In Fig. 3 is a feed device for the networks A, B, C and D and four groups of bistable amplifiers 41, 43, 45 and 47. A four-phase fluid clock pulse generator 65 is associated with this device.

ίο The fluid clock pulse generator generates clock pulses A ', B', C and £) 'which the working flow inlet channels of the bistable amplifiers 41, 43, 45, 47 of the logic networks A, B, C, D via the pipes 57, 59, 61 or 63 are supplied. The timing of these pulses can be seen in FIG.

The logic networks A, B, C and D as well as the four groups of bistable amplifiers (flip-flops) are interconnected to form a closed loop, with a fluid flip-flop group between each two successive networks. The output signals of the logical Γ> network A thus pass through the bistable amplifier 43 and arrive at the logical network B.

The output signals of the logic network B pass through the bistable amplifiers 45 and arrive at the logic network C , etc. The thick lines each denote a number of connecting lines. Data, ie, signals, from external sources are fed to the system as described in connection with FIG. 1 was described.

The operation of this feed device is similar to that previously described, so that a detailed Description unnecessary.

In Fig. 5 shows a feed device constructed in accordance with the present invention; which feeds a plurality of fluid flip-flops. These include a logical network 67 and a plurality of delay elements

69. A fluid clock pulse generator serves as the feed device 71

The fluid clock pulse generator 71 continuously generates a series of - ■■ at its output Clock pulses that pass through the working flow inlet channels of all fluid flip-flops Pipes 73 and 21 are fed. The signals generated by the fluid flip-flops arrive Via the pipes 27 and 29 in the logical network, which in turn sends flow signals the lines 68 emit.

All lines 68 are each connected to a delay element 69, the output of which is via a pipe 23 or 25 connected to the signal inlet channel of one of the fluid flip-flops is. Flow capacities such as, for example, can be used as delay elements or several chambers interconnected by lines, so that between the occurrence of one Flow signal at the input of a delay element and the appearance of this signal at the output of the element elapses a predetermined period of time.

In the case of the FIG. 5 illustrated embodiment it is essential that the energy of the steep currents which are fed to the fluid flip-flops via pipeline 23 or 25, is smaller than the one required to switch the flip-flops by removing an existing boundary layer

7 8

required energy. This means that the control currents continue to open during the time when these new Si

must on the one hand be so strong that the working signals are fed to the fluid flip-flops

Currents can deflect as soon as they begin to flow. The working currents therefore retain as a result

begin, on the other hand, however, not be so strong that the boundary-layer effect contributes to its old flow path.

you can change the direction of a working flow.

as soon as this flow is fully switched on to flow. For this reason, the strength of the

has to indulge. Signals are limited.

To limit the strength of the control currents At the end of the first clock pulse time the interrupts

can be briefly in the lines 68 and the pipelines fluid clock pulse generator 71

23 and 25 and / or in the control flow inlet ca- io the supply of fluid to the flip-flops,

signal attenuators, such as flow restrictors, the duration of this interruption must be so long,

are provided. In Fig. 5 such throttles are that in the chambers of all fluid

not shown, since their number and arrangement of flip-flops then no longer work flow

Can be different from case to case. Sometimes let it flow.

15 After this interruption has elapsed, the The signals supplied to 27 and 29 even have a wide inherent resistance due to the fluid clock pulse generator dampen the network, so that ren clock pulse, whereupon in all flow with ^ further attenuation of the working flow occurring again on line 68 tel flip-flops Signals before they are forwarded to the ginnt. As a result of the network and delay control flow inlet channels unnecessary. ao approximately elements 69 caused the transit time of the signals

As soon as the clock pulse generator starts to flow under the influence of the previous clock pulse, control signals generated in all flow clock pulses also continue to flow in the pipes 23 and 25, so that in the flow. As will be described below, medium flip-flops receive small control currents on all fluid flip-flops at this point in time. By means of these control flows, the new control flow signals introduced via the pipeline 23 are diverted so that or 25. This control signal is dimensioned in such a way that the network receives signals again,
The direction of the newly introduced working flow In summary, the fluid is controlled and it is determined whether the working flow activates the flip-flops with each clock pulse, the flip-flop via the pipeline 27 or 29, whereupon they generate signals that leave the outlet. As soon as the working flow completely depends on the flow of the network. With each actuation ßen has begun, it is through the boundary layer flow the fluid flip-flops is held by this the fect in its path, even then, network for generating new output signals when the control signal is switched off. caused, which then serve to turn the flip-flops too

The control under the influence of a predetermined clock when this next time activated

pulse generated output signals of the amplifier.

are processed in the logical network and the delay elements 69 are intended to ensure

cause the creation of a new group of those under the influence of the first-time initiation

Output signals on lines 68. After those of the working streams generated by network 67

new signals of the network the delay elements 40 output signals even then to the flow

have passed through 69, they will be in contact with the control means flip-flops when the working flow

Flow inlet channels of the fluid flip genes are introduced for the second time. Is the own

Flops fed. The clock pulse that makes the working current delay of the logical network large enough

for the purpose of generating the new output. In order to meet this condition, the delays are

gnals of the network, occurs however 45 guiding elements 69 are not required.

1 sheet of drawings

Claims (4)

Patent claims: 1. Feed device consisting of a fluid clock pulse generator for several fluid flip-flops interconnected to form a logical unit, which the Working flows via a working flow inlet channel and control signals via control flow inlet channels can be supplied, characterized in that the control signals in the pauses between two working flow pulses of the fluid clock pulse generator (39,65,71) and can be entered in an overlapping manner with its use. 2. Feed device consisting of a fluid clock pulse generator according to claim !, characterized in that the control signals are generated by delay elements (69) out of phase in the lines with respect to the working flow pulses, of the same single-phase fluid clock pulse generator (71) can be derived. 3. Feed device consisting of a fluid clock pulse generator according to claim 1, characterized in that the phase-shifted control signals from the multiphase fluid clock pulse generator (39, 65) can be derived. 4. Feed device consisting of a fluid clock pulse generator according to claims 1 to 3, characterized in that the control signals are generated by line resistances and / or additional damping elements are damped in the lines.