DE1208410B - Method for manufacturing electrical semiconductor components with at least one tunnel junction, in particular tunnel diodes - Google Patents

Description

ΠUΛ OF THE REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. α .:

HOIl

German class: 21 g -11/02

Number: 1208 410

File number: J 23252 VIII c / 21 j

Filing date: February 26, 1963

Opened on: January 5, 1966

The invention relates to a method for producing electrical semiconductor components with at least one tunnel crossing, in particular tunnel diodes, and on the according to this method manufactured semiconductor components.

It is already known when producing electrical semiconductor components with a semiconductor body with several zones of opposite conductivity type, especially when manufacturing tunnel diodes, to remove the semiconductor material in such a way that the area of the pn junction is reduced. In this way one obtains semiconductor components with a particularly small capacity. This is particularly important with tunnel diodes, which should be used for higher frequencies.

By removing the semiconductor material in the * 5 In the vicinity of the pn junction, the cross section of the semiconductor part is reduced there so much that the arrangement becomes very sensitive to mechanical influences. In addition, the area of the pn junction cannot be reduced arbitrarily.

These disadvantages are avoided in the method according to the invention.

The method according to the invention is characterized in that a first zone doped via the degeneracy is generated in an intrinsically conductive semiconductor part, that on a portion of the surface of the semiconductor part where the transition area between the degenerately doped zone and the intrinsically conductive zone comes to the surface , and in the vicinity of this sub-region of the transition area doping material is introduced by alloying, so that a second, degenerate and oppositely doped zone is formed, and that the two degenerately doped zones are ^{partially removed to reduce the p +} n ⁺ transition area.

In this way, while maintaining a mechanically stable arrangement, it is possible to reduce the pn junction to be reduced to any size.

It is already known to place a highly doped plate on a high-resistance plate made of semiconductor material P-layer and an η-layer with graded doping to be arranged so that a tunnel diode characteristic and etch the graded doping layer. This arrangement should only be used for this serve to show how the characteristic changes when etching. After just a little bit of etching, the arrangement has no longer the characteristic of a tunnel diode.

In the method according to the invention, the characteristic curve remains essentially unchanged.

The invention will be explained in more detail with reference to the drawing, which shows an embodiment in Representing the shape of a tunnel diode.

Method of making electrical
Semiconductor components with at least one
Tunnel crossing, especially tunnel diodes

Applicant:

International Standard Electric Corporation,

New York, N.Y. (V. St. A.)

Representative:

Dipl.-Ing. H. Ciaessen, patent attorney,

Stuttgart 1, Rotebühlstr. 70

Named as inventor:

Carl Father Sandbank, London

Claimed priority:

Great Britain March 1, 1962 (8001)

In the F i g. 1, 2 and 3 are different process steps for the production of a tunnel diode according to the method according to the invention shown in section.

First, using the known method, a germanium disk serving as a base is doped with gallium until it degenerates, ie a zone with p ⁺ conductivity is created, preferably about 0.25 mm thick. A layer of intrinsic germanium, preferably also 0.25 mm thick, is then produced on the p + layer using the epitaxial method. The disc is then cut into narrow plates, one of which is shown in FIG. 1 is shown.

The plate according to FIG. 1, which is shown in cross section, consists of a single crystal 1 made of germanium with two zones, of which zone 2 is intrinsically conductive and the other zone 3 is doped with gallium to the point of degeneracy, so that a layer with p ⁺ -line results.

In the next process step, a platelet of doping material, which consists of an alloy of antimony and arsenic, is placed on one side of the platelet 1 in such a way that it lies in the middle of the boundary zone between zones 2 and 3. This plate is then alloyed into the semiconductor plate in such a way that a further degenerately doped zone with n ⁺ -conduction is created, which borders on the two zones 2 and 3. Then an ohmic contact is made on the

509 777/325

Alloy zone opposite side of the semiconductor chip alloyed.

The resulting structure is shown in FIG. 2 shown. The plate 4 made of doping material was alloyed into the semiconductor wafer 1 in such a way that the degenerate zone 5 with η ″ conduction has arisen. In this way, the pn junction 6 of a tunnel diode was formed between zones 3 and 5. Of the Ohmic contact 7 is attached on the side opposite this coating.

Finally, the structure according to FIG. 2 subjected to electrolytic etching. The resistances the degenerate doped zones 3 and 5 are both in the same order of magnitude, namely around many orders of magnitude lower than the resistance of die 4, intrinsic zone 2 and contact 7. The exposed parts of the zones 3 and 5 are therefore quickly removed, while the remaining semiconductor material is essentially not attacked. The etching process is continued until the tunnel junction 6 has been reduced to the required size.

The structure obtained in this process step is shown in FIG. 3 shown. The semiconductor die 1 contains a thin layer of zone 3 with p + -conduction, which is in small-area contact with zone 5 stands which n + line has and so the tunnel junction 6 forms. Both zones are supported by zone 2 made of intrinsically conductive semiconductor material.

In the exemplary embodiment described above, an intrinsic zone is produced on the p + zone by the epitaxial method, and a suitable doping material is then alloyed in to produce ^{the n + zone.} However, one can also start from an n ⁺ layer and generate the p + layer by alloying a suitable doping material. The zone doped for degeneracy can also be produced by epitaxial growth on an intrinsically conductive substrate. A single-crystal wafer with a degenerately doped zone and a subsequent intrinsic zone can also be produced by another known method without using the epitaxial method. In addition to germanium, other semiconductors, e.g. An Am-Bv compound such as gallium arsenide can be used. Instead of electrolytic etching, another etching can also be used. By partially covering the semiconductor plate, individual zones, such. B. the p ⁺ zone or the n ⁺ zone, are preferably etched off. The advantages of the invention are that a method for producing a semiconductor tunnel diode with low current, ie with a small pn junction, is specified in which the tunnel junction is mechanically held by the same crystal from which it was formed, the intrinsic zone xo does not affect the effect of the transition.

According to the method according to the invention, semiconductor components other than tunnel diodes can also be used are produced in which the pn junction is arranged on a substrate of semiconductor material.

Claims (3)

Patent claims: 1. A method for producing electrical semiconductor components with at least one tunnel junction, in particular tunnel diodes, characterized in that in an intrinsic semiconductor part a doped on the degeneracy first zone is generated that on a portion of the surface of the semiconductor part on which the transition area between the degenerately doped zone and the intrinsically conductive zone to the surface, and in the vicinity of this sub-area of the transition surface doping material is introduced by alloying, so that a second, degenerate and oppositely doped zone is formed, and that the two degenerately doped zones to reduce the p ⁺ n ⁺ transition surface are partially removed. 2. The method according to claim 1, characterized in that during the removal of the semiconductor part is partially protected against the removal.
3. The method according to claim 1 or 2, characterized in that the removal of the semiconductor material is carried out by electrochemical etching. Considered publications:
French Patent No. 1,281,763;
AEÜ, Vol. 15, 1961, issue 3, pp. 125 to 144;
SEL-Nachrichten, Vol. 9, 1961, Issue 1, pp. 47 to 49. 1 sheet of drawings 509 777/325 12.65 © Bundesdruckerei Berlin