DE1203317B - Process for converting a static binary counter consisting of main and auxiliary memory for each counter level into a static decimal counter - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. α .:

H03k

German class: 21 al - 36/22

Number: 1203 317

File number: L 43579 VIII a / 21 al

Filing date: November 28, 1962

Opening day: October 21, 1965

Static binary counters have already been proposed which consist of a main memory outputting the counting result and an associated auxiliary memory for each counting stage and are controlled by counting signals (J ₁ ) and auxiliary counting signals (t ₂ ) that are offset in time.

These meters are largely insensitive to interference; they do not need any specially shaped ones Control signals. The memories forming the counting stages are coupled galvanically. The memory set or delete when the amplitude of the triggering signals exceeds a certain value.

The F i g. 1 shows a possible embodiment for the first four counting stages of one designed in this way Binary counter, the number of stages of which can be expanded as required.

The binary counter according to FIG. 1 consists of the main memories Sa ₀ to SU ₃ , which have the same structure as one another. The main memories are assigned auxiliary memories Sh ₀ to Sh ₃ , which are also identical to one another. Main and auxiliary memories Sa ₀ and Sh ₀ form the counting stage with the value 2 °. Main and auxiliary memories S ^ ₁ and Sm represent the counting level with the value 2 ¹ , etc.

The main memories Sa each consist of three AND levels & _2? to & ₂₈ , & ₃₆ to & ₃₈ , & _4e to & ₄₈ , & _M to & ₅₈ . These AND stages each control an or-not stage V ₃₀ , V ₄₀ , V ₅₀ , V ₆₀ , each of which is followed by a non-stage 31, 41, 51, 61. The non-stages give the method representing the counting result for converting one per counting call
consisting of main and auxiliary storage
static binary counter into a static
Decimal counter

Applicant:

Licentia Patent-Verwaltungs-G. m. b. H.,

Frankfurt / M., Theodor-Stern-Kai 1

Named as inventor:
Dipl.-Phys. Dieter Petzold, Berlin

Signals A ₀ to A ₃ , the or-not stages corresponding to the negated signals A ₀ to A ₃ , the z. B. can be used for a countdown.

The auxiliary memory of the binary counter according to FIG. 1 each consist of two AND levels & ₂₂ / &23> 8C ₃₂ ISc ₃₃ , & 42 / &43>& 52 / & 53 · These groups of AND levels each control an or-not level V ₂₄ , V ₃₄ , V ₄₄ , V ₅₄ , each of which is followed by a non-level 25, 35, 45, 55. The auxiliary signals H ₀ to H ₃ ' are generated at the nipht stages, and the corresponding negated signals H ₀ to Ti ₃ are generated at the or-not stages.

The main memories Sa ₀ to Sa ₃ have the following logic switching functions:

(^ ₁ & Z ₂ & H ₀ ) V (A ₀ & H ₀ & /) V (A ₀ & I ₁ ') = A ₀ (I ₁ & H ₀ & H ₁ ) V (A ₁ & H ₁ & T) V (A ₁ & J ₁ ) = A ₁ (I ₁ & H ₁ & F ₂ ) V (A ₂ & H ₂ ScT) V (A ₂ 8CT ₁ ') = A ₂ (i _x & H _2. & F ₃ ) V (A ₃ & H ₃ & T) V (Zt ₃ AT ₁ ') = Λ

The auxiliary memories Sh ₀ to Sh ₃ have the logical switching functions:

(t _t 8c A ₀ ) V (H ₀ See) = H ₀ (t ₂ & A ₁ ) V (H ₁ 8c H ₀ ) = H ₁ (t ₂ & AJ V (H ₂ & H ₁ ) = H ₂ (t _% & A ₃ ) V (H ₃ 8CHJ = H ₃

(2)

The signal ti introduced in this exemplary embodiment is a combination of the negated count signal t _x and the negated clear signal /. The circuit for forming the signal Z ₁ 'according to FIG. 2 consists of an and-not stage & ₇₀ , which controls a reinforcing non-stage 71. The signal e has been introduced so that the structure of the auxiliary memory Sho corresponds to the auxiliary memory of the following counting stages. The circuit for forming the signal e according to FIG. 3 consists of two AND stages & ₇₂ , & ₇₃ , which control an or-not stage V ₇₄ . _

When a reset signal I = L (i.e. / = 0) occurs, all outputs A = 0 and all outputs H = O.

509 718/407

3 4

The signal z ₂ driving the counter is a free signal. The invention accordingly relates to an allocation signal for counting. The signals t _x are only counted to convert a static binary counter when z is ₂ - L. Appropriately, the signal z ₂ of each counting stage from a main and auxiliary memory from a counting command signal z, which exists at any time and can occur through counting signals and auxiliary counting signals, synchronized so that it is controlled in any form, in a static state only with the beginning of a counting auxiliary decimal counter. The invention consists in that each signal can change t _2. Decade consists of four binary counting levels and in each

The F i g. 4 shows a circuit made up of two memories decade a signal from the fourth counting stage to the one for forming the counting enable signal z ₂ . The one second counting stage and a signal from the fourth number memory consists of input and stages A ₁ to & ₃ , io stage is fed back to the third counting stage or the one or-not stage V ₄ with downstream that a signal of the fourth counting stage to the second non-stage 5. The other memory consists of the counting stage and a signal of the first from the input AND stages & ₆ to & _g , which is a counting stage led to the fourth counting stage. Control an or-not level V ₉ , which will replace a non-level 10 further training that is connected to the downstream. 15 Decimal conversion signals require the binary

The F i g. 5 shows a counter previously driving signals or are with a previously signal diagram for 23 counting steps, namely the signals driving the binary counter in separate Fig. 5a for upward counting, FIG. The designations of the signals output signals replace the previously actuating signals have already been explained. In order to keep the structure of the binary counting stages visible, only the affirmative signals remain unchanged. The auxiliary memories are expediently reproduced (for example, not also T ₁ for I ₁ ), with a further signal for the second and third counting stages being drawn as rectangles for the sake of simplicity. The fed from the fourth counting stage. Another signal can have the values 0 or L. The design is corresponding to the auxiliary memories of the zero lines are assigned to the value 0, the second and third counting stages above each one logical input line is assigned to the value L. level added, which is for the / + 1st decade (val-

The counter described so far represents a not speed 100 has the following logic switching function:

pre-settable binary counter whose effect (A * ■ & t)

already described in detail elsewhere ^ ^{3 2} ' '

has been. 3 ° where A and t _{2 are} the driving signals and the

The F i g. 6 shows a binary counter which is based on a lower index of the signal A, the weight and the

any binary number can be preset. The preset upper index denotes the different decades,

Bare binary counter has, compared to the non-presetting, the control of the auxiliary memory is expedient

binary counter according to FIG. 1 additional and the second and third counting stage compared to one

Levels & 29, & 39, & 49, & ₅₉ . These AND levels are changed 35 binary counters by adding one of the previously different

is replaced by a presetting signal k ₀ , Ic ₁ , Ar ₂ , k ₃ and common control signals of each counting stage

economically through the presetting release signal / to the output signal of a separate logic

controlled. The output of the AND stages & ₂₉ , & ₃₉ , circuit in which the signal that was previously activated with

&49>& 59 is combined ^at or-not stages V ₃₀₀ , V _4oa , V _5oa , a signal of the fourth counting stage

Veoa (J ^ev i ^er inputs), which is at position 40. According to further training, the

of the or-not stages V ₃₀ , V ₄₀ , V ₅₀ , V ₆₀ (three separate logic circuits each for the second counting stage

Inputs) of the binary counter, which cannot be preset, has the function

are kicking. . ... .

The preset enable signal / becomes L after a ^ ¹ ^ A ₃ ) - q _x or A ₁ & A ₃ - q _x

Delete command signal / = L and disappears (/ = 0) 45 _{and for the third counter stage} the function
with the beginning of the number release signal z ₂ = L. In

Presetting signals (Aj V Aj) = q ₂ ⁱ or Äj & AJ = q ₂ ^{ ,

are taken over by the counting levels. While _

a count is already preset to a new preset - where A, A are the triggering signals and q is that

preparable. 5 ° is the output signal and the lower index is the value

The F i g. 7a, 7b show circuits for forming and the upper index the different decades

of the signal /. The arrangement according to FIG. 7a.

consists of the memory Sf with the AND level & ₇₅ , a further training is corresponding to the

the or-not stage V ₇₆ and the non-stage 77 main memory of the second counter stage a signal from

as well as the or-not stage V ₇₈ . The arrangement according to 55 of the fourth counting stage and the auxiliary memory of the fourth

7b consists of the memory Sf with the counting stage a signal from the first counting stage

AND-stages & ₈₀ , & ₈₁ , the or-not-stage V ₈₂ and leads. In the i 4-1. Decade

of the non-stage 83 and the and-not stage & ₈₄ speed 10 »") to the input stage of the main memory of the

and the non-level 85.. second counting stage additionally a signal from the auxiliary

The mode of operation of the presetting is already carried out on 60 memories of the fourth counting stage, as well as in one

has been described in detail elsewhere. Input stage of the auxiliary memory of the fourth counting stage

The present invention has for its object a signal of the auxiliary memory of the preceding

set, non-presettable or, presettable counter level by the signal HJ of the auxiliary memory of the

Binary counters with main and auxiliary memories for each counting first counting stage replaced, with H, H being the triggering ones

level with little effort and if possible below 65 signals and the lower index the value and

Retention of the individual assemblies in a not the upper index, the various decades

pre-settable or pre-settable static de- signs. A further training is appropriate

to convert to numeric counter. one of the main memory of the second counting

Stage controlling signals replaced by the output signal a separate logic circuit in which the previously driving signal with a signal of the fourth counting stage is summarized and the auxiliary memory of the fourth counting stage previously driving Signal is replaced by a signal from the first counting stage. The separate logic circuit for the second counting stage the function

H ₀ * & Hj = p ₀ * or

H ₀ * V

= _Po \

where H, H are the driving signals and ρ is the output signal and the lower index denotes the significance and the upper index denotes the various decades.

The invention is illustrated with further advantageous developments on the basis of exemplary embodiments explained in more detail below.

Since each counting level can assume two states (O or L), at least four counting levels per decade are required for the decimal counter. Of the sixteen possible combinations that four counting levels can output, only ten are used. So six counting positions have to be skipped. The choice of which output combinations should not occur is made so that the switching functions for the decimal counter are as simple as possible. In this respect, a counter that outputs the counting result as a decimal number in binary code has proven to be particularly advantageous. FIG. 8a shows a signal diagram for such a decimal counter which, for example, according to FIG. 9 can be formed. The meaning of the signals I ₁ , t ₂ , I and z ₂ has already been explained. The signals output by the main memories Sa of the counting stages are in turn denoted by A, while those of the auxiliary memory Sh are denoted by H. In the case of signals A and H , the upper index relates to the decade (value 10 °, 10 ¹ , ...), the lower one to the respective level within the decade (value 2 °, 2 \ ...). The signal A ₃ ⁰ thus has z. B. the valency 2 ³ · 10 ° = 8. The main and auxiliary memories of the respective stage within the decade are designated accordingly. The description of the decimal counter according to FIG. 9 takes place below. As can be seen, the signals A vote ₀ ⁰ to A ₃ ⁰ of the first four stages according to the signal diagram of Fig. 8 a to by the vertical line W ₁ marked location with the signals A ₀ to A ₃ of the binary counter according to the signal diagram of the Fig. 5 a corresponds. As the signal diagram according to FIG. 8a shows, in contrast to the binary counter with the decimal counter

ίο however in the following step (start with counting signal c ₁₀ ) the ^ "output remains 0 (the / 4 _r output of the binary counter becomes L at this point), the ^ ₃ ° output changes from / to 0 (the ^ ₃ Output of the binary counter remains beyond the relevant position L) and the signal A ₀ ¹ = L occurs (the ^ 4 ₄ output of the binary counter still remains 0). The four counting levels of the decimal counter for the first decade then start again from 0, 1, 2, ... to count until the next crazy diagram marked by the vertical line H ₂

ao point is reached, where again a cycle is completed. One cycle comprises ten counting positions. The same applies to the counting levels assigned to the following decades.
The signal diagram according to FIG. 8a shows the signals A ₀ ⁰ to A ₃ ⁰ and A ₀ ¹ to A ₃ ¹ as well as H ₀ ⁰ to H ₃ ⁰ and H ₀ ¹ to TZ ₃ ¹ up to and from the counting stages of the first two decades 23. Counting step, taking into account that the counting process is interrupted twice (z ₂ = 0).

8b shows the output signals B ₀ ⁰ to JS ₀ ^{1 of} a converter described elsewhere, which is connected downstream of the decimal counters for counting down.
The way in which the switching functions of the binary counter according to the invention are to be changed for decimal counting is shown, for example, on the binary counter of FIG. 1 explained.

First of all, the switching functions of the first four counting levels of this binary counter are once again unchanged, but in the same notation used for the decimal counter (with the upper index for the decade), specified [cf. Functions (1) and (2)]:

Ci ₁ & Z ₂ & H ₀ ") VU ₀ O & H ₀ ⁰ 8c I) V (A ₀ ⁰ Sc I ₁ ') = A ₀ ⁰ (f _x & TZ ₀ ⁰ & F ₁ ⁰ ) V (A ₁ ⁰ & F ₁ ⁰ & T) V (A ₁ ⁰ Sc T ₁ ) = ^ ₁ ⁰ (I ₁ & H ₁ ⁰ & F ₂ ⁰ ) V (A ₂ ⁰ & F ₂ ⁰ & T) V (A ₂ ⁰ & T ₁ ') = A ₂ ⁰ (I ₁ & H ₂ ⁰ & F ₃ ⁰ ) V (A ₃ ⁰ 8c F ₂ ⁰ & 7) V (A ₃ ⁰ & 7 /) = / I ₃ ⁰

(t ₂ & Λ ⁰ ) V (H ₀ ⁰ & e) = H ₀ o (t ₂ & Λ ⁰ ) V (H ₁ ⁰ 8c H ₀ ⁰ ) = H ₁ ⁰ (Z ₂ & ^ ₂ ⁰ ) V ( H ₂ ⁰ & H ₁ ⁰ ) = H ₂ ⁰ (i ₂ & A ₃ ⁰ ) V (H ₃ ⁰ & H ₂ ⁰ ) = H ₃ ⁰

(7)

(8th)

(9)

(10)

As can be seen from the signal diagrams according to FIGS. 5a and 8a, the signals of the first counting stage of the binary and decimal counter, that is ^ i ₀ ⁰ with A ₀ and H ₀ ⁰ with H _0, match. The first counting level of the binary counter can therefore be adopted unchanged for the decimal counter.

So that, as required for the decimal counter, A ₁ ⁰ cannot become L _{at position W 1} (signal diagram Fig. 8a), the first bracket of the switching function for ^ ₁ ⁰ (4) is influenced accordingly. A) a suitable blocking signal can be added to the mentioned element of the response condition or b) the signal H ₁ ⁰ = L _{can be made for the duration of the ij signal (c 10} ), as indicated, for example, by the dashed block b ₃ in FIG F i g. 8 a is indicated.

7 8

In case a), A ₂ ⁰ (15) remains to be influenced at the point marked W _1. This can be done by generating the

Zf ₁ O == 0 (in this case the dashed block b- occurs. (The case, a blocking signal to the

block b ₃ drawn), so A ₂ ⁰ can also add switching function for A ₂ ⁰ (5), should not be here

and thus H ₂ ⁰ does not become L either. A ₃ ⁰ is already to be considered L , since this possibility is better - like

and should become 0 at the jump point; this is done on 5 already described - at counting level A ₁ ⁰

simplest through the block b ₅ (ie, it can be used for.) Because of the block b _t occurs - without

Duration of the ^ _{signal [c 10} ] the signal H ₃ ⁰ - L and change of the switching function for H ₃ ⁰ (10) - the

_{so that the block A 5} in the first and second brackets, and thus A ₃ ^{0 is} deleted at W _1.

Switching function for A ₃ ⁰ occurring H ₃ ⁰ = 0). Since in order that the blocks b ₃ and b ₄ arise, both

Case a) the dashed block b _t ^{does not match} the switching function for H ₁ 0 (8) like that for H ₂ ⁰ (9)

occurs, is to generate the block b ₅ , in which the link as an additional setting condition
Switching function for H ₃ ⁰ (10) in the second bracket H ₂ "

replaced by H ₀ ⁰ , it is then V (A ₃ ⁰ & A ₀ ⁰ & t ₂ ) (13)

. _{15 added since} H ₃ o through U ₂ ScA ₃ ⁰ ) independently

The resulting block b ₅ can be set as the one mentioned by H ₁ ⁰ and H ₂ ⁰ , if the specified blocking condition for the occurrence of VOn ^ ₁ ^{0 can take} effect, ie, an additional element can be added
the switching function for A ₁ ⁰ (4) must be changed so,.,

that A ₁ ^{0 is} not. L can become when # 3 ° = L. ^v ^ ^{& A} °> W

Simplify from the first bracket of the response condition for ao.
^ i ₁ ⁰ (4) is thus The switching functions for the counting levels of the following

(t Sr vr Sr i / o Sr TT o \ the decade with the value 10 ¹ - initially without

U ₁ cc H ₀ cc JH ₁ cc Ha) -,. »,,. , ..., ",.,

the necessary changes - result from

In case b) the block b _{3 is} generated. The functions (3) to (10) must then be prevented by everywhere the upper one, that at the point W ₁ the signal 25 index 0 through 1 and also in (3) z ₂ through H ₃ ⁰ , A ₂ ⁰ - L will. For this purpose, the response condition for and in (7) e is replaced by H _z ° . It is then

U ₁ & H ₃ o Sc H ₀ ¹ ) V (A ₀ ¹ Sc H ₀ ¹ & T) V (A ₀ ¹ & F ₁ ') = A ₀ ¹ (15)

U ₁ Sc H ₀ ¹ Sc H ₁ ¹ ) V (Λ ¹ & H ₁ ¹ & T) V (A ₁ ¹ & ii ¹ ) = A ₁ ¹ (16>

(<i & H ₁ ¹ & H ₂ ¹ ) V (A ₂ ¹ & F ₂ ¹ & 75 V (A ₂ ¹ & T ₁ ') = A ₂ ¹ (17)

(i, & H ₂ ¹ & F ₃ ¹ ) V (A ₃ ¹ & F ₃ ¹ & T) V (A ₃ ¹ & F ₁ ') = A ₃ ¹ (18)

(r, & A ¹ ) V (/ V &# 3 °) = Ή. ¹ (19 ^

(/, & A ₁ ¹ ) V (H ₁ ¹ & H ₀ ¹ ) = H ₁ ¹ (20)

U ₂ ScA ₂ ¹ ) V (H ₂ ¹ ScH ₁ ¹ ) = H ^ (21)

U ₂ & A ¹ ) V (^ ₃ ¹ & H ₂ ¹ ) = ^ ₃ ¹ (22)

After the counting steps of this second decade 45, the switching functions for (valency 10 ¹ ) a cycle of ten counting positions result in the following decades (valency 10 ² , 10 ³ etc.). The circuit complexity of a decimal from 99 to 100, these steps should start again from the beginning Counter is greater for solution b) than for solution a). start counting (starting with 0). An analogous one. In case b), the number of inputs of the additional consideration as for the counting stages of the first decade 50 elements in each decade increases by two; z. B. come (valence 10 °) teaches that the solution case a) corresponds to the additional element for H ₁ ² and H ₁ ^{3 of} the third, the first bracket of the function (16) for A ₁ ¹ in the decade the inputs A ₀ ² and A ₃ ^Z added. The solution b),

which is characterized in that the in Fig. 8a

U ₁ ic H ₀ ¹ & .H ₁ ¹ & ^ T ₃ ¹ ), (23) blocks designated _{with Z) 3} , b _t , b ₈ , b _{9 can occur}

55 to a solution c) can be simplified by z. B.

the second bracket of the function (22) for H ₃ ¹ in instead of the above-mentioned terms (25), (26) to the

Switching functions for HJ and Hf the additional link (H ₃ ¹ & H ₃ O) (24)

is to be changed or the solution case b) corresponding to 60 ³ '', j *

the switching functions (20) and (21) for H ₁ ¹ and H ₂ ^{1 K} '

the link is added as an additional setting condition. In solution c) still occur

in Fig. 8 a also dotted blocks b _e ,

V Uz Sc A ₀ ⁰ & A ₃ ⁰ & A ₀ ¹ & ^ ₃ ¹ ) (25) b _ls b ₁₀ , b _n on, but not counting

or 65 disturb. For a better overview, the switching functions

\ ZfffoßrjosrjiSrji- \ ολλ oncR for the two decades of a decimal counter that

V \ S1 ₃ OC A ₀ CC A ₀ CC A ₃ j l- ^ OI it. 11 1 τ-. · Λ ι ■ ^

from the binary counter according to FIG. 1 emerged, is to be added. compiled according to solutions a) and c).

9 10

Solution a)

U ₁ & z ₂ & F ₀ ⁰ ) V OV & H ₀ ⁰ Sc 7) V OV & T ₁ ') = ^ ₀ ⁰ (28)

(Z ₁ &# o ° &# ι ° &#s ⁰ ) V OV Sc F ₁ ⁰ & Γ) V OV ScJ ₁ ') = A ₁ ⁰ (29)

U ₁ & / ίι ^ο & F ₂ ⁰ ) V OV & F ₂ ⁰ & 7) V OV & T ₁ ) = Λ, ° (30)

Cr ₁ & iJ ₂ "& F ₃ ⁰ ) V (V & F ₃ ⁰ & T) V OV & V) = V> (3D

(Z ₁ & H ₃ ⁰ Sc H ₀ ¹ ) V (A ₀ ¹ Sc F ₀ ¹ & 7) V (Λ ¹ & V) = V (32)

(A & i / o ¹ &# 1 * & ^ a ¹ ) V (A ₁ ¹ Sc H ₁ ¹ & 7) V (A ₁ ¹ Sc T ₁ ') = A ₁ ¹ (33)

Cr ₁ & H ₁ ¹ & F ₂ n V OV & F ₂ ¹ & 7) V OV & V) = A ₂ ¹ (34)

(I ₁ ScH ₂ ¹ ScW ₃ ¹ ) V (A ₃ ¹ SlH ₃ ¹ ScT) V (A ₃ ¹ SlV) = A ₃ ¹ (35)

(r ₂ & ^ ₀ ⁰ ) V (H ₀ ⁰ See) = Zi ₀ ⁰ (36)

U ₂ Sc A ₁ ⁰ ) V (Zi ₁ ⁰ & Zi ₀ ⁰ ) = H ₁ ⁰ (37)

(T ₁ & Λ ⁰ ) V (ZZ ₂ ⁰ & Ti ₁ ⁰ ) = / Z ₂ ⁰ (38)

U ₂ V) V (Zi ₃ ⁰ & _7/0 °) = BR ⁰ ₃ (39)

(t ₂ & ^ ₀ ¹ ) V (ZZ ₀ ¹ & / Z ₃ ⁰ ) = / Z ₀ ¹ (40)

U ₂ & V) V (A ₁ ¹ &#"*). = H ₁ ¹ (41)

U ₂ & / J ₂ ¹ ) V (Ti ₂ ¹ & Zf ₁ ¹ ) = / Z ₂ ¹ (42)

(t, Sc A ₃ ¹ ) V (ZT ₃ ¹ & Ti ₀ ¹ ) = Zi ₃ ¹ (43)

Solution c)

(I ₁ ScZ ₂ SlH ₀ O) V (A ₀ ⁰ SCH ₀ ⁰ ScT) V (A ₀ ⁰ ScV) = A ₀ ⁰ (44)

Cr ₁ & H ₀ ⁰ Sc F ₁ ⁰ ) V OV &# ΐ ^ο & 7) V OV & T ₁ ') = ^ ₁ ⁰ (45)

(ti ScH ₁ ⁰ Sc F ₂ ⁰ ) V OV &# 2 ° & 7) V (^ ₁ O & T ₁ ') = ^ ₂ ⁰ (46)

(I ₁ Sc H ₂ ⁰ Sc H ₃ ⁰ ) V (A ₃ ⁰ Sc H ₃ ⁰ ScT) V (A ₃ ⁰ Sc T ₁ ') = Λ ⁰ (47)

(I ₁ Sc H ₃ ⁰ Sc H ₀ ¹ ) V (A ₀ ¹ Sc H ₀ ¹ ScT) V (A ₀ ¹ Sc T ₁ ') = A ₀ ¹ (48)

(h Sc H ₀ ¹ ScH ₁ ¹ ) V (A ₁ ¹ Sc H ₁ ¹ ScT) V (A ₁ ¹ ScT ₁ ') = ^ ₁ ¹ (49)

Ci ₁ & ZZ ₁ ¹ & F ₂ ¹ ) V (A ₂ ¹ Sc F ₂ ¹ & T) V (A ₂ ¹ Sc T ₁ ') = Λ ¹ (50)

(I ₁ Sc ZZ ₂ ¹ & F ₃ ¹ ) V OV & F ₃ ¹ & 7) V (A ₃ ¹ Sc T ₁ ') = A ₃ ¹ (51)

U ₂ Sc V) V (H ₀ ⁰ See) = H ₀ ⁰ (52)

U ₂ Sc A ₁ ⁰ ) V (H ₁ ⁰ Sc H ₀ ⁰ ) VM ₃ ⁰ & t ₂ ) = H ₁ ⁰ (53)

(r, & V) V (H ₂ ⁰ ^ Sc H ₁ ⁰ ) V (V & t ₂ ) = H ₂ ⁰ (54)

U ₂ Sc A ₃ ⁰ ) V (H ₃ ⁰ Sc H ₂ ⁰ ) = H ₃ ⁰ (55)

U ₂ Sc A ₁ ⁰ ) V (H ₀ ¹ Sl H ₃ ⁰ ) = H ₀ ¹ (56)

U ₂ Sc A ₁ ¹ ) V (H ₁ ¹ Sc H ₀ ¹ ) V (A ₃ ¹ Sct ₂ ) = / Z ₁ ¹ (57Ϊ

(t ₂ Sc A ₂ ¹ ) V (H ₂ ¹ Sc H ₁ ¹ ) V (A ₃ ¹ Sc t ₂ ) = ZZ ₂ ¹ (58)

(t ₂ Sc A ₃ ¹ ) V (H ₃ ¹ Sc H ₂ ¹ ) = H ₃ ¹ (59)

The switching functions for the i + 1st decade with S ¹ ^ ₂ according to FIG. 9 compared to the corresponding of the valency 10 * go from the switching functions for auxiliary memories SjJ ₁ , 5Ή ₂ of FIG. 1 a further the second decade (value 10 ¹ ) is produced by adding input stage & ₉₀ , Sc ₉₁ . Both additional levels are everywhere the upper index 1 is replaced by /. 55 by the auxiliary counting signal t ₂ and the output signal A ₃ ⁰

F i g. 9 shows e.g. B. the first decade of one of the main memory S ^ _{3 is not} controlled. The level & _{90 of the} pre-settable decimal counter after the functions, like the levels & ₃₂ , & _33, controls the or-not (44) to (47) and (52) to (55), those of the solution c) ent- level V ₃₄₀ , level & ₉₁ as well as levels & ₄₂ , speak. The counter is from the binary counter after. & _{43 adopts} the or-not level V ₄₄₀ . The stages V ₃₄₀ , the F i g. 1 emerged. Correspondingly, the 60 V _{440 have elements with the same V 34} , V ₄₄ of FIG. 4 that have been adopted unchanged compared to the corresponding stages. 1 one more entrance. As shown in the reference numbers. borrowed, the conversion effort is very low.

As can be seen, the main _{memories match 5 ^ 0} Both those counting stages of a decimal counter

to Sj ₃ and the auxiliary memories 5 ^ 0 and 5 ^ ₃ according to the solution a) as those according to solution c), F i g. 9 with the corresponding memories of the binary 65 which compared to the counting stages of the binary counter expands counter according to FIG. 1 are in the structure and in the activation can be modified so that they coincide with the control. To convert the binary counter, the remaining stages and a part corresponding to FIG. 1 only have the auxiliary memory Sj ^ ₁ , an additional part.

11 12

In case a) becomes ζ. B. from the switching functions (29) and (33)

U ₁ & P ₁ " & F ₁ ⁰ ) V (A ₁ ⁰ & H ₁ ⁰ & T) V OV & T ₁ ') = A ₁ ⁰ (60)

U ₁ & P ₁ ¹ & tfi ¹ ) V (A ₁ ¹ & F ₁ ¹ ScT) W (A ₁ ¹ & T ₁ ') = A ₁ ¹ (61)

with (Zf ₀ ⁰ & H ₃ ⁰ ) = P ₀ ⁰ (62) or H ₀ ⁰ V H ₃ ⁰ = P ₀ ⁰ (64)

and (tfo ¹ & A ₃ I) = P _o i (63) or Zi ₀ ¹ V H ₃ ¹ = P ₀ ¹ (65)

in case c) z. B. from the switching functions (53), (54), (57) and (58)

Ut & ft ⁰ ) V (Ζ // & // "») = H ₁ ⁰ (66)

(i ₂ & q ₂ ⁰ ) V (H ₂ o & Zf ₁ ") = H ₂ ⁰ (67)

(ig & ^ ₁ ¹ ) V (Zf ₁ ¹ & Zf ₀ ¹ ) = Zf ₁ ¹ (68)

(t ₂ & qj) V (H ₂ ¹ & Zf ₁ ¹ ) = H ₂ ¹ (69)

with (., A. a ⁰ ) - and (, A. 3 °) = and (. A. 3 ¹ ) = VV W. VV

(70) or A ₁ ⁰ & / i ₃ ⁰ = q ₁ (74)

(71) or A ₂ ⁰ & Λ ₃ ° =? ₂ ^P (75)

(72) or A ₁ ¹ & A ₃ ¹ = ^ ₁ ¹ (76)

and (A ₂ ¹ V A ₃ ¹ ) = ^ r ₂ ¹ (73) or ^ ₂ ¹ & ^ ₃ ¹ = ^ ₂ ¹ (77)

The F i g. 10 shows, for example, the first decade where the switching functions for AJ around the element V.

of a non-presettable decimal counter after the 30 (/ & k /) have been extended, kj is a preset

Functions (44) to (47), (52), (66), (67), (55), the position with the value 2 "· 10 *.

Solution c) and in which all counting levels The counter according to Fig. 13 agrees with the previous

have the same structure. adjustable binary counter according to FIG. 6 match - EI-

The elements that correspond to those of the counter with the same structure and control

F i g. 1 match have the same reference numerals. 35 have the same reference numerals -, only that to the

Compared to the counter of FIG. 9, stages & ₉₀ , place of elements & ₅₃ and & _38, are stages & _53a and

& 8J has ceased to exist and the & _{38O has been activated} . The AND stage & _{53 of} the auxiliary

Input _{stages & 32 (t of} the auxiliary memory S ^ ₁ and & _42tt memory S% ₃ is used instead of the output signal of the

of the auxiliary memory S ¹ ^ ₂ changed to the "place of the auxiliary memory of the previous stage of the

corresponding levels & ₃₂ , & ₄₂ of FIG. 1 entered 40 output signal of the auxiliary memory S £ "of the first

are. The control is controlled by the output signal A counting stage of the decade. The AND stage & ₃₈ "

of the assigned main memory is different from that of the main memory S ^ ₁ compared to the corresponding

Signals ^ ₁ ⁰ (stage & _32a ) and q ₂ ⁰ (stage & _42a ) replaced. The corresponding AND stage & ₃₈ according to FIG. 6 another

11 shows a circuit design for the input which is connected to the output of the or-not stage V _51. Forming the 45 of the auxiliary memory S ^ _{n of} the fourth counting stage of the decade ^ signals [cf. Functions (74) to (77)]. This is connected. The effort for the conversion order consists of two and-not stages A ₁₀₀ and development according to solution a) is extremely low. & ₁₀₁ represented by the signals A ₁ ¹ and A ₃ ¹ and A ₂ ¹ and FIG. B. the solution a) can be controlled according to A ₃ ^i. At the output of stage & ₁₀₀ the first decade of a presettable decimal counter occurs the signal q ^ and at the output of stage & ₁₀₁ 50 after the functions (28), (60), (30), (35), where the signal qj occurs . Switching functions for A ⁱ around the element V (/ & k ⁴ )

When converting the decimal counter after which have been expanded and all main memories and auxiliary s

F i g. 9 and 10 from the non-presettable binary memory of the counting levels have the same structure,

counter according to FIG. 1 is from solution c) Use The elements of the counter according to FIG. 14 agree

been made. 55 the corresponding elements of the counter according to FIG.

In the following, the conversion into a deci- 13 (same reference number) in structure and in the color counter according to solution a) using a pre-control is the same, with the exception of the AND stage & _3Sft adjustable binary counter according to FIG. 6 explained. (three inputs) of the main memory S '^ _l5 which the

Fig. 12 shows a signal diagram of a pre-AND stage & _38a replaced; are_ two adjustable decimal counters. The meaning of the 60 control signals of stage & _38Π (the signals H ₃ ⁰ and H ₀ ⁰ ) signals has already been explained. The output signal P ₁ ^{0 of} this circuit to a block, which is combined in a separate circuit and signals H ₁ ⁰ , H ₂ ⁰ , H ₁ ¹ and H ₂ ¹ , only occur with a decimal counter according to the input of stage & ₃₈₆ ,
solution c) described above, but not in the case of a Die F i g. 15 a and 15 b show circuit execution decimal counters according to solution a). 65 genes for forming the in a counter according to FIG. 14

Fig. 13 shows e.g. B. the solution a) correspondingly occurring P signals [cf. Functions (61) to (65)].

the first decade of a presettable decimal counter. The arrangement according to FIG. 15 a consists of one

according to functions (28) to (31) and (36) to (39), and-not-level & ₁₀₂ , which is a non-level 103 after-

is switched, at the output of which the signal P ₁ * occurs. Stage & ₁₀₂ is controlled by signals H ₀ ' and H ₃ ¹ . The arrangement according to FIG. 15b for generating P ₁ ^ jSt an or-not stage V ₁₀₄ , which is controlled by the signals H ₀ ' and H ₃ ^1.

In the above examples, two auxiliary memories of a binary counter are used for decimal conversion according to solution c) modified according to solution a) a main and an auxiliary memory of a binary counter.

The following describes an example of the decimal conversion in which two main memories of a binary counter.

16 shows the first four counting stages of a binary counter without presetting, consisting of the main _{memories SU 0} to Sa ₃ and the auxiliary memories Sh ₀ to Sh ₃ (the counting release is not taken into account here). The switching functions for this binary counter are given below:

(J ₁ & H ₀ & /) W [A ₀ 8c I & Z ₁ ) V (X ₀ & / & H ₀ ) = A ₀ (78)

U ₁ & H ₁ & H ₀ ) V (A ₁ & T 8c T ₁ ) V (A ₁ & 7 & H ₁ ) V (X ₁ & 7 & H ₀ ) = A ₁ (79)

(I ₁ & F ₂ & H _x & J ₁ ) V (A ₂ & T 8c F ₁ ) V (A ₂ & 7 & H ₂ ) V (A ₂ & T 8c H ₁ ) V (A ₂ & A ₁ ) = A ₂ (80)

U ₁ & F ₃ & / Z ₂ & J ₂ ) V (A ₃ & T 8c T ₁ ) V (X ₃ & T 8c H ₃ ) V (X ₃ & T 8c W ₂ ) V (X ₃ & A ₂ ) = X ₃ (81)

U ₂ & A ₀ ) V (// "& T 8c T ₂ ) V (/ Z ₀ & A ₀ ) = / Z ₀ (82)

(iss & X ₁ ) V (#! & T 8c 7 ₂ ) V (#, & X ₁ ) = H ₁ (83)

(i ₂ & X ₂ ) V (H ₂ & T 8c T ₂ ) V (H ₂ & X ₂ ) = H ₂ (84)

(Z ₂ & X ₃ ) V (H ₃ & T & T ₂ ) V (ff, & X ₃ ) = H ₃ (85)

In FIG. Figure 17a shows a signal diagram for this binary counter. As can be seen, in this example, while the X output of a main memory is L , the associated auxiliary memory changes its state only once. According to the invention, for conversion to a decimal counter zu_der setting condition of X ₁ (79), a blocking signal H _{3 is} fed back from the fourth counting stage and, in the case of holding conditions for X ₃ (81), signals A ₂ , H _{2 are given} by signals X ₀ , H ₀ from the first counting stage replaced. It is accordingly in the binary counter according to FIG. W the AND stage & _{166 is} additionally controlled by the signal H ₃ and in the AND stage & ₁₈₉ the signal H _{2 is} replaced by the signal H ₀ and in the AND stage & _18S the signal X _{2 is} replaced by the signal X ₀ . The switching functions for the main memories of the first two decades of a decimal counter formed in this way are listed below. Upper indices are again introduced to denote the decades.

(Z ₁ & H _o ^a 8c I) V (X ₀ "& / & I ₁ ) V (X ₀ "& / & H ₀ ⁰ ) = A _o o (86)

(Z ₁ & W ₁ ⁰ & Zi ₀ ⁰ & H ₃ O). V (X ₁ ⁰ & T 8c T ₁ ) V (X ₁ ⁰ & T8c H ₁ ⁰ ) V (X ₁ ⁰ & Γ & F ₀ ⁰ ) = X ₁ ⁰ (87)

U ₁ & H ₂ ⁰ & H ₁ O & J ₁ ⁰ ) V (X ₂ ⁰ & T8c T ₁ ) V (X ₂ ⁰ & T8c F ₂ ⁰ ) V (X ₂ ⁰ & T8c W ₁ ⁰ ) V (X ₂ ⁰ & X ₁ ⁰ ) = X ₂ ⁰ (88)

(Z ₁ & H ₃ ⁰ & H ₂ o & J ₂ ⁰ ) V (X ₃ ⁰ & T8c T ₁ ) V (X ₃ ⁰ & T8c H ₃ ⁰ ) V (X ₃ ⁰ & T8c F ₀ ⁰ ) V ( X ₃ ⁰ & X ₀ ⁰ ) = X ₃ ⁰ (89)

(Z ₁ & F ₀ ¹ & H ₃ ⁰ & J ₃ ⁰ ) V (X ₀ ¹ & T8c T ₁ ) V (X ₀ ¹ & 7 & F ₀ ¹ ) V (X ₀ ¹ & T8c F ₃ ⁰ ) V ( X ₀ ¹ & X ₃ ⁰ ) = X ₀ ¹

(90)

(Z ₁ & F ₁ ¹ & / ^ ₀ ¹ & J ₀ ¹ & F ₃ ¹ ) V (X ₁ ¹ & T8c T ₁ ) V (X ₁ ¹ & T 8c F ₁ ¹ ) V (X ₁ ¹ & 7 & F ₀ ¹ ) V (X ₁ ¹ & X ₀ ¹ ) = X ₁ ¹

(91)

(Z ₁ & F ₂ ¹ & H ₁ ¹ & J ₁ ¹ ) V (X ₂ ¹ & T8c T ₁ ) V (X ₂ ¹ & T8c F ₂ ¹ ) V (X ₂ ¹ & T8c F ₁ ¹ ) V ( X ₂ ¹ & X ₁ ¹ ) = X ₂ ¹

(92)

(Z ₁ & F ₃ ¹ & H ₂ ¹ & J ₂ ¹ ) V (X ₃ ¹ & T8c T ₁ ) V (X ₃ ¹ & T 8c F ₃ ¹ ) V (X ₃ ¹ & T8c F ₀ ¹ ) V (X ₃ ¹ & X ₀ ¹ ) = X ₃ ¹

(93)

The switching functions for the auxiliary memory remain unchanged in all decades as with the binary counter.

So that all stages of the decimal counter have the same number of inputs as the binary counter, a further development corresponding to the AND stage & _{1ββ can combine} a signal previously controlling the binary counter with the signal H ₃ from the fourth counting stage in a separate logic circuit and the output of this circuit to the AND stage & ₁₆₆ . For example, with an arrangement according to FIG. 15 a or 15 b, the signals H ₀ ¹ and H ₃ ^{1 can be} formed from the signals H 0 1 and the signal H ₀ ¹ controlling the binary counter can be replaced by the signal P ₁ ¹ .

Claims (2)

Patent claims: 1. Method of converting a static. Binary counter, which for each counting level consists of a main and auxiliary memory and controlled by counting signals and auxiliary counting signals of any form is, in a static decimal counter, characterized in that every decade consists of four binary counting stages and a signal from the fourth to the second in every decade Counting stage and a signal from the fourth counting stage is fed back to the third counting stage or that a signal from the fourth counting stage is fed back to the second counting stage and a signal from the first counting stage is led to the fourth counting stage. 2. The method according to claim 1, characterized in that that the signals required for decimal conversion have previously been driving the binary counter Replace signals or with signals that used to drive the binary counter in separate logic Circuits are summarized whose output signals replace the previously controlling signals in such a way that the structure of the binary counting stages remains unchanged. 3. The method according to claim 3, characterized in that the auxiliary memories of the second and a further signal from the fourth counting stage is fed to the third counting stage. 4. The method according to claim 3, characterized in that a logic input stage is added to the auxiliary memories of the second and third counting stage, which has the following logic switching function for the i + 1st decade (valency 10 *): (AJ & t ₂ ), where A and t _{2 are} the driving signals and the lower index of signal A denotes the significance and the upper index denotes the various decades. 5. The method according to claim 2, characterized in that the control of the auxiliary memory the second and third counting stage is modified compared to a binary counter by one of the previously driving signals of each counting stage is replaced by the output signal of a separate one logic circuit in which the previously driving signal with a signal of the fourth counting stage is summarized. 6. The method according to claim 5, characterized in that the separate logic circuit the function for the second counting level (A ₁ * V AJ) =, qj or A ₁ * & AJ = q
and the function for the third counting level (AJ V AJ) = qj or AJ & AJ = qj 35 where A, A are the driving signals and q is the output signal and the lower index denotes the significance and the upper index denotes the various decades. 7. The method according to claim 1, characterized in that the main memory of the second Counting stage a signal from the fourth counting stage and the auxiliary memory of the fourth counting stage a signal is fed from the first counting stage. 8. The method according to claim 7, characterized in that in the / + 1st decade (valence 10 *) to the input stage of the main memory of the second counting stage, a signal (HJ) is also carried from the auxiliary memory of the fourth counting stage, and in an input stage of the Auxiliary memory of the fourth counting stage, the signal (HJ) of the auxiliary memory of the previous counting stage is replaced by the signal (HJ) of the auxiliary memory of the first counting stage, H, H being the triggering signals and the lower index denoting the significance and the upper index denoting the various decades . 9. The method according to claim 2, characterized in that one of the previously the main memory the second counter stage driving signals is replaced by the output signal of a separate logic circuit in which the previously driving signal with a signal from the fourth counting stage is summarized, and that the auxiliary memory of the fourth counter stage previously driving signal is replaced by a signal from the first counting stage. 10. The method according to claim 9, characterized in that the separate logic circuit the function for the second counting level HJ & HJ = PJ or HJVHJ = PJ where H, H are the driving signals and P is the output signal and the lower index denotes the significance and the upper index denotes the various decades. 11. The method according to claim 1, characterized in that the main memory of the second Counting stage a signal from the fourth counting stage and the main memory of the fourth counting stage Signal from the first counting stage is supplied. 12. The method according to claim 11, characterized in that in the i + 1st decade (valence 10 *) to the input stage of the main memory of the second counting stage, a signal (HJ) is also carried from the auxiliary memory of the fourth counting stage and in an input stage of the main memory of the fourth counting stage, the signal (HJ) of the auxiliary memory of the previous counting stage is replaced by the signal (HJ) of the auxiliary memory of the first counting stage and the signal (AJ) of the main memory of the previous counting stage is replaced by the signal (AJ) of the main memory of the first counting stage, with H , H and A are the driving signals and the lower index denotes the significance and the upper index denotes the various decades. 13. The method according to claim 2, characterized in that one of the previously the main memory the second counter stage driving signals is replaced by the output signal of a separate logic circuit in which the previously driving signal with a signal from the fourth counting stage is summarized, and that the main memory of the fourth counter stage so far driving Signal is replaced by a signal from the first counting stage. 14. The method according to claim 13, characterized in that the logic circuit for the second counting stage the function HJ & HJ = PJ or HJVHJ = PJ where H, H are the driving signals and P is the output signal and the lower index denotes the significance and the upper index denotes the various decades. In addition 3 sheets of drawings 509 718/407 10.65 © Bundesdruckerei Berlin