DE1298559B - Circuit arrangement for bilateral pulse reduction for electronic bidirectional and differential pulse counters - Google Patents

Description

The invention relates to a circuit arrangement for bilateral Pulse reduction for electronic bidirectional and differential pulse counters, whereby when receiving pulses of the first type upwards and when receiving pulses of the second type is counted down and the one input is one with two inputs provided AND gate receives pulses of the first type and its other input is then energized by the counter to open the gate when the counter is up is at the upper limit of its counting range, and with one input of another AND gate equipped with two inputs receives pulses of the second type and its other input is then excited by the counter to open this gate, when the counter is at its lower limit of its counting range, where a register is connected to the output of each AND gate, which when opened the corresponding AND gate stores the pulses of the corresponding type, and delay circuits being provided for delaying the opening of each AND gate are to delay the opening until the end of the pulse that causes the counter to open sets the corresponding limit value of its counting range. In particular, relates the invention relates to such an electrical circuit arrangement which is used for summing electrical signals are used from a variety of sources, such as from meters for electrical energy.

An electrical circuit arrangement is already known in which a storage device in the form of a single flip-flop is provided, so as to store the incoming signals; this is done by a in the storage device incoming signal of one kind deleted the signal of the other kind contained therein, a first signal register is used to register each signal of the first type, which enters the storage device after the signal of the second kind is deleted therein; there is also a second signal register for recording signals of the second type which enter the storage device after the stored signal of the first type has been deleted. Finally is at this known circuit arrangement also includes a delay circuit between an output of the flip-flop and a corresponding signal register. With this well-known Arrangement is disadvantageous, however, that with close succession of the pulses first and second type an incorrect operation can occur, in particular when the pulses are not sharp or when the pulses are a have an expanded width. This known circuit arrangement can only therefore work satisfactorily when the incoming signals are a well-defined one Have shape.

Further, one is responsive to electrical pulses of a first and second type appealing circuit arrangement known in which a reversible counter by Impulses of one kind are counted upwards and impulses of the other kind are counted downwards will. The impulses of one kind are thereby via a first AND gate and the Received pulses of the other kind via i a second AND gate. The counter generates corresponding output variables if it exceeds the upper limit value or the lower limit value reached its counting range. These two output variables of the counter control corresponding ones Delay circuits. When the counter reaches its upper limit, so comes at the end of the delay period one of the delay circuits in its operating state and closes the AND gate controlling the passage of the pulses of the first type to the counter and opens a third AND gate, which sends these pulses directly to a circuit output can get. When the counter reaches its lower limit, the situation is similar Way, at the end of a delay period, the other delay circuit in its Operating state and closes the passage of the pulses of the second type to the counter controlling AND gate and opens a fourth AND gate, which receives the pulses of the the second type can reach a further circuit output.

In this known circuit arrangement and also in the first mentioned known circuit arrangement ensure the delay circuits, that a pulse that sets the counter to its lower or upper limit value, cannot run to the corresponding circuit output at the same time; with others In words: the delay circuit in question ensures that this pulse is complete must have come to an end before the path to the corresponding circuit output is opened will. In the second known circuit arrangement, however, it is disadvantageous that it is relatively complicated and has four AND gates and two delay circuits needed.

To avoid the disadvantages of these known circuit arrangements is provided according to the invention that each delay circuit the delay the impulses of the first or second type when entering the meter makes and it also forms the pulses and that the two AND gates connect directly to the counter are in communication so that they are opened immediately when the counter denies corresponding limit of its counting range has been reached.

In this way the delay circuits form the only connection between the incoming pulses and the counter inputs, and the counter outputs are directly connected to the AND gates feeding the signal registers. The delay circuits can thus be designed for pulse shaping and also the required Make a delay effect; the circuit arrangement provided according to the invention gets by with a minimum of components because it only requires two AND gates.

An electrical circuit arrangement is described below as an exemplary embodiment for summing electrical signals described by a variety of electrical Energy meters are generated; some of these meters measure the flow of electrical energy to a specific point in a power circuit, and some measure the dated Point running away electrical energy flow.

In the drawing showing an exemplary embodiment, FIG. 1 is a block diagram of the circuit arrangement, FIGS. 2A, 2B are detailed Circuit of the circuit arrangement.

The measurement of electrical energy on a Job in a complex circuit network includes the consideration of the energy flow in two directions, d. H. to and from the point in question. in the the following are the expressions "import" and "export" to describe the two Directions of flow used. For practical reasons, knowledge of the net export electrical energy away from a certain point and the net import of electrical Energy to a certain point may be necessary. These two sizes are given one from a comparison of the (total) gross exports of energy and gross imports of energy. The circuit arrangement to be described measures these gross values Summation of electrical impulses from a multitude of suitably switched on Electricity meters come in and also subtract the smaller of the gross quantities from the larger one and puts the result on the associated register of two registers which show the net export or the net import of energy.

The circuit arrangement (FIG. 1) has a memory 10 in the form of a reversible (reversible) non-cyclic counter which can count from "1" to "5"; a net import register 12 and a net export register 14 are also provided. The circuit arrangement has two input lines 16 and 18. The line 16 is connected via a suitable circuit, not shown, to one or more measuring meters for electrical energy, also not shown, and carries "import" pulses, each of which represents the measurement of a predetermined amount of electrical energy. which flows to the particular point at which the measurements are made. The line 16 is connected to an AND gate 20, the output of which is connected to the net import register 12. A line 22 connects the line 16 via a delay circuit 24 to one input 26 of the counter 10, whereby each pulse on the line 16, after being increased by the delay circuit 24, increases the counter reading in the counter 10 by one. When the counter reaches the count "five", further pulses on line 16 have no effect on it.

The line 18 is via a control circuit (not shown) with a or several further, likewise not shown, measuring meters for electrical energy connected and carries out "export" pulses, each of which is the measurement of a given Represents the amount of electrical energy obtained from the point at which the measurements are taken become, flows away. The line 18 is connected to an AND gate 28, whose Output is connected to the net export register 14. A line 30 connects the line 18 via a delay circuit 32 to the other input 34 of the Counter 10, which removes each pulse on line 18 after passing through the delay circuit 32 was delayed, the counter reading in counter 10 was reduced by one. When the counter When the count reaches "one", further pulses on line 18 have no effect out on him.

The counter 10 has two output lines 36 and 38 which are connected to the second inputs of the AND gates 20 and 28, respectively. Line 36 is energized when the count in counter 10 is "five", while output line 38 is energized when the count in counter 10 is "one".

The control circuit, not shown, which sends the pulses into the lines 16 and 18 feeds, ensures that only one line at any one time Impulse can lead.

The mode of operation of the circuit arrangement is described below.

It is assumed that the counter 10 has a count of "five" and that successive export pulses occur on line 18 while the line 16 does not carry any pulses.

Each of the first four export pulses arriving on line 18 after they have been delayed in the delay circuit 32 reduces the count of the counter 10 by one, but has no other influence on the circuit arrangement: these four export pulses cannot be processed by the AND gate 28 pass through to register 14 . The fourth export pulse has the effect, however, that the count in counter 10 is reduced to "one", so that line 38 is energized. The fifth export pulse and each subsequent export pulse can thus run directly through the AND gate 28 and increase the total in the net export register 14 by one.

It is now assumed that 16 import pulses arrive on the line. Since the line 36 is not energized, the first four input pulses do not run through the AND gate 20 to the register 12, but only serve to increase the count of the counter 10 from "1" to "5", whereupon the line 36 is energized. The fifth input pulse on line 16 can therefore run through AND gate 20 and is registered in net import register 20 .

If, for example, only two import pulses are received on line 16, the counter will only assume a count of "3" and both AND gates 20 and 28 are kept closed. If the next following pulse is an export pulse on line 18 , the counter 10 will assume a count of "2" and both AND gates remain closed. Only when a sufficient number of pulses of one type (either export or import pulses) have arrived to cause the memory 10 to assume either a count of "1" or a count of "5" will further pulses be generated fed into the associated register 12 or 14 of this type. In this way, registers 12 and 14, respectively, store the net amount of imported and exported electrical energy. The capacity of the counter 10 determines the number of pulses that; is taken into account when determining the net number. The counter shown in the drawing has a capacity of four. In other words, this means that only four pulses of one type (export or import) can be neutralized by the pulses of the other type, the previously received pulses of one type already being irrevocably recorded in the appropriate register 12 or 14. The pulses already recorded can of course be included in the calculation at any time by subtracting the lower reading of the two registers 12 and 14 from the higher one. The capacity of the counter 10 can be increased if necessary, and if it is of such a size that it is able to store the maximum number of pulses of any kind which in practice are likely to occur consecutively, then on At the end of a given period of time only one of the registers 12 and 14 register a total which depends on whether a net import or a net export of electrical energy has taken place. If the capacity of counter 10 is insufficient to count the maximum number of consecutive pulses of any kind, both registers 12 and 14 will show a total at the end of any given period of time, requiring the subtraction of the lower total from the larger total, to get the true net import or the true net export.

The delay circuit 24 is provided to prevent an import pulse arriving on line 16 from simultaneously switching the counter to count "5" and running through the open AND gate 12: the delay circuit ensures that the pulse from line 16 has disappeared until the counter is set to the counter reading "5"; therefore this pulse cannot pass through the opened gate 20. The delay circuit 32 has the same effect on the export pulses.

There is already a proposal for a circuit arrangement to receive signals from a variety of electrical energy meters, each signal measuring a predetermined amount of electrical energy represents one of the counters. A memory is provided for each such counter and each memory can store one signal each; the system further comprises a scanning arrangement for successive reading of the signals from the memories. If in a some of the electrical energy meters can be connected to such a system, to measure the import of energy to a point in a power circuit, and if so some other meters can be connected to export electrical energy from To measure this point, the lines 16 and 18 can use appropriate OR gates be connected to the outputs of suitable memory, and you can reach them Way that a pulse on line 16 does not coincide with a pulse on line 18 occurs.

The F i g. 2A and 2B show the circuit arrangement of FIG. 1 going into more detail, and the parts in FIGS. 2A and 2B, which correspond to parts in FIG. 1, have been given the same reference numerals. The in F i g. The counter 10 shown in FIG. 2A has four bistable transistor circuits 40 to 46, each of which is then in the "1" state when its left transistor is non-conductive, and each of which is then in the "0" state when you are on the right lying transistor is non-conductive. If all the bistable circuits are in the "1" state, the counter contains a count of "5", and the line 36 is excited by the non-conduction of the left transistor of the bistable circuit 46 and then carries a negative voltage. If all the bistable circuits are in the "0" state, the counter has a count of "1" and the line 38 is excited by the transistor of the bistable circuit 40 on the right not conducting. If all of the bistable circuits with the exception of circuit 46 are in the "1" state, the counter contains a count of "3"; if only the bistable circuit 40 is in the "1" state, the counter contains a count of "2".

The delay circuits 24 and 32 have corresponding one-shot circuits. Each import pulse on line 16 switches the monostable circuit 24 which, after a predetermined time interval, feeds a positive pulse via a capacitor C 1 and a diode D 1 into the input 26 of the counter 10; the input has four capacitors C 2 to C 5, which are connected to the left-hand transistors of the bistable circuits 40 to 46 in a corresponding manner. Each export pulse on line 18 switches the monostable circuit 32 which, after a predetermined time interval, delivers a positive pulse to the input 34 of the counter or memory 10; this input has four capacitors C6 to C9 , which are correspondingly connected to the transistors of the bistable circuits 40 to 46 on the right. The positive pulses applied to input 26 render the left-hand transistors of circuits 40 to 46 non-conductive in sequence, while the positive pulses applied to input 34 render the right-hand transistors of the circuits non-conductive in the reverse order. Accordingly, the counter 10 can be viewed as a memory in which the conduction of each of the left transistors represents the storage of a corresponding export pulse, while the conduction of each of the right transistors represents the storage of a corresponding import pulse.

The AND gate 20 includes a pair of diodes D 2 and D 3 which control the conduction of an output transistor TR 1; the diode D 2 is switched on in such a way that it is switched off when the line 36 is excited, ie carries negative voltage, the diode D 3 is connected via a transistor TR 2 and a diode D 4 to the line 16 in such a way that it is switched off by each pulse on line 16. When both diodes D 2 and D 3 are switched off, the transistor TR 1 is made conductive and applies a pulse to the register 12. The operation and structure of the AND gate 28 is the same.

Claims (1)

Claim: Circuit arrangement for bilateral pulse reduction for electronic bidirectional and differential pulse counters, whereby when receiving Pulses of the first type upwards and, when receiving pulses of the second type, downwards is counted and one input of an AND gate provided with two inputs Receives impulses of the first kind and then its other input is excited by the counter will to open the gate when the counter is at the upper limit of its Counting area is located, and one input is equipped with another with two inputs AND gate receives pulses of the second type and its other input through the Counter is then energized to open this gate when the counter is at its the lower limit of its counting range is located, being with the exit Each AND gate is connected to a register which, when the corresponding AND gate stores the pulses of the corresponding type, and delay circuits to delay the opening of each AND gate are provided to the opening up to delay the end of the pulse, which takes the counter to the appropriate limit adjusts its counting range, d a -characterized in that each delay circuit the delay of the impulses of the first or the second kind upon entering the Counter makes and thereby also forms the pulses, and that the two AND gates are directly connected to the meter so that they can be opened immediately, when the counter reaches the corresponding limit of its counting range.