DE1282795B - Method for manufacturing semiconductor devices - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY GERMAN ^ ¥ W PATENTAMT Int. CL:

HOIl

EDITORIAL

German KI .: 21g -11/02

Number: 1282795

File number: P 12 82 795.1-33 (ST 22908)

Filing date: November 6, 1964

Opening day: November 14, 1968

The invention relates to a method of manufacture a semiconductor arrangement according to the planar diffusion technology with semiconductor areas that are defined by pn junctions are separated from the rest of the semiconductor body.

The structure known as planar is obtained in such a way that in a disk-shaped semiconductor body of a certain conductivity type (p or n) and of the desired conductivity value Areas of a surface are successively diffused different contaminants, so that Layers of different conduction types are connected to one another by pn junctions, which end at the surface of the semiconductor body. To protect the pn junctions that emerge there, which represent the most sensitive parts of the semiconductor body, its entire surface is initially covered with silicon dioxide. In this layer there are windows of a certain area through a etched photolithographic process and carried out the diffusion at these points. After all, it becomes so attached to the contact surfaces on the individual zones of the transistor or diode and lead wires attached to it.

Regardless of the type of semiconductor material, for example silicon, germanium or a semiconducting one Compound, a protective coating of silicon dioxide has been found to be most beneficial, either has grown by oxidation of the semiconductor material itself, as is the case with silicon, or which, as is the case with the other semiconductor materials, was applied externally. At the start of the procedure it is necessary to etch windows in this coating, so in the following one Diffusion of the contaminant material through the otherwise impermeable oxide layer onto the semiconductor surface can get.

The object of the invention is to provide a new method for the production of planar semiconductor arrangements to specify. In particular, it is the object of the invention to provide planar arrangements with improved Establish properties including arrangements with very low residual current. This is according to the invention achieved in that first in a disk-shaped semiconductor body of the one Conduction type a semiconductor layer of the second conduction type is produced that then on the surface the semiconductor layer of the second conductivity type is the location of a for receiving an active semiconductor switching element provided semiconductor area covered with a correspondingly designed oxide mask is that then the semiconductor layer of the second conductivity type by diffusion of impurities of the first Method for manufacturing semiconductor devices

Applicant:

German ITT Industries

Company with limited liability,

7800 Freiburg, Hans-Bunte-Str. 19th

Named as inventor:

Dave Francis Thomas Dunster, London

Claimed priority:

Great Britain November 15, 1963 (45 228.)

Conduction type is completely converted into the original conduction type of the semiconductor body, with the exception of the part lying under the oxide mask, and that finally in the semiconductor areas isolated in this way of the second conductivity type for the production of active semiconductor switching elements required semiconductor zones of different conductivity types by diffusion of the corresponding impurities be generated.

Layers of the semiconductor body are intended to be among the layers which are covered by the oxide layer be understood, in which active semiconductor switching elements are to be generated, for example the pn junction for a diode or the base and emitter zone for a transistor. The rest the semiconductor body does not play a role in the mode of operation of the special semiconductor switching element, except that it serves as its carrier and for insulation from other semiconductor switching elements, which can be arranged in the finished semiconductor body.

From French patent specification 1341029 is a method is known which is used, in the case of one accommodated in a semiconductor body, of several Semiconductor switching elements existing integrated circuit an already generated, but superfluous short-circuit the pn junction at the same time as the emitter diffusion. For this purpose, the head

809 637/1106

3 4

surface of the semiconductor body a recess diffused from the surface in order to produce one or more depths such that the η-conductive layers of high conductivity in the diffusing impurity material up to the semiconductor p-layer diffused in the emitter diffusion, as in the case of 5 body can penetrate and thus the line type is shown. The two layers 5, which can be seen in FIG. 3 of the overlying layer in the conductivity type of 5, extend slightly below the oxide surface 4 converts semiconductor body. In contrast to and form pn junctions 6, which within the present method are therefore common here, as is common practice, the conductivity type of a layer pass through and are then bent in depth, so that overcompensating counter-doping converted. it will be horizontally just below the original. In the method of the invention, however, there will be an io pn junction. Overlapping of the pn-over-layer of a certain type of conduction and certain passages must be avoided, so that the geometry is not generated by the fact that this layer can produce desired npn-layers, while the diffusion is masked. The semiconductor body is now subsequently or

—Furthermore - is.-from ~ _der-_deutschen-_Auslegeschrift also- at the same time.jn with "the diffusion step on _der.

1 033 787 a method for producing a pnp-15 whole surface is oxidized, as shown at 7 in FIG. 4th or npn structure known, in which is represented by using, so that there is an increased thickness formation of impurity flate'riäl of different diffusion, where originally the oxide layer was present. speed in a diffusion step, the p-layer below the original oxide

three-layer structure can be generated. A layer is contacted in such a way that a Cover using JV masks is not provided. 20 windows 8 etched into this original oxide layer

'The "invention will now be based on the figures"_; and metal electrodes 9 are applied, explained in more detail, in which individual steps. Fig. 4 shows a typical planar pn diode with

lying procedure are shown. "" ■ an access to the p-layer via the contact 9,

Fig. 1 shows a layer of semiconductor material with access to the n-layer 5 via the Haüptvomn type, into which an acceptor element is diffused 35 mass of the semiconductor body 1 and with a pn; '' ■ "Transition through what is known as a passivating

F i g. 2 shows a semiconductor body which is protected by an oxide layer 7.

Diffusion generated p-layer, in which a certain ^ With these diodes can be achieved that the surface area silicon dioxide "is covered;" breakdown voltage between the epitaxial Fig. 3 shows a further diffusion of the impurity layer and the semiconductor body through the diffusion material from η-type to that around the oxide mask _s - _{: is} not changed significantly, so that after these

p-type arranged layer; Process Zener diodes can be manufactured.

Fig. 4 shows the "on the surface completely. The diode structure described above can be used for

oxidized disc with a window in the origin- making a planar transistor, if borrowed oxide mask in which a contact material is added to an emitter zone. This is one

was brought so that a diode results; further η-conductive layer (for the arrangement according to

FIGS. 5 to 8 show further modifications of FIG. 3), which are below the original area Embodiment according to FIGS. 3 and 4, whereby silicon dioxide is produced. With consideration,

a transistor of the npn type results; but on the fact that the contaminant concentration

Fig. 9 shows a PNP type transistor; 40 at the first η-conduction producing diffusion ab-F ig. 10 shows details of a pn junction that is chosen to be visibly high, in particular at the

the embodiment of Fig. 9. surface, it may be too high (and

In Fig. 1, a disk-shaped semiconductor is uncontrolled) in order for an emitter zone to

body 1 made of ri-conductive silicon of suitable suitable, which a carefully selected concentration Resistance shown, for example a thin 45 requires. It is therefore appropriate to use a second Mas-silicon wafer or to use a coating on a silicon wafer and another diffusion, low resistance (n + type) grown epitaxially to produce the emitter region. This is in the table layer. In this η-conductive silicon, boron is shown in FIGS. 5 to 8.

(B) diffuses in from an exposed surface. Fig. 5 shows a semiconductor body with the structure

dated, so that a p-conductive layer 2 and a planar 5 ° construction of FIG. 3 after the first phosphorus diffusion, pn junction 3 obtained between the two layers ^ _; which "is completely made of a new layer 7 and 4. Silicon dioxide is covered. By means of the photo-etching

The surface of the semiconductor body is now technically a window 8 in the middle of the originally determined Sites are oxidized, producing any known borrowed oxide layer4, as shown in FIG. 6 Method for applying or producing 55 is shown. Then the semiconductor body is again Silicon dioxide on the silicon surface uses donor impurities, such as. B. phosphorus exposed can be so that certain areas of the upper (Fig. 7), but this time in much more precisely controlled area protected in the next process stage or amount, so that the emitter zone 10 is formed, are isolated. As shown in FIG. 2, the pn junction 11 between the emitter and for example a single area of oxide 4 on the base extends beyond the edges of the window 8 Silicon surface generated. This oxide layer has extended under the oxide layer 4. Finally, a thickness of about 1 μm. as shown in Fig. 8, the windows 8 and 12 off

In Fig. 3 the next process step is shown - the oxide layer is etched out in order to create the metallic structure, in the case of phosphorus (P), a donor interfering substance, to be added at bars 9 for the base and emitter zones Bring the surface of the semiconductor body in a con 65. There can also be a contact for the collector centering applied larger than that of zone 2 when a contact is made to the Bors is the upper surface of the semiconductor body which is present in silicon on the surface is. The phosphorus will'in the exposed parts of the will. However, this is not shown. '

The described structure of a transistor of the npn type is for the application of the present one Process particularly suitable due to the generally higher diffusion constants of donors than that of acceptors in silicon. However, the method according to the invention can also be used for Manufacture of pnp transistors are used when boron and phosphorus are used as impurities. In such a ball, the surface concentration must be properly adjusted so that it is ensured that the diffusion front of the donor impurities is exceeded by the acceptor diffusion that is, the ratio of the .surface concentration the acceptors to which the donors must be chosen as high as possible.

In the following table are the diffusion coefficients "of some contaminants, measured at around 1100 ° C.

Disruptive material . temperature
in
■ ⁰ C Diffusion
coefficient in
10- "cm ² / s gallium 1105 61.5 gallium 1170 200 boron 1020 5.7 boron 1122
1030
1148.
1095 110
5.7
130
2.9 phosphorus 1190 41 phosphorus 1095 1.9 arsenic 1190 10.5 arsenic antimony antimony

(From: C. S. Fuller and J. A. Ditzenberger, "Diffusion of Donor and Acceptor Elements in Silicon", Journal of Applied Physics, Vol. 27 [1956], H. 5, pp. 544 to 553.)

In a typical embodiment, the starting material is p-conductive, the first pn junction 3 is obtained by phosphorus diffusion, and boron becomes round as the main diffusion with high concentration around the first oxide surface 4, the layers 5 in FIG. 3 can be obtained. The final diffusion through the windows in the original oxide surface to produce the emitter zones also carried out with boron, and in a carefully controlled amount. The transistor geometry obtained in this way is in Fig. 9 shown. The corresponding contacts are also shown there.

However, it is known that pnp transistors have unfavorable reverse-bias properties, what Perhaps this is due to the fact that the oxide layer on the surface of the disc is beneath the oxide Donor impurities forms or that it acts as such, so that a high resistance layer of the p-type arises, or that a layer is converted to n-type, which extends the transition is equivalent to. In this way a high resistance channel is formed under the oxide layer, and the space charge layer of the collector-base pn junction extends over the surface in this channel.

The method of the invention for making diodes and transistors makes the formation of surface channels much less likely, which is evident from the structure of the pnp transistor from F i g. 9 should be explained.

10 shows the collector-base pn junction 6 of the pnp transistor of FIG. 9 in detail. The pn junction 6 separates the diffusion 5 of a large one Concentration of p-material from normal diffusion 2 (the first diffusion) of n-material, which takes place around the oxide layer. However, the diffusion 5 only extends to the edge of the oxide layer 4 a great concentration (dense horizontal lines). This is followed by a gradual transition

ίο until the pn junction, after which a lower concentration of the η material (less dense horizontal lines) that forms the base. The mode of action of this training is. the fact that the space charge layer is not over the edge the oxide layer and is effectively anchored in the high concentration layer (Layer 5 low resistance), whereby the

Reverse current is reduced.

'This effect can be used with diodes as well as transistors and is used for Improvement of the characteristic of the diodes in which an η-layer is created in a p-type disk became.

If the original η-layer is an epitaxial Is a layer which has been produced by growing on a p-type substrate in such a way that a pn junction with a certain breakdown voltage results, this pn junction can be as above described, isolated in small pn junctions of the planar type, d. H. divided by the Diffusion of an acceptor element, for example boron, to create zones 5, which up to the base advance of the p-type. In this way, you can take advantage of the epitaxial process and the planar process be united. Similarly, phosphorus diffusion can be used to To isolate surface parts of the pn junction from each other, which occurs when a p-type layer is grown was generated on a substrate of the η type.

It should be noted that the breakdown characteristic generally has the disadvantage of being slightly to change, in the direction of higher tension. This is especially true with the controlled Low voltage breakdown of Zener junctions is the case.

Another interesting case is the production of transistors from epitaxial wafers with pn junctions, as described above. With the usual planar technique, in which all diffusions are etched through If windows take place in the original oxide layer, the diffused zones have a graduated concentration and a graded resistance, particularly in the base zone. In the case of orders, however, made by the method according to the invention, the base zone is of the epitaxial one Layer through the diffusion around the oxide layer - the usual planar process is just the opposite - isolated, and so the base zone is uniform everywhere and has no graded resistance since the epitaxial one Precipitation occurs over the entire surface of the disc.

One advantage of this method is that a better characteristic curve of the emitter-pn junction, d. H. the breakdown voltage results.

The emitters of transistors, whose collector-base-pn-junction, as described above, can be prepared by one of the known processes getting produced. The diffusion process can

for example by gas etching with the following epitaxial precipitation are replaced.

Claims (9)

Patent claims: 1. Method of manufacturing a semiconductor device according to the planar diffusion technology with semiconductor areas, which are created by pn junctions are separated from the rest of the semiconductor body, characterized in that initially in a disk-shaped semiconductor body (1) of one conductivity type, a semiconductor layer (2) from second conductivity type is generated that then on the surface of the semiconductor layer (2) from second conductivity type, the location of a provided for receiving an active semiconductor switching element Semiconductor area is covered with a correspondingly designed oxide mask (4) that then "<iie ^ Tlälbleiferschicht (^)" from the second Conduction type by diffusion of impurities of the ao first conduction type completely into the original Conduction type of the semiconductor body (1) is converted, with the exception of the below Oxide mask lying part, and that finally in the so isolated semiconductor areas of the two-as th conductivity type required for the production of active semiconductor switching elements Semiconductor zones of different conductivity types are generated by diffusion of the corresponding impurities. 2. The method according to claim 1, characterized in that that the semiconductor layer (2) is produced by diffusion. 3. The method according to claim 1, characterized in that that the semiconductor layer (2) is produced by epitaxial growth. 4. The method according to claim 1, characterized in that either as a cover mask one on the. Foreign oxide layer applied to the semiconductor surface or one produced on it Self-oxide layer is used. 5. The method according to claim 1 or 4, characterized in that several limited areas the semiconductor layer surface are covered with an oxide layer, so that when diffusing of the impurities of the first conductivity type island-shaped zones of the second conductivity type in of the semiconductor layer surrounded by the semiconductor material of the first conductivity type are. 6. The method according to claim 1, characterized in that that during or after the diffusion of impurities of the first conductivity type into the semiconductor layer on its whole Surface an oxide layer is generated and that then holes in this oxide layer Attaching contacts to the individual semiconductor zones are made. 7. The method according to claim 1 or 5, characterized characterized in that during or after the diffusion of impurities of the first conductivity type into the semiconductor layer over the whole Surface an oxide layer is generated that then in this oxide layer holes of smaller diameter and concentric to the ones in front of the Diffusion of impurities of the first conductivity type Areas of the semiconductor layer surface that have been covered with an oxide layer are generated will that continue to generate contaminants at these points freed from the oxide layer are diffused in by semiconductor zones of the same first conductivity type as that of the semiconductor body, simultaneously or subsequently a new oxide layer on the whole Surface of the semiconductor layer is formed, and that eventually holes in the oxide layer through which the individual zones are contacted. 8. The method according to any one of claims 1 to 7, characterized in that silicon is used as the semiconductor material. 9. The method according to one or more of claims 1 to 8, characterized in that on the surface of the unconverted parts of those created by the second diffusion Layer (2) prevents channels of high resistance or channels with conduction type inversion that a high surface concentration of contaminants on the mask uncovered areas is chosen. Considered publications:
. German Auslegeschrift No. 1033 787;
French patent specification No. 1341 029. 1 sheet of drawings 809 637/1106 11.68 © Bundesdruckerei Berlin