DE1279085B - Circuit arrangement for decoding information symbols with the aid of magnetic core logic - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H 03 k

German KL: 21 al - 36/20

Number: 1279 085

File number: P 12 79 085.1-31 (A 50944)

Filing date: December 2, 1965

Open date: October 3, 1968

The invention relates to a circuit arrangement for decoding binary encrypted information ■ characters, especially telex characters, consisting of η bits. The bits of each character can be entered both simultaneously and sequentially. The decoding will with the help of .Magnetic cores with a quasi rectangular hysteresis loop, which by means of several windings are interconnected to an output logic, executed.

There are also electromechanical or as Diode matrix constructed decoders or allocators are known, but the invention relates specifically on magnetic core allocator. These are preferred to the known circuits if one is very high operational reliability is required.

The well-known magnetic core allocators - as they are τ. B. in the "Taschenbuch der Nachrichtenverarbeitung" by K. Stiinbuch, 1962, on page 502 and in FIG. 1 of the drawing - have the disadvantage that in order to decipher m binary characters consisting of η bits, m signal loops with different threads must be individually threaded through up to η magnetic cores or η magnetic core pairs. Since this is done mostly by hand and, as is well known, requires a lot of manual dexterity, the work time is considerable.

Furthermore, in the case of the crowned magnetic core allocators, the distinction? 'Vk; hen an to be evaluated and a character that cannot be evaluated, often by a threshold at the input of a downstream one Evaluation level reached. Here, the tolerances of the magnetic cores also have an effect occur in their partial signals, disturbing.

According to the invention, these disadvantages in a circuit arrangement for decoding binary-coded information characters, preferably telex characters, with the help of magnetic core logic in which the η bits of a character are assigned η magnetic core pairs, namely the regular and the negated signal of all bits of a character each Cores that are interconnected by signal loops in such a way that when the cores are queried via an interrogation winding, a useful signal is only available at the output of that signal loop whose assigned character was stored in the cores, thereby eliminating the partial signals from the first core pair or from ( 1 + i) core pairs [(I + 1) <«] separated from those of the [« - (1 + O] other core pairs are logically linked by signal loops, in such a way that the [n - (1 + i)] circuit arrangement for Decoding of
Information signs with the help of a
Magnetic core logic

Applicant:

Wolfgang Assmann G. m. B. H.,

6380 Bad Homburg, Industriestr. 5

Named as inventor:

Theodor Nocken, 6000 Frankfurt;

Herbert Ritzenthaler, 6380 Bad Homburg

Core pairs and the i core pairs several signal loops are included in parallel (that is, at the same time during production), in the same direction for all cores to which a regular signal is assigned, and in opposite directions for all cores to which a negated signal is assigned, furthermore the signal loops of the first core pair are connected to the reference potential zero via a compensation loop of the [n - (1 + I)] core pairs and i core pairs, such that the sum of all partial signals generated by the [w - (i + I)] core pairs and i core pairs is equal to zero, that the useful signals are only supplied by the first core pair and that the number of turns of the signal loops of the first core pair is twice as large as that of all the other signal loops.

This type of interconnection of the magnetic cores reduces the threading effort to a minimum, while at the same time the tolerance of the partial signals caused by the magnetic cores, be compensated. Another advantage is that all useful signals have approximately constant amplitudes have the same polarity and that only between signals of positive and negative amplitude or the amplitude zero is to be distinguished.

The circuit arrangement according to the invention is therefore distinguished from the known arrangements characterized by low workload and high reliability.

The invention will now be described in detail with reference to the figures. In

Fig. 1 is a known magnetic core allocator shown schematically; in

809 619 515

F i g. 2 is a magnetic core allocator according to the invention for a five-digit binary code for four certain telex combinations and in

F i g. 3 shown schematically for four further telex combinations.

To simplify the representation of the magnetic cores and their windings, the mirror symbolism according to RP Mayer is used here (see the book cited above, p. 482 and the first reference [1] on p. 509). The magnetic cores are in this case represented by thick vertical lines and their windings by horizontal. The lines t at their intersection points at 45 ° indicate the winding direction. The directions of current in the windings are indicated by arrowheads.

In Fig. 1, a known magnetic core allocator is shown schematically, in which the regular signals ■ X ₁ ... X ₁₁ outlines of a character and their negations X ₁ ... X _n each have a core K ₁ ... K _n or K ₁ ... K _{n is} assigned. That is, each signal pair X ₁ , X ₁ ... X _n , X _{n of} the η bits of a character, or in short, each bit is assigned a core pair K ₁ , K ₁ ... K _n , K _n . Magnetic core allocators are also known which only decode the regular or true signals X ₁ ... X _{n of} the bits of a character. Then only η kernels are required. To increase security, however, as in the example shown, the negated signals X ₁ ... X _{n are} usually decoded. The signals X ₁ ... X _{n of} the η bits magnetize or "set" the η core pairs via set windings SW ₁ ... SW _n according to the bit combination of the character currently being decoded.

Accordingly, the characters are to be decoded signal m grinding SS ₁ ... SS _n sequentially performed only by very specific cores, and specifically where g in Fi. 1 an oblique line is drawn. This means that each signal loop is assigned to a specific character. All signal loops are connected to one another on one side and via a switch Z to the reference potential zero. The switch Z is only closed when the cores are queried.

The partial signals emitted by the set cores when the magnetic cores are interrogated with the aid of an interrogation winding AW that runs through all cores in the same direction are transmitted through the signal loops SS ₁ . .. SS _n linked in such a way that a useful signal is only present at the output A ₁ ... A _{m of} the signal loop that is assigned to the set character.

The decoding of the binary character LLOO is described as an example of the mode of operation of this magnetic core allocator. _Here_ would be η = 4, X ₁ = X ₂ = X ₃ = X ₄ - LundXx = X ₂ = X ₃ = X ₄ = 0.

With this_character LLOO the kernels If ₁ , K ₂ , K ₃ and K ₄ . set, on the other hand not all the rest. If a current is now sent through the query winding AW , then these set cores change their magnetization state at the same time and induce a voltage pulse in each of the signal loops routed through them. Since the winding sense is the same in all cores, all impulses add up in a loop. If the amount E is assigned to each pulse, then a total of 4 E are induced in the signal loop SS ₁ , whereas only 3 E are induced in the signal loop SS ₂ 0 E and in the signal loop SS _n. This means that in all loops that are not assigned to the set character, fewer impulses are induced in total than in the one assigned to the set character. A threshold set accordingly - in this example to AE - at each output A ₁ ... A _{m of} the signal loops or at the input of downstream evaluation stages, which are not shown here, is then used to determine which signal loop the currently set character is assigned to . This known circuit arrangement has now however the disadvantage that for distinguishing mark m and m variously strung signal loops SS ₁ ... SS _m are necessary. The threading effort is therefore very great, and the tolerances of the magnetic cores, which accordingly occur in the partial signals E , add up through the addition of the partial signals in the signal loops.

In Fig. 2 shows a magnetic core allocator according to the invention to explain the invention only for five-digit binary codes, e.g. B. for the well-known five-digit telex code. This allocator can, however, be extended to any number of places, generally to η places or bits per character, or limited to less than five places. Here, too, as in the known magnetic core allocator _der Fi g.J_, each binary digit or each bit X ₁ , X ₁ ... X _n , X _{n has} two magnetic cores K ₁ , K ₁ ... K _n , K _n _ assigned. Each regular and negated SignaJLXi ... X _n is again a reset winding SW ₁ ... _n associated with SFP and a Abfragewicklunj ^ yl W again in the same direction looped through all cores K ₁ ... K _n.

According to the invention, on the other hand, there are several groups of signal loops - with a five-digit binary code there are eight groups with four signal loops each, of which only one group, consisting of the signal loops SS ₃₂ , SS ₅ , SS ₂₉ and SS ₂₂ , is shown here to simplify the illustration - drawn in the same direction through all cores K ₂ ... K _n assigned to the regular signals and in opposite directions through all cores K ₂ ... K _n assigned to the negated signals, namely all signal loops of a group simultaneously in one operation.

Here i <η is chosen; in the special case of one

five-digit binary codes is i = 0 and «= 5. This is explained in more detail below. It is advisable to have a different color for each line

chosen.

The first core pair K ₁ , K ₁ separate from the n-1 remaining core pairs K ₂ , K ₂ ... K _n , K _n draw their own signal loops SS _a and SS _b. Finally, all signal loops are connected to one another according to the desired binary code. In the example shown for a five-digit binary code, for example, the _{signal loops S 32} , S ₂₉ , S ₂₂ and S ₅ assigned to the teletype combinations No ₃₂ , No ₂₉ , No ₂₂ and JVr ₅ are at their ends 13 ... 16 through lines 11 and 12 connected to each other. Furthermore, the end 13 is connected to the signal loop SS _b and the end 15 to the signal loop SS _a . Finally, the 6o ^ ends of the signal loops SS _a and SS _b are connected to each other and via a compensation _{loop A 's} , which is looped in the same direction through all π-1 core pairs, and via a switch Z to the reference potential zero. As a result of this connection between the signal loops and their combination with the compensation loop K ₅ leading through the core pairs K ₂ , Ji ₂ ... K _n , K _n , it is achieved that the useful signals to be evaluated have the same amplitude and polarity

and that the signals not to be evaluated have zero amplitude or opposite polarity to have. Tolerances of the partial signals, which are caused by the magnetic cores, are compensated.

A transistor stage T can be connected as an evaluation stage to the outputs _{A 1} ... A _n , of all signal loops. Only one transistor stage T is shown.

The function of the circuit arrangement according to the invention and the reduction of the threading effort to a minimum is shown using the example of the F. S. code.

The characters consisting of η - 5 bits are assigned η = 5 pairs of magnetic cores K ₁ , K ₁ ... K ₅ , K ₅ , which are arranged in two rows and η = 5 columns.

When storing a character, depending on the value of the individual bits, e.g. B. "0" or "1" or with teletype pause or current step, one core of the core pairs is set by a current pulse in their writing windings SW ₁ , SW ₁ ... SW ₅ , SW ₅ .

All cores are then queried via the query winding AW. All set cores induce partial signals in the signal loops SS ', SS _b and SS ₁ ... SS _{32 that link them.}

The number of all set cores is constant after each received character; so is the Number of all partial signals in the signal loops constant.

The following conditions apply to the linking of the partial signals of the 2 ⁵ - 32 possible telex characters S:

5 ₁ = X ₁ & X ₂ & X ₃ & X ₄ & X ₅

5 ₂ = T ₁ & X ₂ & X ₃ & X ₄ & X ₅

5 ₃ = X ₁ & T ₂ & X ₃ & X ₄ . & X ₅

etc.

& X ₂

& T ₅

32 differently threaded signal loops would be required.

If the linkage of the SJgHaIe _- X ₁ , X _{1 is separated} from the linkage of the remaining signals X ₂ , X ₂ ... X5, X ₅ , the conditions are obtained

<h = Xi

U ₁ = T ₁ (2)

and

f>! = X ₂ & X ₃ & X ₄ & X ₅ (3)

\ h = T ₂ & X ₃ & X ₄ & X ₅

b ₃ = X ₂ & T ₃ & X ₄ , & X ₅

etc.

/ J ₁₆ = X ₂ & X ₃ & X ₄ & X7

The conditions for the useful _{signals are then S 1} = O ₁ & fej (4)

S ₂ = O ₂ &i>!

S ₃ = «j & b ₂

etc.

S ₃₂ -O ₂ Sc b _m

Since the conditions according to (3) contain 8 * 2 complementary combinations and two identical conditions according to (3) with those according to (2) result in the conditions according to (4), one can assign eight groups in the thread shown in FIG Draw four signal loops in parallel through the core pairs X ₂ , X ₂ ... X ₅ , X ₅ . Then the signal loops SS ₁ ... SS _{32 are} interconnected with the signal loops SS _a and SS _b and connected to the reference potential “zero” via the compensation loop K _s. The compensation loop Xjj is routed in the same direction through the cores Jt ₂ , K ₂ ... K ₅ , K ₅ .
The number of partial signals induced in it is also constant, and they are opposed to the partial signals of the signal loops.

The number of turns of the signal loops SS ₁ ... SS ₃₂ and that of the compensation loop K _s are dimensioned the same.

The sum of all partial signals that are supplied by the cores K ₂ , K ₂ ... K ₅ , K ₅ is therefore always zero if the associated character was previously stored.

The amplitude of the useful signal to be evaluated provides only core K ₁ or K ₁ . Tolerances of the partial signals, which are caused by differences in the other magnetic cores K ₂ ... K ₅ , are therefore eliminated.
If the received character differs from the one assigned to a signal loop only in one bit, no signal is obtained at this loop output; If it differs in two or more bits, the result is a signal whose polarity is opposite to that of the useful signal.

The distinction can easily be made by the transistor stage T connected downstream.

The suppression of the signals generated when setting the cores is done by time selection using of switch Z reached.

The decoding of teletype combination No. 25 (LOLOL) is described as an explicit example. The routing of the associated signal loop SS ₂₅ is shown in FIG. 3.
So it is

and

Aj - '-λ 2 -— Λ3 - ^ .Λ, φ ^: -' -Ag · - xj

This symbol sets the kernels K ₁ , K ₂ , K ₃ , K ₄ and K ₅ , but not all the other kernels.

These set cores change their magnetization state when queried and induce a partial signal in each of the loops carried out. Each partial signa], supplied by the cores K ₂ ... K ₅ and K ₂ ... K ₅ , is again assigned the construction amount E. The partial signals supplied by the cores K ₁ and K ₁ have the amount 2 E, since the number of turns of the loops SS _a and SS _{h is} twice as large as that

fio of the remaining loops. The winding sense from the right to the left should result in signals of negative polarity.

Starting from the reference potential zero, at

closed switch Z, the course of the loops K _s , SS _a and SS _{25 should be} followed and all in it

f> 5 induced partial signals are added.

In the compensation loop K ₅ partial signals positive_Arapliudß are generated by the following kernel: K ₅ , K ₃ , K ₄ and K ₂ . Add these partial sinks

to the value + 4 E. In the signal loops SS _a and SS ₂₅ , partial signals of negative amplitude are generated by the cores K ₁ , K ₂ , K ₃ , K ₄ and K _5. These partial signals add up to the value - 6 E. The value of the useful signal at the loop output A ₂₅ is (+ 4 £) + (-6 £) = -2 £.

If the character stored in the decoder core differs from that of the telex combination no.25 only in the first bit, which is the case with telex combination no.8 (OOLOL), the value of the signal at the loop output A is ₂₅ (+4 E) + (-4 E) = O.

If there is a distinction in the fifth bit, such as B. with the telex combination No. 19 (LOLOO), in the signal loop SS ₂₅ . Partial signals of negative polarity are generated by the cores K ₂ , K ₃ and K ₄ , whereas the core K ₅ generates a partial signal of positive polarity in the signal loop SS _25.

The value of the signal at the loop output A ₂₅ is

Claims (1)

Claim: Circuit arrangement for decoding binary-coded information characters, preferably telex characters, with the aid of magnetic core logic in which η magnetic core pairs are assigned to the η bits of a character, namely the regular and the negated. Signal of all bits one character each one core, which are interconnected by signal loops so that when the cores are queried via an interrogation winding, a useful signal is only available at the output of that signal loop whose associated character was stored in the cores, characterized in that the partial signals from the first core pair or from (1 + i) core pairs [(I + i) <n] separated from those of the [n - (1 + i)] remaining core pairs are logically linked by signal loops (SS) , such that by the [n - (1 + 0] core pairs and the i core pairs several signal loops are drawn in parallel (ie, at the same time during production), in the same direction for all cores to which a regular signal is assigned and in opposite directions for all cores to which a The negated signal is assigned that furthermore the signal loops (SS _a and SS _b ) of the first core pair are connected to the reference potential zero via a compensation loop K _{s of} the [«- 0 + I)] core pairs and i core pairs are in such a way that the sum of all the partial signals generated by the [n - (i +1)] core pairs and i core pairs is equal to zero, that the useful signals are only supplied by the first core pair and that the number of turns of the signal loops of the first core pair is twice as high are large like those of all other signal loops (Fig. 2). Considered publications:
K. Steinbuch, "Taschenbuch der Nachrichtenverarbeitung", 1962, p. 502. Hierza 1 Platt drawings 809 619 515 9. 68 © Bundesdruckerei Berlin