DE1272973B - Method and circuit arrangement for analog-digital conversion, the analog value being compared with a reference value - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Int. CL:

H03k

German KL: 21 al - 36/00

Number: 1272 973

File number: P 12 72 973.6-31 (L 48372) Filing date: July 24, 1964 Opening day: July 18, 1968

The invention relates to a method and a circuit arrangement for analog-digital conversion (A-D conversion) in which the output signal is output naturally-binary or decimal-binary.

Processes for A-D conversion have become known which work on the counting principle. Such Converters, where z. B. a mechanical displacement by counting the speed of a drive spindle is brought into digital form, are particularly suitable for analog quantities that are used as mechanical There is a shift or can be converted into such a shift. For coding However, such converters are less suitable for purely electrical quantities. The same applies to converters, which work with mechanically or photoelectronically scanned coding disks.

In the case of an A-D conversion based on the time base principle, the analog input variable is initially transformed into an analog time segment, the length of which is counted by means of electrical impulses is determined. In the case of an arrangement that works according to the above-mentioned principle, one is called an electrical Voltage present analog value during the counting process through an electronic button removed and held. A voltage comparison circuit compares the input voltage with a sawtooth voltage and sends a pulse to the counter when the voltage is simultaneous, which ends the counting process. The process is repeated in time with the sawtooth generator, whereby the counting pulses are stored in the counter and processed further.

In the known arrangement, a very precise sawtooth generator is required. Besides, the digital value in incremental form. Coding in binary form requires additional facilities.

Furthermore, an analog-digital converter has already become known in which the analog voltage to be converted Via a fixed resistor of the parallel connection of graded according to powers of the number 2 Evaluation resistors is supplied. The individual evaluation resistances are determined via coincidence gates, which are called up one after the other by a counter and which in turn are bistable circuits tilt, queried. The digital value is output in series and dynamically via a summing network comprising all answering stations.

In contrast, the invention relates to a method for converting an analog value into a digital, preferably binary-coded, static, parallel method and circuit arrangement for analog-digital conversion, the analog value being compared with a reference value

Applicant:

Licentia Patent-Verwaltungs-G. m. b. H.,

6000 Frankfurt, Theodor-Stern-Kai 1

Named as inventor:

Dipl.-Ing. Erwin Sanetra, 6056 Heusenstamm

Output signal in which the analog value is compared with a reference value.

According to the invention, the implementation is achieved in that the analog voltage with the reference voltage over from equal fixed resistances and from parallel graded according to powers of the number 2 Evaluation resistors existing voltage dividers each assigned to a value are compared is that a comparison stage the voltage present at the voltage divider tap with a fixed voltage (OV) compares and, if they are equal, a trigger level switches, which in turn, the evaluation resistors assigned to the lower values, additional resistors each on the size of the comparison or Evaluation resistors assigned to the trigger level switched in parallel.

If the output of the converter is to be decimally coded in binary, only the evaluation resistances of the voltage dividers assigned to the last four digit values are graded according to powers of the number 2. The evaluation resistor of the following voltage divider then has ¹ I _{10 of} the value of the evaluation resistor of the last place value (2 °), the next V20 etc. Switching elements controlled by the potentials at these evaluation resistors have additional resistances when they respond to the evaluation resistances of the place values with the lower powers parallel, the size of which is equal to the size of the evaluation resistor assigned to the relevant switching element.

The switching elements are contactless switches, e.g. B. transistor switch, advantageous, the practically instantaneous switch and are not subject to wear and tear. The transistors operated in switching mode trigger levels are expediently connected downstream, which add the assigned priority values once.

809 570 «9

the associated bits, but also the switching on and off of the evaluation resistors Control parallel additional resistors. The switching on and off of these additional resistors becomes contactless again with fast and purely electronic converters, z. B. by means of transistors, carried out.

The invention is explained in more detail on the basis of the drawing showing an exemplary embodiment:

The A-D converter shown is for a decimal binary Coding of the analog values is provided, but a purely binary coding is also possible without Additional effort possible.

The analog value U _A , the z. B. can be in the form of a voltage, the input _terminal A J5 and the fixed reference voltage U _{ref is} fed to the input terminal B of the voltage dividers that are parallel to one another and each assigned to a setpoint value. The ratio of the resistors R ₀₀ and r ₀₁ assigned to the lowest value and forming the voltage divider is selected so that the voltage at the tap of the voltage divider is in accordance with the relationship

U _A ^ 00

U,

'ref

^r o, i

gets the value 0 if with a divider ratio

^ 00 1

100

the tension also behaves like -τ ^ -τ.

Uref ^lüt)

If the reference voltage U _{ref has a} fixed amount of 10 V, the potential of OV occurs at the base of the transistor T _r0 , which is connected to the voltage divider tap, at a value of the input voltage U _A of -0, iV.

The resistors R ₀₀ ... i? ₀₈₀ the voltage dividers are the same size. The transistor T _r0 then becomes conductive and triggers the trigger stage T ₀ , which emits an L signal corresponding to bit 2 ° = 1. If the analog voltage U _{A increases} after negative values, nothing changes initially. Only when it reaches twice the response _value of T p0, ie -0.2 V, does the base potential of the transistor T _{rl become} zero. The resistance r _{12 of} the associated voltage divider has half the value as the resistance r _{01 of} the first voltage divider. The transistor T _n that has become conductive triggers the trigger stage T ₁ , which emits an L signal corresponding to bit 2 ¹ = 2. The output signal of the trigger stage T ₁ simultaneously switches the additional resistor _{r Oi2 parallel to} the twice as large evaluation _{resistor r 01} . The potential at the base of the transistor T _r0 changes in such a way that T _r0 blocks again and the trigger stage T ₀ falls back into its starting position, whereby its output signal also disappears. The digital output signal is therefore 2 + Q = 2. If the analog variable U _{A increases} to the value -0.3 V, the transistor T _p0 becomes conductive again and triggers the trigger stage, which again produces an L signal corresponding to bit 2 ° so that the digital signal 2 ¹ + 2 ° = 3 is output.

If the analog value continues to grow to -0.4 V, transistor T, ₂ becomes conductive, the associated voltage divider resistance r ₂ , 4 of which is the fourth part of the value of the resistance _{r 0l} . The transistor T _r2 triggers the trigger stage T ₂ , which emits an L signal corresponding to bit 2 ^2. At the same time, from the output signal of the trigger stage T _2, the additional resistor r _Oi 4 is connected in parallel to the resistor r _{0> 1} (ratio of the resistors 1: 4) and the additional resistor r _{1A to} the resistor r _l2 (ratio of the resistors 1: 2). The potentials at the bases of the transistors T _r0 and T _rl are changed in such a way that these transistors block and the trigger stages T ₀ and T ₁ connected downstream of them fall back, ie the output signals become zero again. When the output of trigger stage T ₁ disappears, the additional resistor r ₀₂ parallel to resistor r _{01 is} switched off again. The digital output is 2 ² + 0 + 0 = 4 and corresponds to four times the basic analog unit of -0.1 V.

If the analog variable U _A grows to the value -0.5 V, the transistor T _r0 becomes conductive again, since the two parallel _{resistors r 01} and r _{0A form} a total resistance at which, given a constant voltage divider resistance R _00, a voltage drops such that the Base potential of transistor T _{r0 becomes} zero, so it conducts again. The trigger stage T ₀ thus also emits an output signal again, so that the total digital ^{signal 2 2} + 0 + 2 ° = 5. An increase in the analog variable U _A to -0.6 V causes the transistor T _rl to become conductive, the downstream trigger stage T _{1 of} which emits an output signal corresponding to bit 2 ¹ , which at the same time again switches the additional resistor r ₀₂ parallel to J _01. Transistor T _r0 then blocks again. The digital output signal is now 2 ² + 2 ¹ + 0 = 6. When the analog variable U _{A increases} to -0.7 V, transistor T _{r0 conducts} again, so that the L signal additionally emitted _{by a trigger stage T 0 corresponds to the bit} 2 ° the digital output signal ^{assumes the size 2 2} + 2 ¹ + 2 ° = 7.

An increase in the analog variable U _A to 0.8 V makes the transistor T _r3 conductive, the voltage divider resistor r _{3 of} which has the eighth part of the value of the resistor J _0-1 . The trigger stage emits an L signal according to bit 2 ³ . The output of the trigger stage T _{3 also} puts the resistor r _{08 in} parallel with the resistor J ₀₁ (ratio of the resistors 1: 8), J ₁₁₈ to T _{1 2} (ratio of the resistors 1: 4) and r ₂₈ to r _{2 4} (ratio of the Resistors 1: 2), so that the associated transistors T _r0 , T _rl and T _r2 block again. The disappearance of the L output of T ₂ and T ₁ causes the parallel _resistors r li4 and r _0A or r _{02 to be switched off} . The digital output signal is thus 2 ³ + 0 + 0 = 8. When the analog variable U _{A increases} to -0.9 V, T _r0 becomes conductive again, so that the digital output variable 2 ³ + 0 + 0 + 2 ° = 9. In IT ₄ = -1 V transistor T is conducting _rl0 whose voltage dividing resistor ^{r 1} io.io Ao r has the value of resistor _01, while resistor R has the same value as ₀₁₀ .R _{00th The trigger stage T 10} connected downstream of the transistor causes the parallel connection of the resistors r ₀₁₀ to r _{Oil (resistance ratio} 1:10), r lil0 to r ₁₂ (resistance ratio 1: 5), J ₂₁₀ to r ₂₄ (resistance ratio 4: 10) and r ₃₁₀ to r ₃₈ (resistance ratio 8:10). This means that the outputs of all trigger levels T ₀ .. .T ₃ become zero. As a result, the additional parallel resistances? ₀₂ , r _0A and r ₀₈ to r _oa , the parallel _resistors r iA and T _{1 8} to J ₁₂ and parallel _{resistor 28} to J _{24 are} switched off. '

When the analog value U _{A increases} to -1.1 V, transistor T _r0 becomes conductive again, when U _A = -1.2 V the transistor T _n , when U _A = -1.3 V both transistors T _r0 and T _{n are} conductive, and so on When the value U _A = - 2 V is reached, the parallel resistances 'Ίο, 2ο>' 3.20. »2.20. »Ί.20 and rp _{i20 switched on} by the trigger stage T _{20 of} the transistor T _r20 , because the transistor has a voltage divider _{resistance r 2020} of V20 of the resistor j ^- ₀₁ and is therefore conductive at twenty times the smallest unit of the analog value. When the value U _A = - 4 V is reached, transistor Γ _{ρ40 becomes} conductive, when U _A = - 8 V transistor T _r80 etc.

Instead of _assigning voltage divider resistors J ″ ₁₀₁₀ , J ₂₀₂₀ , J _40-40 to the transistors T _no , T _r20 , T r40 etc., which are 7io> ¹ Z ₂ O * ¹ Ao ^{etc. of} the value of r ₀₁ , the resistors can also according to powers of the number 2 of the value of r ₀ , so that these resistances are ¹ Z ₁₆ , ¹ Z ₃₂ , / ₆₄ etc. of the value of J _01. In this case, the trigger stage T ₁₀ controls the place value 2 ⁴ , Trigger level T ₂₀ the priority value 2 ⁵ , trigger level T ₄₀ the priority value 2 ⁶ , etc. The AD converter then does not code decimal-binary on the output side, but natural-binary.

The switches for switching the parallel resistors on and off can of course be used as contactless switches be trained. Switching transistors, for example, are suitable for this purpose.

Claims (4)

Patent claims: 1. Method for converting an analog value into a digital, preferably binary coded, static, parallel output signal in which the analog value is compared with a reference value is, characterized in that the analog voltage with the reference voltage each consisting of the same fixed resistors and of parallel evaluation resistors graded according to the powers of the number 2 a voltage divider assigned to a value is compared, that a comparison stage compares the voltage at the voltage divider tap with a fixed voltage (OV) and if they are equal, a trigger stage switches, which in turn is assigned to the lower values Evaluation resistors additional resistors each of the size of the comparison or. Evaluation resistors assigned to the trigger level switched in parallel. 2. The method according to claim 1, characterized in that with decimal binary coded output, the voltage dividers of the last four place values are followed by parallel voltage dividers with evaluation resistors (r _{10> 10} , r ₂₀₂₀ , J ₄₀₄₀ ), the size of which is V ₁₀ , V20. 740. ' · · · _{Of the evaluation resistor (r 01} ) of the last place value (2 °) and their assigned switching elements ( _{T,. 1O} , T r20, T _r40 , ...) when they are addressed to the evaluation resistors that are assigned to the places with lower exponents connect resistors in parallel with the size of the evaluation resistor assigned to the responsive switching element. 3. Circuit arrangement for performing the method according to claim 1 or 2, characterized in that contactless switches (transistors T _r0 ... T _r80 ) are provided as switching elements. 4. Circuit arrangement according to claim 3, characterized in that the transistors acting as contactless switches are followed by trigger stages (T ₀ ... T ₈₀ ) which emit both the signals associated with the assigned value of the digital output variable and the switching on and off of the evaluation resistors (r _O i ... r ₈₀₈₀₎ parallel auxiliary abutment projections (r _Oi2 ... r _{0) 80}
steer. »Ί.80. '2.4 '2.80 etc.) Considered publications:
Instruments and Automation, May 1956, p. 911 to 917; Proceedings of the IRE, August 1953, p. 1053 to 1058. 1 sheet of drawings 809 570/469 7.6 "& Bundesdruckerei Berlin