DE1242480B - Procedure and arrangement for centralized payment - Google Patents

Description

Method and arrangement for centralized enumeration The invention relates to a method for centralized counting, in which the data from different, cyclically queried encoders originate information in a common memory be recorded in which each encoder has a memory cell containing the counter reading is assigned, and at which the time interval between two consecutive Queries from the same encoder are less than the smallest occurring half-period of the alternating voltage signal supplied by the encoder, as well as an arrangement to carry out this procedure.

As is well known, the consumption of fluids is measured electricity etc. with the help of meters, and the transmission of the meter readings can be done by equipping these counters with electrical signal transmitters generally in the form of photoelectric or electromagnetic devices, which emit pulses, the number of which is proportional to the amount of fluid dispensed or of electric current.

There is already an arrangement with several inputs known that is intended to poll a certain number of pulse transmitters and cyclically to store the pulses from these different transmitters separately, whereby the duration of the cycle, d. H. the time interval between two consecutive ones Queries from the same sender, smaller than the time interval is measured, that can be between two consecutive pulses emitted by one of these Transmitters are generated. In practice this arrangement includes one for each transmitter storing input organ, a rotating switching device, which cyclically connects the input organs with an addition circuit, and a magnetic drum memory, in which a memory cell is assigned to each transmitter. The rotating switching device and the Magnettromrrielspeicher are synchronized so that during interrogation of the input organ of a transmitter, the content of the memory cell assigned to this transmitter is transferred to the addition circuit. If the input organ during the duration of the cycle has registered a pulse, the content of the addition circuit increased by one unit, and at the end of the polling this transmitter will be this Contents brought back into the corresponding memory cell of the memory.

This device has the disadvantage that as many storing Entrance organs must be pre-determined how transmitters are available so that it can be determined it can be determined whether a pulse is generated by the polled transmitter in the course of a cycle has been or not. The presence of these input organs causes on the one hand a considerable amount of equipment and, on the other hand, a limitation of the repetition frequency of the queries, thus also the number of transmitters, which in the course of a cycle can be queried one after the other without the subsequent period being greater than that Time interval between two consecutive pulses from the same transmitter will.

On the other hand, it is a device for recording the counter readings known from different remote counting points in a common control center, in which every meter is equipped with a complete counter and every one Counting roller of the counter is assigned a commutator that controls the position of the counting roller indicates. Each time the counter is queried, the positions of the commutators scanned one after the other with the help of a rotating selector, one after the other Pulse groups are generated which correspond to the position of the commutator in question Number of pulses included. In the center, these groups of impulses are assigned to the various Places fed to a recording device so that they display the count. The correct evaluation of the pulses is ensured that in the Headquarters a similar voter rotates synchronously with the voter at the counting point. at this known device is so each time a counting point is queried The complete meter reading is transmitted to the control center in the form of pulses. The one for this required effort is extremely large. For each counting point there is a with Commutator-equipped counter required as well as an encoder from a own synchronous motor is driven. A common drive for several encoders the same synchronous motor is only possible if the counting positions are the same Place. In addition, devices must be provided that enable synchronous start-up of the synchronous motor with the drive of the selector in the control center. This The entire effort is multiplied by the number of counting positions to be queried. Further polling all counting stations takes a long time because polling each individual counting point requires a complete cycle of the assigned Voter.

In contrast, the aim of the invention is to create a method of the type specified at the beginning, which is a continuous counting with little effort which enables quantities measured in any number of counting points.

According to the invention, this is achieved in that with each query of an encoder is the instantaneous value of the AC voltage signal supplied by the encoder is sampled that the sign of the sample with the sign of the previous query of the same encoder received sample is compared and that if the signs differ, the content of the one assigned to this encoder Storage cell is increased by one unit.

The inventive method is based on the principle that not at each time a counting point is queried, the complete count is transmitted to the control center is, but in the control center a continuous count of the continuously from each counting point transmitted information takes place. This information takes the form of AC voltage signals, whose number of periods is proportional to the changes in the measured value. At the counting point there is therefore no need for a counter at all, if not from others For reasons, a reading is also desirable there. Rather, it is sufficient to add the measuring mechanism Organ add an alternating voltage signal with the required property generated. This alternating voltage signal is continuously sent from each counting point to the control center transfer. There is a shared memory in the control center that is used for each The counting point to be queried has a memory cell that contains the relevant counter reading contains. It is therefore necessary with every change of the from a counting point incoming AC voltage signal to change the content of the assigned memory cell.

The method according to the invention is based on this principle from the following steps: 1. Each time an encoder is queried, the instantaneous value of the AC voltage signal supplied by the encoder is sampled, and the sign of the sampled instantaneous value is determined. Since it's only on the sign and does not depend on the absolute value of the instantaneous value, this sampling can can be done with very simple means and in a very short time. 2. That so stated The sign is obtained from the previous scan of the same encoder Signs compared. Of course, this assumes that what has been established in each case The sign is retained for the duration of a sampling period, what with a simple binary memory is easily possible.

3. If the comparison shows that the two signs compared are different, the content of the memory cell assigned to the relevant encoder becomes increased by one unit; if, on the other hand, the two compared signs are the same, nothing happens.

These simple process steps have the consequence that in each memory cell the change in sign of the AC voltage signal of the assigned encoder and thus the size represented by the number of periods of this alternating voltage signal continuously is counted. The number of encoders can be very large because the sampling time is very short is. The additional effort is practically limited to a sign memory per encoder, since the comparison circuit for the sign comparison is common to all encoders can be.

An arrangement for carrying out the method according to the invention with a clock that emits clock signals, a memory with one of the clock controlled address register, a selector and a write and read counting register, and with a channel selector, which is formed by input circuits, which with a Sampling flip-flop are connected to two stable states is characterized by that the address register of the memory is also the address register of the channel selector is, so that each input circuit assigned to a specific encoder is then unlocked and connected to the scan toggle circuit while the content of the same Encoder assigned memory cell is transferred to the counting register that a comparison circuit is provided with two inputs, which on the one hand with the scanning flip-flop and on the other hand with a special one that stores the sign of the last sample Flip circuit of the counting register are connected to the output of the comparison circuit is connected to the toggle of the least significant value in the count register and that a connection for transferring the contents of the scan toggle circuit to the there is a special toggle switch of the counting register.

The invention is illustrated below with reference to the drawings described. In it, F i g. 1 is a block diagram of a system according to the invention, F i g. 2 the connection between the input circuits and the sample flip-flop circuit, F i g. 3 shows an embodiment of the comparison circuits, FIG. 4 another embodiment the comparison circuits and F i g. 5 and 6 circuits for transmitting the information from memory to a numerical calculator or magnetic recorder.

The block diagram of the plant from FIG. 1 shows an oscillator 10, the output of which is connected to a ring counter 11; these two parts together form the clock which controls all operations of the arrangement. The counter 11 is designed as a time step counter so that it delivers a pulse with each counting step. The clock signals forming a pulse sequence are designated by V 1 to V $ for the case shown, in which the ring counter is constructed in eight stages, so that eight elementary times are determined for the sampling of an encoder. The sampling frequency, which is equal to the frequency of the oscillator 10 divided by eight, is selected as a function of the number n of transmitters so high that a cycle, ie the time interval between two successive samples of the same transmitter, is certainly less than the smallest half-period of the signal supplied by this encoder.

At El to E, r the various encoders are shown, their signals are fed to the corresponding input circuits, which will be described in more detail later will. These input circuits together form a channel selector 12, which each the encoder in turn with a scanning flip-flop circuit 13 with two stable states can connect.

The donors E, to E, t are designed so that they are continuous Supply alternating voltage signals, the periods of which reflect the changes in the periods to be counted Mark sizes. These AC voltage signals are rectangular in shape, that they have either a constant positive amplitude or a constant negative Have amplitude. Square-wave voltages of this type can be achieved, for example, by limiting the amplitude from alternating voltages which are proportional to the measured quantity by a tachometric alternating voltage generator or a similar device are generated, which is connected to the shaft of the measuring mechanism, its information should be registered.

The input circuits of the channel selector 12 are each connected to an address register 14 which supplies address signals N, N2 ... Nk ... N, Z, for example in binary form, which correspond to the number of the encoder and the number of which is at least equal to the number of encoders is. The incrementation of the addresses, which makes it possible to form the addresses of the n channels one after the other, which correspond to the n encoders El to En , takes place under the control of the first clock signal b;

The scanning flip-flop circuit 13 is used to determine the sign of the instantaneous value determine the alternating voltages of the selected encoder at the time of scanning, which is determined by the clock signal V3. At the end of the scan, the flip-flop reset to their reference state "0" by the clock signal V7. The toggle switch For example, 13 remains in the "0" state if the sampled signal is negative Has instantaneous value, and it goes into the at a positive instantaneous value State "1".

The address signals emitted by the address register 14 are also fed via a gate circuit controlled by the clock signal V2 to a memory selector 15 which is connected to the common memory 16, which is, for example, a ferrite ring core memory. In this memory, each encoder is assigned a memory cell that can store a binary number that contains a certain number, for example twelve binary digits, which in binary representation represents the number of half-waves (or periods) of the alternating voltage signals supplied by the corresponding encoder, as well as a special binary digit which represents the sign of the instantaneous value of the signal in the previous sample. A write and read counting register 17 enables the information contained in a memory cell with the address supplied by the address register 14 to be read at a time determined by the clock signal V2 and re-entered into the same memory cell at a time determined by the signal V6. This counting register 17 is designed as a counter so that its content can optionally be increased by one unit if the sign has been changed between two scans.

This change in sign is made with the aid of a comparison circuit 18 found, the inputs of which on the one hand with the scanning flip-flop 13 and on the other hand with the flip-flop 17A of the counting register 17, which is the same as in the preceding Sampling obtained signs are connected. The clock signal V4 causes possibly the addition of a unit to that contained in the counting register 17 Number. A connection between the scan toggle circuit 13 and the toggle circuit 17A of the counting register 17, in which a gate circuit controlled by the signal L; 19 enables the state of the scan toggle circuit 13 to be in the toggle circuit 17A must be entered so that the sign of the instantaneous value of the Signal is saved. A connection 20 enables those contained in memory 17 Information from the counting register 17 to an external organ, for example a numerical one Calculating device or a magnetic tape recorder, as explained later will.

The operation of this system then takes place under the control of the successive clock signals in the following way: At the beginning of a scanning cycle, the signal V, is applied to the address register 14, which advances by one unit and supplies an address signal Alk. As a result, on the one hand, the input circuit in the channel selector 12 is unlocked which is assigned to the transmitter Ek with the address Nk, and on the other hand, the output in the memory selector 15 which corresponds to the memory cell with the address Nx in the memory 16 is excited. Reading is triggered by the signal V, and the content of this memory cell is entered into the counting register 17. The signal Y3 then closes the input circuit of the scanning trigger circuit 13, which maintains the state "0" or assumes the state "1", depending on whether the sign of the instantaneous value of the signal from the EL- signal is negative or positive at that moment. The relevant state of the sampling flip-flop circuit 13 is compared with the state which it had assumed during the previous sampling of the signal from the same transmitter Ek, and which is stored by the state of the flip-flop circuit 17A of the counting register 17. This process takes place with the aid of the comparison circuit 18 at the point in time determined by the clock signal V4. If this state is the same, the sign of the instantaneous value has not changed between the two samples and the content of the counting register 17 is not changed. If there is an inequality between the two states, the sign of the signal has changed since the last sample. As a result, the comparison circuit 18 emits a signal which causes a unit to be added to the number contained in the counting register 17, whereby the half-waves of the signal from the encoder Ek are counted. The circuit of such a comparison circuit is shown in FIG. 3, but it is also possible to determine only the periods of the signal with the aid of the in FIG. 4 to count the comparison circuit shown.

The clock signal VS then unlocks the gate circuit 19 so that the current state of the sampling latch circuit 13 can be input into the latch circuit 17A of the counting register 17. The signal VB triggers the rewriting of the contents of the counting register 17 in the memory cell, the address Nk of which is still indicated by the memory selector 15. The clock signal V7 then resets the scanning flip-flop circuit 13 to its idle state “0” so that it is ready for scanning the following encoder.

Since the clock signal V8 indicates the end of the sampling cycle, a new Scan cycle analogous to that just described; However, since the address advances by one unit under the action of the clock signal V1 now the signal of the encoder Ek + l is sampled, and the content of the assigned to this encoder Memory cell is entered into the count register 17. Repeat the same process then, so that the signals of all encoders are scanned in sequence, and the number of their half-waves (or periods) recorded in the common memory 16 will.

F i g. 2 schematically shows the channel selector 12 with the input circuits 201, 202 ... 20k ... 20., The number of which is equal to the number of transmitters El to En . Such an input circuit 20k consists of an AND circuit, one input of which is intended to supply the signal from the corresponding transmitter Ex , while the other inputs receive the address signal Nk of this transmitter, which comes from the address register 14. The outputs of all input circuits are connected to one of the two inputs of a further AND circuit 22, which receives the clock signal V3 at its second input, which is the supply of the signal from the encoder , via a logic circuit 21, which performs the function "exclusively or" Ex to input "1" of the scanning flip-flop circuit 13 is allowed. This flip-flop is reset to its idle state "0" by the clock signal V7 fed to its other input.

3 shows a first embodiment of the comparison circuit 18 for counting the number of half-waves of the signal from an encoder, which amounts to that both the sign changes from "negative" to "positive" and the sign changes counted from "positive" to "negative". The outputs "0" and "1" of the sampling toggle switch 13 are connected to the corresponding inputs of the flip-flop 17A via an AND circuit 31 or 31 'with two inputs and an OR circuit 32 or 32' with two inputs tied together. The AND circuits 31 and 31 'are supplied to the second input by the Clock signal V5 unlocked. The OR circuit 32 receives the clock signal V7 that the Flip circuit 17A after the contents of the counting register 17 have been rewritten resets in the memory 16 to the state "0". The second OR circuit 32 ' receives the read signal i of that memory location at the time of the clock signal V2 in the selected memory cell of the memory 16, in which the sign of the last Sampling of the relevant encoder was stored, whereby the flip-flop 17A is brought back to the state which the registered letter in the course of the previous sampling cycle of the same encoder.

Furthermore, the output "0" of the sampling latch circuit 13 and the output "1" of the latch circuit 17A are connected to an AND circuit 33, which has a third input to which the clock signal V4 is fed, while the output "1" of the latch circuit 13 and the output "0" of the flip-flop 17A are connected to an AND circuit 33 'which has a third input to which the clock signal V4 is also fed. The outputs of the AND circuits 33 and 33 'are connected to the toggle circuit for the lowest place value in the counting register 17 via an “exclusively OR” circuit 34.

Thus, after the flip-flop 17A by the read signal at the time of the clock signal V9 brought into the state corresponding to the previous sampling has been, the scan latch circuit 13 assumes a state which corresponds to the sign corresponds to the instantaneous value of the signal from the encoder at the time of the clock signal V3. If an inequality between the states of the two flip-flops 13 and 17A exists when the state of the scanning flip-flop circuit 13 is opposite to its has changed the previous state shown by the flip-flop 17A one of the AND circuits 33 or 33 'unlocked by the clock signal V4, so that they transmits a pulse which is one unit for the number contained in the counting register 17 of half-waves.

F i g. Figure 4 shows a simplified embodiment of that previously described Circuit in which only the state changes of the sign in a be counted in a certain direction, for example from "positive" to "negative", which amounts to counting the number of periods of the signal. the Circuit corresponds to that of FIG. 3, but only output a0 « the sampling flip-flop 13 and the output "1" of the flip-flop 17A with the AND circuit 33 connected, while the flip-flop 33 'is omitted.

There must be the possibility of those recorded in the common memory 16 Counting information on a processing plant or on a buffer for to transfer a later use.

F i g. 5 shows a circuit with which such a transfer can be carried out. An auxiliary register 50 receives from the memory 16 via an AND circuit 54 controlled by the clock signal V2, the result of the count in the course of a sampling cycle of the signal from a transmitter. The twelve flip-flops of the auxiliary register 50, into which the twelve binary digits representing the count result are introduced, are connected to a corresponding number of AND circuits 511 to 5121, each of which has two further inputs, one of which is connected to a line 52 via which the read command is supplied from the external organ, while the other input receives the clock signal V3 or a subsequent clock signal up to the clock signal V6; these clock signals define the possible reading times. For the sake of standardizing the numerical characters, it may be useful to divide the reading into two stages, for example by adding the clock signal V3 to the six first AND circuits 511 to 51s and the clock signal V6 to the six last AND circuits 517 to 51,2 are fed. The outputs of the AND circuits 51 are connected to the input of the external organ 53.

If the external organ is a numerical computing device, the address will be of the encoder also communicated to the computing device. Coupling with different Types of computing devices will be examined sequentially below. In the case of an arithmetic device with fast cycle and automatic interruption calls an outside Clock in the arithmetic unit calls for the transmission of the counting results, and it calls periodically the interruption of the current program. The computing device waits to begin of a sampling cycle, and it reads each time the signal from an encoder is sampled the address of the encoder and the corresponding counting result. At the end of the scan of the signals from all encoders, the counting arrangement is separated from the computing device.

In the case of a fast cycle calculator with programmed interruption the computing device periodically checks a flip-flop circuit in the course of the program, which can be triggered by an external clock. If this toggle switch is in their working state, the computing device waits for the start of a sampling cycle and each time the signal from an encoder is scanned, it reads the address of the encoder and the corresponding count result. At the end of all scans, the computing device reset the flip-flop to zero to allow it to receive a new signal from the Clock is ready. Irri case of a computing device with a slow duty cycle, so that is not able to keep the count result during the duration of the scan To transmit an encoder, the computing device records the address of the encoder whose counting result is required in a register. At this moment, in which there is a coincidence between the recorded donor address and the address of the sampled encoder exists, the counting result is transferred to the auxiliary register 50. The computing device then has sufficient time to read this auxiliary register. As soon as this reading is taken, a new encoder address is recorded, and the same transfer process as before is repeated. In this case you have to the clock signals V3 and V6 are replaced by signals supplied by the computing device will.

If the counting arrangement is to be coupled to a magnetic tape recorder, the inertia of the recording device must be taken into account. F i g. Figure 6 shows a logic control circuit suitable for a device of this type. It is assumed that the time for starting the magnetic tape is equal to the time which elapses between the scanning of the encoder Ex and the scanning of the encoder E. An external command (which comes from a clock generator, a push button or the like) is fed to one input of a flip-flop 60. The corresponding output is connected via an AND circuit 63, which on the other hand receives a signal Sk from the channel with the number k assigned to the transmitter Ek, to the input of a flip-flop circuit 61, the output of which supplies the start-up signal for the magnetic recording device. The same signal is fed via an AND circuit 64 which, on the other hand, receives a signal S, from the channel with the number 1, to the input of a further flip-flop circuit 62, the output of which supplies the excitation signal for reading. This signal is also fed to an AND circuit 65, which receives the signal Sa. from the channel with the number n and the clock signal V7 assigned to this channel at two further inputs. The circuit 65 supplies the stop signal to the magnetic labeling device and triggers the resetting of the flip-flops 60, 61, 62 to zero.

If now the external command energizes the flip-flop 60 and the scanning arrives at the channel with the number k, the AND circuit 63 transmits a signal that the flip-flop 61 energizes and triggers the start of the magnetic tape. When the scanning arrives at the channel with the number 1, the magnetic tape has its nominal speed and the twelve digits of the recorded in the auxiliary register 50 (Fig. 5) The count results are output under the effect of the flip-flop 62 Signal read, for example in words of six binary digits each. Possibly it is possible with a parity checker to add a seventh control binary digit record the magnetic tape. The speed of the belt is such that the recording time of two words of six binary digits each (i.e. the count result) is equal to the duration of the scanning of an encoder. Thus after the scan is all Encoder recorded the entirety of the counting results on the magnetic tape on which they form a block. When the result of the last encoder has been read, the circuit 65 supplies a command for stopping the magnetic tape, and it resets the three flip-flops 60, 61, 62 of the control circuit to zero, so that they are ready for another recording.

Claims (9)

Claims: 1. Method for centralized counting, in which the information coming from different, cyclically queried encoders in one common memory are held, in which each encoder a counter reading containing memory cell is assigned, and in which the time interval between two consecutive inquiries from the same encoder smaller than the smallest is the half-period of the alternating voltage signal supplied by the encoder, d a d u r c h g e -k e n n n z e i c h n e t that every time an encoder is queried the instantaneous value of the alternating voltage signal supplied by the encoder is sampled that the sign of the sampler value with the sign of the previous one Query of the same encoder received sample is compared and that at a difference in the signs of the content of the memory cell assigned to this encoder is increased by one unit. 2. The method according to claim 1, characterized in that that the signals coming from the transmitters are square-wave AC voltage signals. 3. Arrangement for performing the method according to claim 1 or 2, with a clock that emits clock signals, a memory with an address register controlled by the clock, a selector and a write and read counting register and with a channel selector, which is formed by input circuits, which are connected to a scanning flip-flop circuit with two stable states, characterized in that the address register (14) of the memory (16) is at the same time the address register of the channel selector (12), so that each one assigned to a specific transmitter (El, EZ... En) Input circuit (201, 202 ... 20n) is then unlocked and connected to the scanning flip-flop (13), while the content of the memory cell assigned to the same transmitter is transferred to the counting register (17), so that a comparison circuit (18) with two inputs is provided is, which on the one hand with the scanning flip-flop (13) and on the other hand with a special one that stores the sign of the last scan Flip-flop (17A) of the counting register (17) are connected, that the output of the comparison circuit (18) is connected to the flip-flop circuit of the lowest value in the counting register (17) and that a connection for transmitting the contents of the scanning flip-flop (13) in the special flip-flop (17A) of the counting register (17). _ 4. Arrangement according to claim 3, characterized in that each input circuit of the channel selector contains an AND circuit (201, 202 ... 20n), the inputs of which on the one hand with the corresponding encoder (El, E2 ... En) and on the other hand with the Address register (14) are connected, and that the outputs of the AND circuits (201, 202 ... 20n) are connected to the scanning flip-flop (13) via an OR circuit (21) to which an AND circuit (22) follows, to which a clock signal (V3) can be fed. 5. Arrangement according to claim 3 or 4, characterized in that the comparison circuit (18) contains at least one AND circuit (33) with two inputs, which with the non-similar outputs of the scanning trigger circuit (13) and the special trigger circuit (17A) of the Counting register (17) are connected, that the output of the AND circuit (33) is connected to the flip-flop circuit of the lowest place value in the counting register (17), and that a clock signal (V4) can be fed to an additional input of the AND circuit (33) . 6. Arrangement according to one of claims 3 to 5, characterized in that for the transmission of the information contained in the common memory (16) to an external organ, a circuit is provided which contains an auxiliary register (50) into which the content of a memory cell is introduced can be, and that each of the flip-flops of the auxiliary register (50) is connected to the external organ (53) via an AND circuit (51, 512 ... 5112), which on the one hand receives the read signal (52) coming from outside and on the other hand Clock signal (V3, VB) can be supplied. 7. Arrangement according to claim 6, characterized in that that the AND circuits are divided into groups (511, 512 ... 51B; 51, ... 5112), to which various clock signals (V3, VB) can be fed. B. Arrangement according to claim 6 or 7, characterized in that in the event that the external organ (53) is a numerical arithmetic unit is, an interruption of the program flow by one of signal coming from outside can be brought about and that at the beginning of a sampling cycle the Calculating device the address of the encoder and the corresponding in the auxiliary register (50) reads the counting result introduced, if necessary after comparing the recorded ones Address with the address of the scanned encoder. 9. Arrangement according to claim 6 or 7, characterized in that in the event that the outer member (53) is a magnetic tape recorder, a circuit (60 to 65 in F i g. 6) is provided in which a coming from the outside Signal triggers the start of the magnetic tape and the reading of the auxiliary register (50) triggers with a certain delay, which is equal to the duration of a predetermined number of scanning cycles and corresponds to the time that the magnetic tape allows to reach its nominal speed. Publications considered: German Auslegeschriften No. 1045 287, 1 146 266.