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DE112006000497A5 - Mehrlagige Leiterplatte mit leitenden Testflächen sowie Verfahren zum Bestimmen eines Versatzes einer Innenlage - Google Patents

Mehrlagige Leiterplatte mit leitenden Testflächen sowie Verfahren zum Bestimmen eines Versatzes einer Innenlage Download PDF

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Publication number
DE112006000497A5
DE112006000497A5 DE112006000497T DE112006000497T DE112006000497A5 DE 112006000497 A5 DE112006000497 A5 DE 112006000497A5 DE 112006000497 T DE112006000497 T DE 112006000497T DE 112006000497 T DE112006000497 T DE 112006000497T DE 112006000497 A5 DE112006000497 A5 DE 112006000497A5
Authority
DE
Germany
Prior art keywords
offset
determining
circuit board
printed circuit
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE112006000497T
Other languages
English (en)
Other versions
DE112006000497B4 (de
Inventor
Arno Klamminger
Heinz Habenbacher
Wilhelm Lobner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&S Austria Technologie und Systemtechnik AG
Original Assignee
AT&S Austria Technologie und Systemtechnik AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S Austria Technologie und Systemtechnik AG filed Critical AT&S Austria Technologie und Systemtechnik AG
Publication of DE112006000497A5 publication Critical patent/DE112006000497A5/de
Application granted granted Critical
Publication of DE112006000497B4 publication Critical patent/DE112006000497B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE112006000497.2T 2005-03-01 2006-02-23 Mehrlagige Leiterplatte mit leitenden Testflächen sowie Verfahren zum Bestimmen eines Versatzes einer Innenlage Expired - Fee Related DE112006000497B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
ATA344/2005 2005-03-01
AT0034405A AT501513B1 (de) 2005-03-01 2005-03-01 Mehrlagige leiterplatte mit leitenden testflächen sowie verfahren zum bestimmen eines versatzes einer innenlage
PCT/AT2006/000078 WO2006091990A1 (de) 2005-03-01 2006-02-23 Mehrlagige leiterplatte mit leitenden testflächen sowie verfahren zum bestimmen eines versatzes einer innenlage

Publications (2)

Publication Number Publication Date
DE112006000497A5 true DE112006000497A5 (de) 2008-01-17
DE112006000497B4 DE112006000497B4 (de) 2015-07-16

Family

ID=36090933

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112006000497.2T Expired - Fee Related DE112006000497B4 (de) 2005-03-01 2006-02-23 Mehrlagige Leiterplatte mit leitenden Testflächen sowie Verfahren zum Bestimmen eines Versatzes einer Innenlage

Country Status (8)

Country Link
US (3) US20080190651A1 (de)
JP (1) JP4979597B2 (de)
KR (1) KR101234145B1 (de)
CN (1) CN101133689B (de)
AT (1) AT501513B1 (de)
CA (1) CA2600257A1 (de)
DE (1) DE112006000497B4 (de)
WO (1) WO2006091990A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY151594A (en) * 2007-02-08 2014-06-13 Sumitomo Bakelite Co Laminated body, circuit board including laminated body, semiconductor package and process for manufacturing laminated body
JP4912917B2 (ja) * 2007-02-22 2012-04-11 京セラ株式会社 回路基板、携帯電子機器及び回路基板の製造方法
CN102111961B (zh) * 2010-12-20 2012-11-14 胜宏电子（惠阳）有限公司 一种检测线路板内外层制程能力的方法
CN102072716B (zh) * 2010-12-21 2012-05-23 胜宏科技（惠州）有限公司 一种多层线路板层间和钻孔偏移检测方法
US20120212252A1 (en) * 2011-02-17 2012-08-23 Aronson Scott H Printed Circuit Board Registration Testing
US10687956B2 (en) 2014-06-17 2020-06-23 Titan Spine, Inc. Corpectomy implants with roughened bioactive lateral surfaces
AU2016355581B2 (en) 2015-11-20 2022-09-08 Titan Spine, Inc. Processes for additively manufacturing orthopedic implants
TWI726940B (zh) 2015-11-20 2021-05-11 美商泰坦脊柱股份有限公司 積層製造整形外科植入物之方法
WO2017192100A1 (en) * 2016-05-06 2017-11-09 National University Of Singapore A corrector structure and a method for correcting aberration of an annular focused charged-particle beam
US10893605B2 (en) 2019-05-28 2021-01-12 Seagate Technology Llc Textured test pads for printed circuit board testing
CN113513975B (zh) * 2020-04-10 2023-07-07 深南电路股份有限公司 印刷电路板及孔圆柱度测试方法
CN112198417A (zh) * 2020-09-30 2021-01-08 生益电子股份有限公司 一种过孔制作能力测试板及测试方法
KR20220169545A (ko) 2021-06-21 2022-12-28 삼성전자주식회사 인쇄 회로 기판 및 메모리 모듈
US11854915B2 (en) 2021-07-09 2023-12-26 Changxin Memory Technologies, Inc. Electrical test structure, semiconductor structure and electrical test method
CN115602663A (zh) * 2021-07-09 2023-01-13 长鑫存储技术有限公司（Cn） 电学测试结构、半导体结构及电学测试方法
CN114980528B (zh) * 2022-06-28 2024-12-24 生益电子股份有限公司 一种背钻对准度检测方法
CN117320329A (zh) * 2023-09-26 2023-12-29 江门全合精密电子有限公司 一种多层pcb板内层偏位的测试方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3045433A1 (de) * 1980-12-02 1982-07-01 Siemens AG, 1000 Berlin und 8000 München Mehrlagen-leiterplatte und verfahren zur ermittlung der ist-position innenliegender anschlussflaechen
JPS6453499A (en) * 1986-12-15 1989-03-01 Nec Corp Multilayer printed wiring board and inspection of same
US4918380A (en) * 1988-07-07 1990-04-17 Paur Tom R System for measuring misregistration
JP2890442B2 (ja) * 1989-02-27 1999-05-17 日本電気株式会社 半導体装置のコンタクトホールの目ずれ検査方法
JPH02246194A (ja) * 1989-03-17 1990-10-01 Fujitsu Ltd 多層プリント配線板
US4898636A (en) * 1989-05-04 1990-02-06 Rigling Walter S Multilayer printed wiring registration method and apparatus
GB2311618A (en) * 1996-03-27 1997-10-01 Motorola Ltd Determining layer registration in multi-layer circuit boards
JPH1154940A (ja) * 1997-08-05 1999-02-26 Fujitsu Ltd 多層配線基板のスルーホールの位置ずれ検査方法
JPH11145628A (ja) * 1997-11-05 1999-05-28 Toshiba Corp 印刷配線基板
US6103978A (en) * 1997-12-18 2000-08-15 Lucent Technologies Inc. Printed wiring board having inner test-layer for improved test probing
US6297458B1 (en) * 1999-04-14 2001-10-02 Dell Usa, L.P. Printed circuit board and method for evaluating the inner layer hole registration process capability of the printed circuit board manufacturing process
US6774640B2 (en) * 2002-08-20 2004-08-10 St Assembly Test Services Pte Ltd. Test coupon pattern design to control multilayer saw singulated plastic ball grid array substrate mis-registration
US7619434B1 (en) * 2004-12-01 2009-11-17 Cardiac Pacemakers, Inc. System for multiple layer printed circuit board misregistration testing

Also Published As

Publication number Publication date
US20140034368A1 (en) 2014-02-06
CN101133689B (zh) 2010-04-21
JP2008532295A (ja) 2008-08-14
AT501513A1 (de) 2006-09-15
CN101133689A (zh) 2008-02-27
AT501513B1 (de) 2007-06-15
DE112006000497B4 (de) 2015-07-16
CA2600257A1 (en) 2006-09-08
KR20070112826A (ko) 2007-11-27
US20080190651A1 (en) 2008-08-14
US20120125666A1 (en) 2012-05-24
WO2006091990A1 (de) 2006-09-08
KR101234145B1 (ko) 2013-02-18
JP4979597B2 (ja) 2012-07-18

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