DE1199322B - Electronic counting device with a static counter - Google Patents

Description

Electronic counting device with a static counter Electronic Counting methods have become more and more important in recent years. You will find in the entire measurement, control and regulation technology, in particular in digital technology in the incremental process (counting process), application.

Counters have the task of counting successive signals and to output the counting result at the outputs of the counting stages in parallel display.

The known electronic counters work mainly according to the dynamic principle. The individual counting levels of the dynamic counters consist of bistable multivibrators that are capacitively coupled. To control you have to Signals are used that reflect certain conditions, in particular with regard to Edge steepness, meet: The disadvantage of dynamic counters is the requirement according to specially shaped impulses in their sensitivity to external disturbances. Interference pulses can be evaluated like counting pulses and thus falsify the counting result.

The above disadvantages can be avoided to a large extent with counters that are based on work according to the static principle. Such static counters are each by one The step is adjusted when the amplitude of the counting signals exceeds a certain value; the shape of the signal edges is immaterial.

Static counters are known which consist of galvanically coupled, are constructed in a ratio of 2: 1 reducing counting levels. Such counting levels are also called binary levels. The first binary level is from the count signal and its negated form, the following stages each from the output signal of the previous one Stage controlled. This counter is thus an asynchronous counter that is subject to tilting of the individual stages takes place one after the other. The disadvantage of this known static Counter can be seen in the fact that the transition from one switching state to another does not take place safely (buttocks), rather the counting levels can be in a wrong Switching state fall.

A static counter has already been proposed to avoid the joints been, whose binary levels each consist of a counting memory and an assigned Auxiliary memories are built up and simultaneously by counting signals and auxiliary counting signals which are offset in time from one another (on a gap). The tilting of the individual binary levels is thus carried out synchronously with a central clock, so that the proposed counter represents a synchronous static counter. A synchronous one Counter is much more complicated to control than an asynchronous counter. The invention is therefore based on the asynchronous static described at the beginning Counters with galvanically coupled counting stages reducing in a ratio of 2: 1 (Binary levels), the first of which consists of the count signal and its negated form and the following stages are controlled by the output signal of the previous stage will.

According to the invention, the adverse effects of the joints this known counter avoided that the binary levels each from a the counting result of the respective binary digit, two complementary to each other Static counting memory and a assigned static auxiliary memory that prepares the actuation of the counting memory exist, which is deleted after the storage of the counting memory and its Control signal negated in each case to the control signal of the assigned counting memory is, and that the input of an integrating element, z. B. a capacitor is connected downstream.

The binary levels of the counter according to the invention are like that The proposed counter is made up of two storage elements, but the control takes place and the interconnection to a counting chain in a different way.

Further features of the invention and the advantages of the invention Counters result from the description of shown in the drawings Embodiments. It shows F i g. 1 an embodiment for a static bistable multivibrator, F i g. 1 a the short symbol for the circuit according to FIG. 1, Fig. 1 b shows a timing diagram for the circuit according to FIG. 1, Fig. 2 shows an exemplary embodiment for a binary level, FIG. 2 a is a timing diagram for Circuit according to FIG. 2, FIG. 2b the truth table for the circuit according to FIG. 2, F i g. 3 shows a timing diagram for the circuit according to FIG. 2, fig. 4 is a block diagram for an asynchronous counter, FIG. 5 shows an embodiment for the construction of the invention asynchronous counter, FIG. 6 a pulse pattern for the edge change in the case of two complementary ones Signals, F i g. 7 shows an exemplary embodiment for a binary level and FIG. 8 one asynchronous counter according to FIG. 5 with presetting.

The F i g. 4 shows a binary asynchronous counter in the block diagram. The counter consists of galvanically coupled counting levels, the binary levels, which are scaled down in a ratio of 2: 1. The first binary level is controlled by the counting signal (input EL) and its negated form (input Eo). The following binary levels are each controlled by the output signal of the previous level. The counter according to FIG. 4 is for example encoded in the natural binary code, also called dual code. A binary level is therefore provided for each binary digit. It is conceivable to use another binary code, e.g. B. od in Aikenkode. Like. To make. It can also be designed as a decimal counter (tetrads).

As the F i g. 4 shows is the main element of a counter the binary level on a binary basis. Before going into the counter in detail the structure of the binary levels should therefore first be described.

The basic building block of a static binary level is a static flip-flop. In FIG. 1 shows an advantageous exemplary embodiment for such a flip-flop. The flip-flop consists of a passive network and a downstream two-stage amplifier, which is made up of the transistors Tri, Tr2, the voltage divider resistors R1, R2 or R7, R8 and the load resistors R5, R6. The signal at the output A of the transistor Tr. Is complementary to the signal at the output 7f of the transistor Tri.

In the input circuit of the transistor of the first stage there is a passive OR gate with two inputs, which is formed by the diodes D5 and D. Each input of the OR element is controlled by a passive AND element with two inputs. One AND element, which has the inputs Ei and E2, is formed by the diodes D., D4 and the resistor R4. The other AND element, one input of which is designated Eo and the other input of which is controlled by the output of the transistor Tr2 (self-holding), consists of the diodes Dl> Dz and the resistor R3.

As is well known, the behavior of a flip-flop can be described by its memory effect. A flip-flop should therefore be viewed as a bistable memory element with two memory cells each. The F i g. 1 a shows the short symbol to be understood in the above sense for the circuit according to FIG. 1. With the aid of the pulse diagram according to FIG. 1 b can be the effect of the static flip-flop according to F i g. 1 or 1 a without further ado. The logic operation for the outputs is this: A = (Ei & D,) V (A & Eo); 1 - ( `V-'I r2) & (Ä- V E0).

The memory is set (saved) by applying »L« (-uB) to Ei and E2. The memory is cleared by applying "0" (0 volts) to E ,; "Save" dominates over "Delete". When saved, »L« appears at output A and »0« at output Ä.

Additional passive units can be connected to input e according to the input network whose inputs are disjunctive (OR) compared to the inputs Ei, E2 work. An additional reset input, decoupled via a diode D7, is included a denotes.

In the case of the dynamic principle, it is already possible to use two edges of a signal with a flip-flop one necessary for the binary representation Achieve 2: 1 reduction of the input signals. When applying the static principle However, two static flip-flops are necessary to build a binary level.

The F i g. FIG. 2 shows a new type of memory made up of two static memories according to FIG F i g. 1 a built-up static binary level, which is advantageous for realizing the Counting stages of the counter according to the invention is used. In principle, others can also Binary levels can be used to build the counter. Modifications to the Circuit according to FIG. 2 result z. B. when using memories which the delete input dominates over the memory input. It should also be mentioned that the binary level according to F i g. 2 can always be used when static Signals should be scaled down in a ratio of 2: 1.

Of the two memories of the binary level according to FIG. 2 is the memory SI the counting memory and the memory SII an auxiliary memory for the intermediate step. The auxiliary memory ensures that the counting memory has a ratio of 2: 1 stocky. The output signals of the auxiliary memory SII are opposite to those of the counting memory SI phase shifted by 90 °.

The binary level has two inputs EL and Eo, of which the input EL with the signal Q (counting signal) to be reduced and the input E with a complementary signal (D).

At output A, the memory output of the counting memory SI, the reduced Signal 4 @, a complementary signal 0 taken from output Ä of the counting memory. These signals are used to control downstream stages.

As the F i g. 2 shows, the counting input EL is connected to the memory input E2 of the counting memory S and to the clearing input E of the auxiliary memory SII. The second memory input Ei of the counting memory is controlled by the output A * of the auxiliary memory. The counting memory can therefore only be saved if SII is also saved. However, as will be shown, the auxiliary memory is only in the memory position after every second counting signal.

The input En of the binary level is connected to the one memory input El of the auxiliary memory SII and the clear input En of the counter memory S connected. Of the The second memory input E2 of the auxiliary memory is taken from output; 1 of the counter memory prepared. The auxiliary memory can therefore only be saved if the Counting memory is cleared.

The input Lö is used to delete the binary level.

The mode of operation of the binary level according to FIG. 2 arises without further ado taking into account the timing diagram according to FIG. 2 a or the truth table according to FIG. 2 B.

Before the first counting signal, EL = "0" and En = "L" and Ä = "L". The binary stage is in the initial position, in which A = "0" and Ä = "L", the auxiliary memory S, 1 is in the memory position, ie A * = "L". (Although "0" is present at the clear input En of the auxiliary memory, ie a clear signal; but since "Save" dominates over "Clear" in this exemplary embodiment, SII is not cleared.) As a result, however, the counter memory SI is prepared via input Ei in such a way that it is saved with the first counting signal (EL = "L" and En = "0"), ie A = "L" and Ä = "0". Because of the Ä = "0", the auxiliary memory now lacks an AND condition, so that when the first count signal disappears, it is deleted because EL = "0" (A * = 0). Because A * = "0", the counting memory SI now also lacks an AND condition, so that it is deleted with the second counting signal (EL = "L" and En = "0") because Eo = "0" (A = "0 «And Ä = » L «). This ends the first cycle. If the second counting signal disappears, SII is stored because En = "L" and Ä = "L" and prepares SI for storage by the third counting signal.

The circuit according to FIG. 2 thus acts in such a way that it emits a signal with the first counting signal (A = "L"), which disappears again due to the second counting signal (A = "0") and reappears due to the third counting signal. It thus results in a 2: 1 reduction of the counting signals, since an output signal occurs only for every second input signal.

The binary level according to FIG. 2 can be used with advantage to build a static Counter according to FIG. 4 can be used. The F i g. 5 shows such an embodiment of the static counter according to the invention. The memories of the binary levels can thereby according to FIG. 1 be realized. The structure of the counter according to FIG. 5 is so hit that in the first stage of the counting memory S, from the counting signal (input EL) and the Auxiliary memory SII is controlled by the negated counting signal (input En). In the The following stages are each an AND input of the counting memory with the output Ä of the counting memory of the previous stage and an AND input of the auxiliary memory connected to the output A of the counting memory of the previous stage. Basically Binary levels can also be used, in which the interconnection of the memory is made in a different way.

The counter according to FIG. 5, constructed with memories according to FIG. 1, only works reliably under certain temporal conditions between the output signals (A *, A, Ä) and input signals (EL, En) of the binary levels. The timing diagram according to FIG. 1 serves to explain these conditions. 3. The circled numbers on the left edge of FIG. 3, ie the individual pulse patterns, relate to the correspondingly designated circuit points in FIG. 2.

In this context, four states of the pulse diagram are of interest. They are labeled ®, ®, and OD.

Let us first consider the state ®. It is assumed that the control of the first stage takes place ideally, ie the edge change at 1) and (2) takes place at the same time with any steepness. At the AND input Ei of the auxiliary storage, the change from "L" to "0" starts (D removes the storage condition, while at the delete input E, of the auxiliary storage, the erase condition is simultaneously activated by changing from "0" to "L" at Q) ceases to exist. If the edges are smoothed so that the "0" signal at (D takes effect earlier than the "L" signal at. (2), the auxiliary memory does not remain in its position a certain response threshold, which is close to the "0" signal (less than 5001o of the "L" signal), the auxiliary memory remains in its position despite the "smoothed" edges, since the "L" takes effect earlier than the "0" takes effect at one of its memory inputs Ei (1G).

On point (CD: The auxiliary memory is deleted because it is at its delete input En (2) a »0« appears and the second memory input E2 (S) is already »0«. The same applies to the counting memory as was said for state #a of the auxiliary memory became.

Regarding point (2): The auxiliary storage unit clearly tilts, since there is “L” at its first storage input Ei through 0 and at the second storage input E2 through (3). The counting memory cannot yet tilt in the desired manner, since at (3) , ie at its first memory input Ei only after the time zII (switching time of the auxiliary memory) an "L" appears, up to this point in time with certainty at its second memory input E2 (ƒ) a »0« is pending.

Regarding point @p: The counting memory is to be deleted, which is clearly done by the "0" at the delete input En (D). The auxiliary memory is not stored in the desired way, because the "L" at its memory input EL (0) only appears after z1 (switching time of the counting memory), while by then a "0" is already at its other memory input Ei (D).

In summary, the following can be stated for points U to: With ® and ƒ, the status of the changes already saved during these changes Memory obtained by setting the input response threshold ("L") according to a feature of the invention is closer to the "0" signal than to the "L" signal. At 0 and OD the storage of the memory that is not to be set is due to the available switching time (Tipping time zI, zII) prevented.

The previous considerations were based on the assumption that the edge change takes place essentially simultaneously. This condition is in not guaranteed in practice with the current resources. The control of the Counter is done with a view to on the two mutually antivalent Input signals expediently through a trigger with two mutually antivalent Outputs. However, this trigger and also the binary levels overlap the two flanks of the equivalent and non-equivalent output, since the equivalent output is faster than the complementary one. In addition, as a result of the different Time constants the transition of an output from "L" to "0" is faster than that Transition from "0" to "L" (if "L" is the output signal with the transistor saved is equivalent to).

The practical conditions are shown in FIG. 6, in which the state changes of outputs A and A are shown. The dashed area, the so-called Butt joint, is quite undefined for the input of the binary level. Around these joints to avoid, are offset against each other in time in the proposed counter Clocks used for control. According to the invention, the effects of this Joints avoided in a simple manner that both memories of the binary level the input logic (input gate) an integrating element, e.g. B. a capacitor, is downstream. A counter according to FIG. 5 with memories designed in this way works reliably.

The above measure is based on FIG. 7 explained in more detail, in which an embodiment of a built with memories in the above sense Binary stage, which is advantageous for the construction of the embodiment of the invention Counter according to FIG. 5 can be used, is shown in detail. In the F i g. 7 are, for example, two memories according to FIG. 1 shown, for example according to FIG. 2 and 5 are interconnected. The same components are with the same Reference numerals have been designated. The elements of the counting memory SI are for differentiation provided with a line opposite the elements of the auxiliary memory SII.

Compared to the memory according to FIG. 1 are stored in the F i g. 7 the integrating capacitors C1 and Ci are also provided. Through this Capacitors are the signals effective at the base of the transistors Tri and Tri »Smoothed« in order to obtain defined ratios for the basic inputs of the memory. (The control of the first stage is expediently carried out by a trigger, by about to get the same changes in state.) The integrating smoothing capacitors C1 and C; make the input slower than the output after the logical connection the previous stage. This avoids the effects of the joints.

Another advantage of the capacitors is that you get the cutoff frequency the counting stage by increasing the capacitance of the capacitors in the sense of a real one Reduce the cut-off frequency reduction in order to suppress higher-frequency interference pulses, which can occur on the lines.

It should also be emphasized that the resistances in the input circuit of the Transistors Tr, or Tri 'are dimensioned so that they can be used for charging and the discharge of the capacitors result in approximately the same time constants.

Instead of a capacitor, the dual switching element, an inductance connected in series with R2 or Rz can be used. The measure with the integrating smoothing capacitors is not on the embodiment according to FIG. 7 limited. It can also be used for differently structured binary levels Find.

In summary, the following can be said of the previous: The F i g. 5 shows an embodiment of the counter according to the invention, in which the Binary levels with regard to the interconnection of the counter and auxiliary memory a specific example, namely according to the circuit of FIG. 2 or 7 built up are. There are also other ways of interconnecting the two memories conceivable to a binary level.

In the way the two interconnected in a certain way Memory are implemented in detail, there are further embodiments of the binary level or of the counter according to the invention. So z. B. the memory according to FIG. 1 are used to build the binary levels. However, the Memory according to FIG. 1 in the manner shown in FIG. 7 shown is.

The counter according to the invention can be preset to a specific number in a simple manner. This should be based on FIG. 8 are explained in more detail, which relate to a counter according to FIG. 5 refers in a simplified representation. For presetting, as shown in FIG. 8 shows that a special input V is provided both on the counting memory and on the auxiliary memory, which is actuated by presetting switches VS " VS2, VS3 ... The presetting input V is, as FIG. 7 shows, in a memory according to FIG g.1 a third OR input, which is formed by the diodes D8 and D8. It is also possible, for example, for the purpose of evaluating in a different code, to make the presetting on the transistor Tr2 or Tr '. For this purpose, diodes are connected in front of the resistor R $ or R, which decouple the preset input from the connection to the transistor Tri or Tri.

To preset a certain binary number, the binary levels, which are assigned to the "L" values of this number, as well as the counting memory as well as the auxiliary storage tank briefly acted upon by the "L" signal.

For example, the number 3 should be preset. The binary number for 3 is: 3 = LL 0, that is, A1 (20) and A2 (21) must be L and A3 (22) = 0. The scheme of the six stores for the number 3 looks like this: A 1 A 1 * A 2 A 2 * A s A s * 0 = 0 0 0 0 0 0 1 = LL 0 L 0 0 2 = 0 0 LL 0 L 3 --- LLL 0 0 L To preset the number 3, ie to achieve the above pattern, the preset lines of stages 20 and 21 are now briefly connected to the "L" signal. When the preset signal is applied, the memories of the first two stages inevitably tilt, ie A1 = L, A1 * = L, AZ = L and AZ * = L.

As a result of A2 = L and Ä2 = 0, the third stage (22) tilts into position A * 3 = L (A3 remains "0"). So everything is correct except for output A2 *, which must be "0" according to the above pattern.

This output becomes "0" as desired, ie the auxiliary memory of the second stage flips back when the preset signal is removed. The tilting back occurs because (see Fig. 5) only one AND input through A. @ 1. = L occupied and the other AND input is not prepared because of A2 - = L. Since 7 = 0, the auxiliary memory SII of the second stage is deleted again. This internal mechanism always works, so that, just like with dynamic binary counters, the individual stages, e.g. B. can be preset using coded switches.

Embodiments of counters are described above that are binary counters. They can easily be modified to that they work as decimal counters. Since each counting stage can assume two states, At least four counting levels per decade are required for the decimal counter. from the sixteen possible combinations that four binary counting levels can output, only ten are used. Six counting positions must therefore be skipped, which is achieved through feedback or through appropriate decryption matrices can be. The choice of which initial combinations should not occur is made such that the switching functions for the decimal counter are as simple as possible result. In this respect, a counter that can do this Outputs the counting result as a dual-encrypted decimal number.

For certain applications, counters must be provided by where one part counts forwards and another part counts backwards. The inventive Counter can be designed in a simple manner so that it counts backwards. this takes place in a known manner by a complementary evaluation of the outputs, the for this purpose z. B. are encrypted according to the 3-excess code.

The advantages of the static counter according to the invention over known ones static counters can be seen in the following: 1. The presetting of the counting levels is very simple, e.g. B. possible with coded switches. There is no extra effort necessary compared to dynamic meters.

2. The control and the structure are very simple.

3. All binary levels are in the same way; built.

4. The smoothing capacitors reduce the impact of the joints avoided. It is thereby the construction of a reliably working asynchronous counter possible. ;

Claims (7)

Claims: 1. Electronic counting device with a static Counters with galvanically coupled counting levels (binary levels) reducing in a ratio of 2: 1, of which the first stage consists of the count signal and its negated form and the following Stages are each driven by the output signal of the previous stage, d a d u r c h indicated that the binary levels each consist of a counting result of the respective binary digit, two complementary control signals static counting memory (SI) delivering the next stage and an assigned, the actuation. static auxiliary memory (S1,) that prepares the counting memory exist, which is deleted after the storage of the counting memory and its. Control signal negated in each case to the control signal of the assigned counting memory is, and that the input of an integrating element, z. B. a capacitor (Ci, C, "), is connected downstream. 2. Counter according to claim 1, characterized characterized in that both the counting memory and the auxiliary memory are at least two AND-linked memory inputs activated by an "L" signal and at least one reset input activated by a "0" signal and two mutually antivalent ones Outputs (memory output A, delete output Ä) has (Fig. 1 a). 3. Counter according to claim 2, characterized in that the memory contains a two-stage amplifier constructed from transistors (Tri and Tr2), wherein in the input circuit of the transistor of the first stage, a passive OR gate (D5, DE) is connected, the two Has inputs that are each controlled by a passive AND element with two inputs (D1, D2; D3, D4), the inputs of one AND element (D3, D4) from the two memory input signals (Ei, E2) and the Inputs of the other AND element (Di, D2) are controlled by the clear signal (E.) and the return of the output (A) of the transistor (Tr2) of the second stage to the input (self-holding) (FIG. 1). 4. Counter according to claim 3, characterized characterized in that an integrating capacitor is connected behind the OR gate is (Fig. 7) - 5. Counter according to claim 3 or 4, characterized in that for Presetting of the memory in the input circuit of the transistor of the first stage third, externally controllable OR input (D8) is provided (FIG. 7). 6th Counter according to Claim 2 or one of the following with memories, in which the memory input is dominant over the erase input, characterized in that to form a Binary level of the memory output of the auxiliary memory (SII) to an AND input of the Counting memory (S1) and the clear output of the counting memory to an AND input of the auxiliary memory is switched, once the clear input of the auxiliary memory is connected to the second AND input of the counting memory, which is an input of the Binary level, the counter input, and on the other hand the clear input of the counting memory is connected to the second AND input of the auxiliary memory, which is assigned to a second input of the binary level, the auxiliary input (F i G. 2). 7. Counter according to claim 6, characterized in that the counting input and the auxiliary input are acted upon by two mutually complementary signals, the counting input in the case of the first stage from the counting signal, in the case of the following stages from the clearing output signal of the counting memory of the preceding binary stage and the auxiliary input in the case of the first stage from the negated counting signal, in the case of the following 5096581437 stages from the memory output signal of the counting memory of the previous stage (FIG. 5). B. Counter according to Claim 1 or one of the following, in particular Claim 5, characterized in that, with the presetting of a binary number in the binary levels assigned to the "L" values of this number, both the counting memories and the auxiliary memories are briefly marked with "L «Signal are applied (Fig. 8).