DE1178114B - Semiconductor arrangement according to compact technology, especially for shift registers, counters or memories - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Boarding school Kl: H 03 k

German class: 21 al -36/18

Number: 1178 114

File number: J 21046 VIII a / 21 al

Filing date: December 19, 1961

Opening day: September 17, 1964

The invention relates to semiconductor arrangements according to compact technology, which are made up of several of the same type built, bistable switching stages exist and in particular for shift registers, counters or Memory can be used.

It is known from the prior art to place several metallic, punctiform on a semiconductor carrier Apply electrodes, for example by soldering. Obtained by such an arrangement one has several non-linear elements, e.g. B. Diodes. If one wants to be spatially united with one of these Group of non-linear elements to build a circuit arrangement, so you have to use the coupling elements between the individual stages and to the inputs / outputs of the circuit arrangement as well as the Switching elements that make the connection to the power source, in the usual technology around the group of arrange non-linear elements.

With the invention, this disadvantage is now avoided and a circuit arrangement is specified, which can be economically produced in large quantities.

The invention thus relates to a semiconductor arrangement according to the compact technology, which consists of several identically structured bistable switching stages, for shift registers, counters, memories or the like, with a mounted on a conductive base plate, semiconducting layer and with point-like or area-like so applied to the semiconducting layer Electrodes that result in non-linear elements at the transition points. She is through it characterized in that a resistance layer is applied to the semiconducting layer, on the one hand with the electrodes and on the other hand with connecting conductor strips is connected, and that the resistance layer is spatially formed so that the working and coupling resistances of the individual stages result.

The conductive layer can correspond to the desired resistance values of the current paths in the be carried out in a suitable form.

According to a development of the invention, the semiconducting compounds can be used as Tunnel diodes can be designed and used as individual storage elements of a storage arrangement, the current paths of the conductive Layer are used for writing and reading information from the individual memory cells can.

Further developments of the invention are the dependent claims in connection with the figures and refer to the description of the figures.

Semiconductor arrangement according to compact technology,
especially for shift registers, counters or
Storage

Applicant:

International Standard Electric Corporation,

New York, N.Y. (V. St. A.)

Representative:

Dipl.-Ing. H. Ciaessen, patent attorney,

Stuttgart W, Rotebühlstr. 70

Named as inventor:

Arthur Edward Brewster, London

Claimed priority:
Great Britain 23 December 1960 (44 297)

The invention will now be described with reference to FIGS. 1 to 4, for example, explained in more detail. It shows

F i g. 1 shows a longitudinal section through the semiconductor arrangement according to the invention,

F i g. 2 shows a plan view of this semiconductor arrangement,

3u Fig. 3 is an equivalent circuit diagram of the semiconductor arrangement,

4 shows the characteristic curve of one of the semiconductor elements used.

The in the F i g. 1 and 2 shown semiconductor arrangement consists of a plurality of interconnected semiconductor elements, which result in a unit module of any length. This unitary component consists of a semiconductor body 10 soldered onto a base plate 11 , which base plate 11 is simultaneously connected to an electrical connection line 12, a multiplicity of semiconductor compounds which are formed on the surface of the semiconductor body 10 by diffusion or alloying of metal beads 13 , and also of a profiled conductor strip 14 with low, but finite resistance. The conductor strip 14 is connected to each of the metal beads 13 by soldering or some other suitable process, and the upper surface of this conductor body 14 is provided with a transverse groove to provide a relatively thin connection path 15 between each pair of adjacent semiconductor compounds.

409 687/273

to manufacture genes. Between each section of the conductor body 14 are on the semiconductor body remote side ohmic connections 16 to each of the three conductor strips 17 are present.

The spaces between this structural unit are completely filled by insulating layers 18 and 19, whereby a solid construction in the form of a continuous strip of any length is ensured.

The semiconductor connections that exist between the semiconductor body 10 and the parts 13 have the characteristics of the already known tunnel diodes.

The equivalent circuit diagram of such a unit is shown in FIG. 3. The structural unit consists of the stages Ji, B, C, D and E of a shift register known per se for storing digital information. Each stage of this register consists of a tunnel diode 20, in series with a working resistor 21. The connection between two adjacent elements is made by a coupling resistor 22, and a further resistor 23 connects the first stage to the input line 24.

It can be seen that the semiconductor connections between the beads 13 and the semiconductor body 10 (Fig. 1 and 2) correspond to the tunnel diodes 20 (Fig. 3), while the resistors 22, which connect two adjacent steps to one another, through the narrow connecting path 15 of the conductor body 14 are shaped. The load resistors 21 are formed by the parts of the conductor body 14, which lie between the metal beads 13 and the ohmic connection points 16. The input line 24 of the assembly is connected to one end of the conductor body 14, and the first narrow connection path 15a corresponds to the coupling resistance at the input 23. The metal strip 12 (FIG. 1) corresponds the common return line 12 in Fig. 3. The three conductor strips 17 supply the individual Steps with clock pulses.

For the functional description of the circuit arrangement, the characteristic curve diagram in FIG. 4 included. The curve 25 corresponds to the characteristic curve of one of the tunnel diodes 20, with the load resistance at the same time is shown as a resistance line 26. There are two stable working points 27 and 28 possible, the applied voltage between the diode and the load resistor depending on Working point is divided differently. These two stable positions can be used by the two digital ones To display values »0« and »1«.

If a voltage ν is now fed to the first stage A of the register via the clock line 17, the operating point of the first stage will be set at point 27. However, if a positive voltage pulse is applied to the input line 24 at the same time, the stage is switched to its second operating point 28. The stage can be reset, either by a negative voltage on the input line 24 or by the fact that the voltage ν on the clock line is switched off.

If, while the stage of the register is at point 28, a voltage pulse ν is applied to the second stage B on one of the clock lines 17, this stage will assume the same position as the stage, so that the first can then be reset. A stored bit can thus be shifted from level to level in the register in this way.

To ensure that the information in the register is only shifted in one direction and In order that no message is lost, it is necessary to provide three levels for each information bit. The steps are grouped together, and every third step is connected to the same conductor 17.

The operation of the register depends on how the clock lines 17 are energized. Are z. B. the lines 17 are fed with a series of voltage pulses, each of the pulses in a Line overlaps the pulse in the previous line, the information becomes continuous advanced in the register. The output of the register can then be connected to the input of the Registers to be connected in order to achieve a permanent circulation of the information. The structural unit however, it can also be used as a simple delay line of a certain capacity.

In order to achieve maximum flexibility in the production of the resistance values of the load and coupling resistors 21, 22 and 23 (Fig. 3), the electrically conductive layer 14 is expediently in the one shown in FIG. 1 executed form. However, it is also possible without departing from the basic principle of the invention to remove the conductive layer 14 as a uniform band, then the resistors 21, 22 and 23 are no longer recognizable as individual resistances, but as meshed ones Current paths that lead over resistance strips of various lengths. In this modified Form, this unit is built up only from evenly extending layers, so that a production is possible through a continuously running, possibly even automatic process.

Claims (7)

Patent claims: 1. Semiconductor arrangement according to compact technology, which consists of several similarly constructed bistable switching stages, in particular for shift registers, counters or memories, with a applied to a conductive base plate, semiconducting layer and with on the semiconducting Layer so applied point or flat electrodes that are at the transition points nonlinear elements result from this characterized in that a resistive layer (14) is applied to the semiconducting layer (10) is, on the one hand with the electrodes (13) and on the other hand with connecting conductor strips (17) is connected, and that the resistance layer (14) is spatially designed so that the working and coupling resistances (21 or 22 and 23) of the individual stages. 2. Semiconductor arrangement according to claim 1, characterized in that on the electrically conductive Layer (14) at least one conductor strip (17) is applied, but only on one or several specific points (16) is connected to the conductive layer (14). 3. Semiconductor arrangement according to claims 1 or 2, characterized in that the electrically conductive layer (14) corresponding to the desired resistance values of the current paths is shaped. 4. Electronic memory device using a semiconductor device according to a or more of Claims 1 to 3, characterized in that the semiconducting compounds individual storage elements of the storage arrangement and the conductive layer (14) current paths represent for the writing and reading of information of the individual memory cells. 5. Electronic memory arrangement according to claim 4, characterized in that this as Shift register is formed. 6. Electronic memory arrangement according to claim 5, characterized in that the with the semiconductor body (10) the semiconducting connections forming metal beads (13) on the one hand Via first current paths and connection points (16) with the conductor strips (17), which clock pulses for the individual storage elements can be supplied, are connected, and that the metal beads (13) on the other hand, for coupling the individual stages to one another, via second current paths (15) are interconnected, the first and second current paths from the conductive Layer (14) are formed. 7. Electronic memory arrangement according to claim 6, characterized in that the bisecting connections existing between the semiconductor body (10) and the metal beads (13) are designed as tunnel diodes. Considered publications:
British Patent No. 654 909. Legacy Patents Considered:
German Patent No. 1137 070. 1 sheet of drawings 499 687/273 9. 64 ι Bundesdruckerei Berlin