DE10241812A1 - Cell element field for processing data has function cells for carrying out algebraic/logical functions and memory cells for receiving, storing and distributing data. - Google Patents

Abstract

A cell element field (CEF) (0101) processes data. Function cells (0102) operate arithmetic/logical functions. Memory cells (0103) receive, store and distribute data. The function cells regulate a control link (0104) to the memory cells. Networking the elements can configure the CEF. Links can be configured when bus systems (0105) are connected as required. Independent claims are also included for a method for operating a multi-dimensional cell element field with function cells for algebraic/logical functions and input/output memory cells for making data available and for a data-processing configuration with a multi-dimensional field.

Description

The present invention relates to a cell element array and a method of operating the same. In order to deals the present invention in particular with reconfigurable Computing architectures.

Under a reconfigurable architecture u. a. Modules (VPU) understood that a variety in function and / or networking have variable elements in operation. To the elements can arithmetic logic units, FPGA areas, input / output cells, Memory cells, analog modules, etc. belong. Building blocks of this type are, for example known as VPU. This typically includes PREs arithmetic and / or logical arranged in one or more dimensions and / or analog and / or storing and / or networking modules and / or communicative peripheral assemblies (IO), directly or through a or several bus systems are connected to each other. The PAEs are arranged in any configuration, mix and hierarchy, the arrangement being referred to as a PAE array or PA for short. A configuration unit can be assigned to the PAE array. In addition to VPU building blocks, systolic arrays are basically neuronal Networks, multiprocessor systems, processors with several arithmetic units and / or logical cells, networking and network components such as Crossbar circuit etc. known, as well as FPGAs, DPGAs, transputers etc.

It is pointed out that essential aspects of VPU technology are described in the following property rights of the same applicant and the associated subsequent applications for the property rights listed: P 44 16 881.0 -53, DE 197 81 412.3 . DE 197 81 483.2 . DE 196 54 846.2 -53, DE 196 54 593.5 -53, DE 197 04 044.6 -53, DE 198 80 129.7 . DE 198 61 088.2 -53, DE 199 80 312.9 , PCT / DE 00/01869, DE 100 36 627.9 -33, DE 100 28 397.7 . DE 101 10 530.4 . DE 101 11 014.6 , PCT / EP 00/10516, EP 01 102 674.7 . DE 102 06 856.9 , 60 / 317,876, DE 102 02 044.2 . DE 101 29 237.6 -53, DE 101 39 170.6 ,

It should be noted that the aforementioned Documents for disclosure purposes, particularly with regard to special features and details of networking, configuration, design of architectural elements, Trigger procedures etc. are integrated.

The architecture has considerable advantages across from usual Processor architectures, as far as data processing in one Way takes place, the high proportions of parallel and / or vectorial Owns data processing steps. The advantages of architecture across from other processor, coprocessor or generally data processing units however, will decrease if the benefits of networking and the given processor-architectural peculiarities no longer in can be realized in full.

This is especially the case when data processing steps are to be processed, which are conventionally on can best be mapped onto sequencer structures. It is desirable to design and use the reconfigurable architecture in such a way that too data processing steps that are typically particularly easy to process with sequencers can be processed particularly quickly and efficiently.

The object of the present invention is new for to provide the commercial application.

The solution to this problem is claimed independently. Preferred embodiments can be found in the subclaims.

According to a first essential Aspect of the invention is thus in function and / or networking not reconfigured especially at runtime without disruption Elements reconfigurable cell element field for data processing with function cells for execution algebraic and / or logical, configurable functions and memory cells, to receive, save and / or output information suggested that a Control connection from the functional cells to the memory cells. This control connection serves the purpose of address and / or data input / output from the memory through the assigned function cell, typically one ALU-PAE, to make it controllable. For example, you can specify whether the next broadcast Information should be treated as an address or as data and whether read and / or write access is required. These dates from the memory cell, which is, for example, a RAM-PAE on the ALU-PAE can then allow new commands to be processed by the ALU can be loaded into it. It is possible in this way only by providing a dedicated and dedicated function cell controlled Control connection between function cell and memory cell already with just two elements over it suitable buses are connected, a sequencer structure in one To build up cell element field without any further measures and / or structural changes required are. Data, addresses, program steps can be stored in the memory cell etc. in conventional per se Processors are stored in a known manner. Because both elements can also be used in another way with the appropriate configuration are a particularly efficient design, both Sequencer structures as well as vectorial and / or parallelisable Structures particularly adaptable is.

It is clear that by using only two cells in a cell element field, namely the functional cell and the information supply cell, a large number of sequencer-like structures in the reconfigurable cell element field can be built. This is advantageous in that a number of tasks that are different and different from one another per se must often be processed in data processing, for example in a multitasking operating system. A large number of such tasks can then be effectively processed simultaneously in a single cell element field. The advantages for real-time applications are obvious. Furthermore, it is also possible to operate the individual sequencer structures, which are set up in a cell element field with the control connection according to the invention, at different clock rates, for example in order to reduce the power consumption in that tasks with a lower priority are processed more slowly. It is also possible to execute sequencer-like program parts in the field in parallel or vectorially when executing largely parallel algorithms per se and vice versa.

The cell element field with the in function and / or Networking configurable cells can obviously be a Form a processor, a coprocessor and / or a microcontroller, or a parallel plurality or combinations thereof.

The functional cells are typical formed as arithmetic logic units, in particular represent coarse granular elements, but with a fine granular State machine can be provided. In a particularly preferred embodiment it is in the case of the ALUs by so-called extended ALUs (EALU), as in the previous registrations of the present applicant. An extension can in particular control line control, command decoding unit etc. include where necessary.

The memory cells can store data and / or fleeting information and / or non-volatile to save. If there is information stored in the memory cells it program steps, addresses for one Access to data or data stored in register or heap form as fleeting Data are stored, so a complete reconfiguration during the Operation. Alternatively, it is possible to use non-volatile memory cells provided. The non-volatile Memory cells can such as EE prom area and the like are provided in the a rudimentary Bios program is stored, which is to be executed when commissioning the arrangement. In this way, a commissioning of a Data processing device take place. A non-volatile Data storage can also be provided if cost and / the space reasons it is decided that always again the same parts of the program are to be executed under such fixed program parts, for example according to the type of WA-VE reconfiguration, can be changed during operation. The possibilities of providing such non-volatile memories and use are subject to other property rights of the applicant. It is possible to do both volatile as well as non-volatile Saving data in the memory cells, for example in a bios program firmly stored and still be able to use the memory cell for other purposes.

The memory cell is preferably designed such that it can store a sufficient number of data to be processed and / or program parts to be processed. It should be noted that these program parts can be designed as program steps, each of which specifies what an individual, in particular the assigned PAE, in particular the function cell controlling the memory cell, has to do in the next step, as well as entire configurations for field areas or other fields. In such a case, it is easily possible for the built-up sequencer structure to issue a command, on the basis of which a reconfiguration of cell element field areas takes place. The functional cell that triggers this configuration then also works as a charging logic. It should be pointed out that the configuration of other cells can in turn be carried out in such a way that sequencer-like data processing takes place there and it is in turn possible in these fields to configure or reconfigure other cells in the course of the program work. This results in an iterative configuration of cell element areas and a nesting of programs with sequencer and parallel structures, which are nested one inside the other like a babushka. It should be pointed out that access to further cell element fields outside of a single integrated module can take place here in particular through input / output cells, which can massively increase the overall computing power. In particular, if configurations occur in a code part of a sequencer structure configured into a cell element field, it is possible to either carry out the configuration requests on an assigned cell element field that is managed by the respective sequencer structure alone and / or such requests can be made to a configuration master unit to ensure that all cell element fields are evenly assigned. This results, so to speak, in a subroutine call by transferring the required configurations to cells or loading logic. This is considered worthy of protection in itself. It should also be pointed out that the cells, provided that they themselves are responsible for the configuration of other cell element field areas, can be provided with FILMO structures and the like implemented in the manner of hardware or software in order to ensure proper reconfiguration. Attention is drawn to the possibility of describing the memory cells during the processing of commands in such a way that the code to be processed or the program to be processed changes. In a particularly preferred variant, however, this type of self-modification (SM) is suppressed by an appropriate control via the functional cell.

It is possible that the memory cell is stored Information here on the control of the function cell controlling it directly or indirectly to one leading to the functional cell Bus there. Indirect output can take place in particular if both cells are adjacent and the one requested by activation Information to the ALU-PAE about a bus segment must arrive, that is not directly connected to the output of the memory cell can be. In such a case, the memory cell can store data on this bus system especially via backward registers output. It is therefore preferred if at least one of the memory cells and / or functional cell has such a backward register, which is in the information path can be arranged between the memory cell and the functional cell. In such a case, these registers do not necessarily need additional ones functionalities be provided, although this is for example when data from the Memory cell for further processing, according to a conventional one LOAD command from a typical microprocessor, for modification of the data is easily conceivable even before it is loaded into the PAE is to z. B. to implement a LOAD ++ command.

The memory cell is preferred to be arranged, information from the functional cell controlling it to receive, with further information storage via a An output cell and / or a cell that does not control the memory cell is possible. Especially when data from an input-output cell in the Memory cell to be written, it is preferred if also this input / output cell (I / O-PAE) is controlled by the functional cell. For example, the address at which one is to be written into the memory cell or possibly also read information transmitted directly to the functional cell (PAE) to which I / O-PAE are transmitted by the ALU-PAE. It is in In this context, it should be noted that this address has a Address translation table (address translation table), an address translation buffer or an MMU-like structure in the I / O-PAE can be set. It results in one Case the full functionality typical microprocessors.

The functional cell / memory cell combination is accordingly in a preferred variant at least one input-output means assigned, with which then to an external unit, another function cell, Function cell memory cell combination and / or memory cells sent and / or information can be received.

The input-output unit is thereby preferably also for receiving control commands from the functional cell educated.

In a preferred variant, the control connection is designed to transmit at least some and preferably all of the following commands:

This can be done by an appropriate Bit width of the control line and an assigned decoding at the recipients respectively. The necessary control and decoding means can problem-free and inexpensive be provided. As can be seen, the commands result a practically complete Sequenzerfähigkeit the arrangement. That on a general-purpose processor data processing unit is mentioned.

The arrangement will typically be chosen so that the functional cell can access the control connection and / or a bus segment or bus system serving as a control connection as the sole master. The result is an arrangement in which the control line acts as a command line as it does is provided in conventional processors.

The functional cell and the memory cell or I / O cells are preferably arranged adjacent. Under neighboring can be understood as preferred that the cells are directly next to each other are arranged. Alternatively, they are at least close together. The arrangement of the function and memory cells in the neighborhood to each other ensures that no, in any case, no significant latency times between activation and data input of the requested information in the functional cell occur just because the connections between cells are too long are. This should be understood as "direct". Must have latency periods be taken into account pipelining can also be provided in the sequencer structures become. This becomes particularly important with very high clocked arrangements. It it should be noted that it easily possible is to provide cell units with corresponding high-frequency clocking, which, as is known per se in the prior art, is also correspondingly fast can access suitable memory cells. Even in one This is the case, for example, when architectural elements known per se for the functional cells are used, a reconfigurability of the To provide functional cell element and the associated networking his. In a particularly preferred variant, the function cells are the information supply cells such as memory cells, I / O cells and the like arranged multidimensionally, in particular according to Art a matrix or on grid points of a one-dimensional grid etc. If a regular structure is present, as is the case there, is typically a cell a first row of information, i.e. operands, configurations, Trigger signals etc. supplied, while in an underlying series of data, trigger signals and other information be delivered. In such a case, it will be preferred if the cells are in the same row and then it can the transfer of information from the information supply cell in the required input of the functional cell via Backward register respectively. The possibility, the registers for Using pipelining should be mentioned.

Protection is still claimed for a procedure for operating a cell element field, in particular multidimensional Cell element field with function cells for performing A1-used and / or logical functions and information provision cells, in particular memory cells and / or I / O cells for receiving and / or outputting information and / or storing the same, at least one of the functional cells Control commands to at least one information supply cell outputs information there for the function cell in response to the control commands is provided and the functional cell is designed to the further data processing in response to the provided To carry out information in order to process sequential data.

So it will be in a reconfigurable Field by issuing the control commands to the memory cell one Sequencer structure enables sequencer-like data processing. The commands issued as control commands from the functional cell can be enable thereby a sequencer-like operation, as it is from conventional processors is known. It should be noted that it is easily possible to implement only parts of the commands mentioned and still one Completely to ensure sequencer-like data processing.

The invention is hereinafter and described for example with reference to the drawings. In this is shown by:

1 a cell element field according to the invention, 2a a detail of this,

2 B . c the detail of 2a during different data processing times, 3 an alternative embodiment of the detail of 2 .

4 a particularly preferred variant of the detail.

To 1 comprises a cell element field, generally designated 1, for data processing 1 functional cells 2 for performing arithmetic and / or logical functions as well as memory cells 3 to receive, store and / or output information, with a control connection 4 of functional cells 2 to the memory cells 3 is led.

The cell element field 1 is in the networking of the elements 2 . 3 . 4 freely configurable, and without disrupting the ongoing operation of non-reconfigurable cell element parts. The connections can be configured using bus systems 5 switched as required. Next are the functional cells 2 configurable in their respective function. The function cells are arithmetic logic units that are expanded by certain circuits that enable reconfiguration, such as state machines, interface circuitry for communication with the external charging logic 6 etc. Attention is drawn to the applicant's corresponding advance registrations.

The cell elements 2 . 3 of the cell element field 1 are arranged two-dimensionally in rows and columns, each with a memory cell 3 right next to a functional cell 2 and there are three memory cell-function cell pairs per row, in which the function and memory cells each have control connections 4 are interconnected. The function and memory cells 2 . 3 have inputs connected to the bus system above the row in which the respective cell elements can be connected in order to receive data therefrom. The cells continue to point 2 . 3 Outputs on the bus system 5 Output data below the row. Moreover, as will be explained later every memory cell 3 provided with a backward register (BW), through which data can be passed from the bus below a row to the bus above the respective row.

Except for the tax connections 4 and the assigned circuits within the functional cells (ALU in 2 ) or memory cells (RAM in 2 ) is the cell element field for data processing of 1 a conventional cell element field, as is customary and known in the case of reconfigurable data processing arrangements, for example a VPU in accordance with the XPP technology of the applicant. In particular, the cell element field of 1 As is known, it has appropriate circuits for wave reconfiguration, debugging, transmission of trigger signals, etc.

The special features of the cell element field of the present invention result from the control connection 4 and the associated shading, which will be described in more detail below with reference to the 2a-c , It should be mentioned that while in 1 a tax connection 4 is always led from a function cell element located further to the left to a memory cell located further to the right, and only and precisely to such a memory cell, it is evidently possible to provide a configurable network for the control lines either in order to address memory cells located elsewhere and / or in order to be able to address more than one memory cell if necessary, for example if there is a large amount of memory required for information to be received, stored and / or output from the memory cells. For reasons of clarity, however, in 1 and 2 reference is made only to permanently provided individual control connections, which considerably facilitates the understanding of the invention. The control connection can, if necessary, be replaced by conventional lines, provided the appropriate protocols are used.

In 2 is the functional cell 2 as ALU and the functional cell 3 referred to as RAM. The bus runs above the row in which the cells are located 5a which is the backward register already mentioned 3a with the entrances 3b the memory cell and 2 B the ALU connects. The bus system running below the row is included 5b designated and they are from the bus system 5a . 5b only the relevant segments are drawn. It can be seen that the bus system 5b alternatively receives data from an output 2c the ALU 2 , an exit 3c of the RAM 3 and that there is data in the input 3a1 of the backward register.

The ALU 2 also shows other entrances and exits 2a1 . 2a2 which can be connected to other bus segments and via which the ALU receives data such as operands or outputs results.

The tax connection 4 is permanently under the control of the extended circuits of the ALU and represents a connection over which a large number of bits can be transmitted. The width of the control link 4 is selected so that at least the following control commands can be transmitted to the memory cell: DATA WRITE, DATA READ, ADRESSPOINTER WRITE, ADRESSPOINTER READ, PROGRAMMPOIN-TER WRITE, PROGRAMMPOINTER REÄD, PROGRAMMPOINTER INCREMENT, STACKPOINTER WRITE, STACKPOINTER READ, PUS. The memory cell 3 also has at least three memory areas, namely a so-called stack area, a heap area and a program area. Each area is assigned its own pointer, which is used to determine which area of the stack, the heap and the program area is read or write.

The bus 5a is shared by the units in time division 2 and 3 used. This is in the 2 B . 2c indicated. So is in 2 B shown a situation in which from the exit 2a2 the ALU-PAE data can be sent via the backward register to the input of the RAM cell, whereas the connection between the output, which exists at the same time but is not used, can be sent 3c the RAM to the bus 5b and the connection between the output of the backward register BW to the input 2 B the ALU-PAE at the time of 2 B is of no importance, which is why they are indicated by dashed lines. In 2c however, a point in time is shown at which the memory cell 3 about their exit 3c from the via control line 4 certain memory area stack, heap, program the information on the backward register to the input 2 B the ALU-PAE 2 feeds while the output of the ALU-PAE 2c is inactive and at the entrance 3b the RRM-PAE no signal is received. For this reason, the corresponding connections are dash-dotted and are therefore shown as inactive.

Inside the RAM cell 3 is a circuit 3d provided in which over the control line 4 or the control line bus segment 4 received information is decoded.

The invention is used as follows:
First the ALU receives 2 Configuration information from a central loading logic, as already known in the prior art. The information transmission can be done in a manner known per se using the RDY / ACK protocol and the like. Attention is drawn to the possibility of providing a FIL-MO memory etc. in the loading logic in order to enable a correct configuration of the arrangement.

With the data for the configuration of the ALU 2 At the same time, a series of data is transferred from the loading logic, which represents a program to be processed sequentially. The ALU therefore gives on the line during its configuration 4 one corresponding command that sets the program pointer for writing to a predetermined value within the RAM. Thereafter, data received by the charging logic at the ALU are output 2c over the bus 5b1 and the backward register 3a fed and get from there to the entrance 3b the RAM-PAE 3 , From unity 3d according to the control command on control line 4 then data is written to the specified program memory space. This is repeated until all program parts in the memory cell received by the loading logic during configuration 3 are filed. When the configuration of the ALU is then completed, it is issued on the control line by issuing the corresponding commands 4 request the next program steps to be processed sequentially and via the exit 3c , the bus 5b , the backward register of the RAM-PAE 3 and the bus 5a received at their entrance. During program execution, situations can arise in which jumps within the program memory area are required, data must be loaded into the ALU-PAE from the RAM-PAE, data must be stored in the stack, etc. The relevant communication between ALU-PAE and RAM-PAE takes place via the control line 4 , so that the ALU-PAE can carry out the decoding at any time. Furthermore, as with a conventional microprocessor, data can also be received from a stack or another RAM memory area and data can also be received from outside as operands in the ALU-PAE.

The processing of the Program sequence instead, which is preconfigured in the RAM-PAE by the loading logic has been. In the ALU-PAE there is also one, as required per se Command decoding made. This happens with the same ones per se Circuits that are already for uses the decoding of the commands received from the loading logic become.

It becomes the control line at all times via the ALU 4 checks that the RAM cell always follows the type of memory access specified by the ALU. In this way it is ensured that regardless of the time division multiplex use of the bus elements 5a , b At any time, the elements present in the sequencer structure are given whether there are addresses on the buses for data or codes to be fetched and / or written or whether and wherever data is to be written etc.

The regarding 2 The arrangement shown can be expanded or changed in different ways. The are particularly relevant 3 and 4 shown variants.

To 3 not only is there a backward register on the RAM-PAE for connecting upper and lower buses, but there are also a forward register on the RAM-PAE and forward and backward registers on the ALU-PAE. As indicated by the multiple arrows, these can serve to receive and receive data from other units, such as external hosts, external peripheral devices such as hard disks, main memory and the like and / or from other sequencer structures, PAEs, RAM-PAEs etc. to send to them. If a corresponding request command for new program parts is sent from the sequencer structure which is formed by the ALU-PAE and the RAM-PAE, it is possible to process program blocks in the sequencer structure which are far larger than those which are in the RAM PAE can be saved. This is a huge advantage in particular for complex data processing tasks, jumps over wide areas, especially in subroutines, etc.

A further preferred variant is in 4 shown. Here, the ALU-PAE not only communicates with a RAM-PAE, but also with an input / output-PAE, which is designed to provide an interface circuit for communication with external components such as hard drives, other XPP-VPUs, third-party processors and Coprocessors, etc. Again, the ALU-PAE is the unit that acts as the master for the control link referred to as "CMD" and again the buses are used in a multiplexed manner. Again, data transfer from the bus below the row to the bus Bus above the row through the backward register.

In the 4 The arrangement shown makes it particularly easy to make external access to information that cannot be stored in the RAM-PAE memory cell and thus enables the sequencer structure to be adapted to existing, conventional CPU technologies and their operating methods to an even greater extent than now in the input Output cell address translation means, memory management units (MMU functions) and the like can be implemented. The RRM-PAE can be used here as a cache, but in particular as a preloaded cache.

It should be noted that several Sequencer structures configured simultaneously in one and the same field can be that functional cells, Memory cells and possibly input / output cells optionally for Sequencer structures and / or a conventional one for XPP technology Way can be configured and that it easily possible is that a ALU outputs data to another ALU, which they configure in a sequencer manner and / or make part of a cell element field with which a certain Configuration is processed. In this way, if necessary the charging logic is also unnecessary.

Claims (17)

Cell element field for data processing with function cells for executing algebraic and / or logic functions and memory cells for receiving, storing and / or outputting information, characterized in that a control connection is made to the memory cells from the function cells. Cell element field according to the preceding claim, characterized in that a Processor, coprocessor and / or microcontroller with a variety reconfigurable and / or predefinable in function and / or networking Forms units such as functional cells and / or memory cells. Cell element field according to one of the preceding claims, characterized characterized that the functional cells are formed as arithmetic logic units. Cell element field according to the preceding claim, characterized in that the arithmetic logic units are formed as extended ALUs. Cell element field according to one of the preceding claims, characterized characterized that the memory cells to the fleeting and / or non-volatile Data storage are trained. Cell element field according to one of the preceding claims, characterized characterized that the memory cells for storing data to be processed and / or data to be processed Program steps are trained. Cell element field for data processing, characterized in that the Memory cells are designed to store information to control the functional cell controlling them directly and / or indirectly on a bus leading to the functional cell. A cell element array according to any one of the preceding claims, wherein assigned to at least one memory cell and / or functional cell register are, in particular a backward register, which is in the information path is arranged between the memory cell and the functional cell. Cell element field according to one of the preceding claims, characterized characterized that the memory cell is arranged, information from the function cell controlling it, an input-output cell and / or one not controlling it Receive cell with arithmetic logic unit. Cell element field according to one of the preceding claims, characterized characterized in that the functional cell-memory cell combination at least one input-output agent is assigned to an external unit and / or information another functional cell, functional cell-memory cell combination and / or to send and / or to receive memory cells. Cell element field according to the preceding claim, characterized in that the input-output means likewise for receiving control commands from the functional cell is trained. Cell element field according to one of the preceding claims, characterized characterized that the control is designed to at least some, preferably all of the following To transmit commands and / or the memory cell or input / output cell is to decode the following commands: DATA WRITE / READ, ADRESSPOINTER WRITE / READ, PROGRAMMPOINTER WRITE / READ, PROGRAMMPOINTER INCREMENT, STACKPOINTER WRITE / READ, the aforementioned commands in each case especially for internal and / or external access, PUSH, POP, OPCODE, FETCH. Cell element field according to one of the preceding claims, characterized characterized that the functional cell as sole master on the control connection and / or as Control connection serving bus segment can access. Cell element field for data processing after a of the preceding claims, characterized in that the Function cell adjacent to at least one of the memory cell and the input / output cell is arranged. Cell element field according to one of the preceding claims, characterized characterized that the cell elements are arranged multidimensionally, in particular matrix-like, wherein the functional cell and / or the adjacent memory or. An output cell Receive data from an upper row and into a lower row Can output data, with buses being provided in a row and the functional cell and at least one memory and / or input Output cell are in the same row. Method for operating a cell element field, in particular multidimensional cell element field with function cells for performing algebraic and / or logical functions and information provision cells, in particular memory cells and / or input / output cells for receiving and / or outputting information and / or storing the same, characterized in that at least one the function cells issues control commands to at least one information supply cell, is processed there in response to the control command information for the function cell, and the Function cell is designed to carry out further data processing in response to information provided from the information supply cell so as to process data in the manner of a sequencer. Method according to one of the preceding claims, characterized in that the functional cell is designed to at least some of the control commands

issues and issues at least some, in particular all, of the above-mentioned control commands as required in the course of cell element operation.