DE10239835A1 - Integrated circuit with an integrated multiplexer has clock speed unit pulse generator and a multiplexer step - Google Patents

Abstract

An integrated circuit with an integrated multiplexer comprises a clock unit (101), whereby many second cycles (CLK2I,Q) are produced from one cycle having a predetermined phase position, and a multiplexer step (103) with a pulse generator (102) between them, giving many third cycles (Takt1-4) of given phase position to control multiplexing.

Description

The invention relates to an integrated Circuit arrangement with an integrated multiplexer.

A multiplexer is an electronic one Circuit or assembly that consists of a certain number of its inputs selected input signals and selects one at its output. That from a plurality of parallel applied to the multiplexer Input signals which are present at the plurality of inputs, an output signal is generated. The selection is made using a control signal.

The basic form of a multiplexer is a 2: 1 multiplexer, which generates a signal from two input signals, which are applied to two parallel input channels, which is transmitted via an output channel. Referring to 4 the structure of a 2: 1 multiplexer according to the prior art is explained in more detail.

A first data input 24 is with the gate of a first transistor 25 coupled, the first source / drain region with a first node 26 is coupled and its second source / drain region with a second node 27 is coupled. The first knot 26 is with a first source / drain region of a second transistor 28 coupled. The gate of the second transistor 28 is with a second data input 29 coupled, which is differential to the first data input 24 is. In the context of this application, two differential data connections are understood to mean that if a signal is present at a data connection, the inverse signal is present at this differential data connection. A second source / drain region of the second transistor 28 is with a sixth knot 30 coupled. Furthermore, the first node 26 with a first source / drain region of a third transistor 31 coupled. The gate of the third transistor 31 is with a first clock input 32 coupled. The second source / drain region of the third transistor 31 is with a third knot 33 coupled. The third knot 33 is with a connection of a power source 35 and with a first source / drain region of a fourth transistor 36 coupled. The gate of the fourth transistor 36 is with a second clock input 37 what second clock input 37 is differentially coupled to the first 32 clock input. The second source / drain region of the fourth transistor 37 is with a fourth knot 38 coupled. The fourth knot 38 is with a first source / drain region of a fifth transistor 39 and with a first source / drain region of a sixth transistor 40 coupled. The gate of the fifth transistor 39 is with a third data input 41 coupled. A second source / drain region of the fifth transistor 39 is with a fifth knot 42 coupled. The gate of the sixth transistor 40 is with a fourth data input 43 coupled, which to the third data input 41 is differential. A second source / drain region of the sixth transistor 40 is with a seventh knot 44 coupled.

The second knot 27 is with the fifth knot 42 coupled. Furthermore, the second node 27 using a first impedance 45 to a connection of a voltage source 66 coupled.

The sixth knot 30 is with the seventh knot 44 coupled. Furthermore, the sixth node is by means of a second impedance 46 to the connection of the voltage source 66 coupled.

The fifth knot 42 is coupled to a first output of the 2: 1 multiplexer and the sixth node 30 is coupled to a second output of the 2: 1 multiplexer. The signals which are present at the first output of the 2: 1 multiplexer and at the second output of the 2: 1 multiplexer are different from one another.

The 2: 1 multiplexer generates from two Signals, which on two parallel input connections of the 2: 1 multiplexers are present, a signal that is sent to a serial Output connection of the 2: 1 multiplexer is present and which is then transmitted via a transmission line can be.

In order to generate a signal from more than two signals which are present at parallel connections, several 2: 1 multiplexers are connected in series in a tree-like structure in accordance with the prior art. Since the individual multiplexer stages are generally arranged one above the other, this is also referred to as a stacked, stacked structure. A schematic arrangement of such a tree-like structure for a 4: 1 multiplexer according to the prior art is shown in 5 shown. The arrangement has a 1: 2 clock divider 50 , a first 2: 1 multiplexer 51 , a second 2: 1 multiplexer 52 , a master / slave flip-flop (MS-FF) 53 , a master / slave / master flip-flop (MSM-FF) 54 and a third 2: 1 multiplexer 55 on.

The 1: 2 clock divider 50 has an input connection, which is coupled to a primary clock, which is the 1: 2 clock divider 50 provides a primary clock CLK, and an output connection, by means of which the 1: 2 clock divider 50 provides an output clock CLK / 2 generated from the primary clock, which has half the frequency as the primary clock.

The first 2: 1 multiplexer 51 and the second 2: 1 multiplexer 52 form a first stage of the 4: 1 multiplexer. The first 2: 1 multiplexer 51 has a clock signal input which is connected to the output connection of the 1: 2 clock divider 50 is coupled. Furthermore, the first 2: 1 multiplexer 51 parallel data signal inputs D1, D1 and D3, D3 on, with the data signal inputs D1 and D1 or D3 and D3 are different from each other. The first 2: 1 multiplexer 51 has an output connection to which a first data signal is present.

The second 2: 1 multiplexer 52 has a clock signal input which is connected to the output Connection of the 1: 2 clock divider 50 is coupled. Furthermore, the second 2: 1 multiplexer 52 parallel data signal inputs D2, D2 and D4, D4 on, with the data signal inputs D2 and D2 respectively. D4 and D4 are different from each other. The second 2: 1 multiplexer 52 has an output connection to which a second data signal is present.

The MS-FF 53 has a first input connection which is connected to the output of the first multiplexer 51 is coupled. Furthermore, it has a second input connection, which is coupled to the primary clock and by means of which the MS-FF 53 the primary clock CLK is provided. The MS-FF 53 also has an output connector.

The MSM-FF 54 has a first input connection which is connected to the serial output of the second multiplexer 52 is coupled. Furthermore, it has a second input connection, which is coupled to the primary clock and by means of which the MSM-FF 54 the primary clock CLK is provided. The MSM-FF 54 also has an output connector.

The third 2: 1 multiplexer 55 has a first data input connection which is connected to the output connection of the MS-FF 53 is coupled and which has a first data input of the third 2: 1 multiplexer 55 represents. Furthermore, the third has a 2: 1 multiplexer 55 a second data input connection, which is connected to the output connection of the MSM-FF 54 is coupled and which has a second data input of the third 2: 1 multiplexer 55 represents. A clock input of the third 2: 1 multiplexer 55 is coupled to the primary clock. The third 2: 1 multiplexer is connected via this clock input 55 the primary clock signal CLK provided. The third 2: 1 multiplexer 55 also has a data output connection. The third 2: 1 multiplexer provides at the data output connection 55 a data output signal ready, which represents the data output signal of the 4: 1 multiplexer.

Stacking multiplexers at a 4: 1 multiplexer according to the state The technology that is implemented on a chip leads to several Disadvantages. A disadvantage is that the three 2: 1 multiplexers of the 4: 1 multiplexers according to the state the technology all have to be provided with a power supply, which are also arranged on the chip. The power supplies take one size Area in Claim. This will make for integrated circuits on a wafer available area reduced, what is the number of integrated circuits that are on can be arranged on a wafer, lowers, which increases production costs for the individual Increase circuit. Furthermore, the power consumption of the circuit arrangement is reduced.

Another problem is a high one Requirement for synchronization of the data signals and the clock signals with a multiplexer according to the state of the technique. It can't be big Phase shift between data and clock signal occur because otherwise clock and data signals no longer match in time, which would interfere with a multiplex operation.

The invention is based on the problem required by a 4: 1 multiplexer area to reduce.

This problem is solved by a device according to the independent claim solved.

An integrated according to the invention Circuit arrangement with an integrated multiplexer has one Clock divider, which is set up such that it consists of a first Clock generates a plurality of second clocks, which is a predetermined, preferably have a fixed phase relationship to one another, and a multiplexer stage on. additionally has the integrated circuit arrangement with an integrated Multiplexer on a pulse generator, which is between the clock divider and the multiplexer stage is switched and which pulse generator is set up such that it consists of the first bar and the plurality of second measures, a plurality of third measures generated have a predeterminable, preferably fixed phase relationship to one another and by means of which the multiplexer stage can be controlled.

An integrated according to the invention Circuit arrangement with an integrated multiplexer is such trained that by means of it a multiplexer with more than two Data input connections implemented in one stage can be. A tree-like structure, like a multiplexer according to the status technology is no longer required according to the invention. additionally is in the circuit arrangement according to the invention the multiplexer stage is powered by a single power source. The reduction in the number of current sources in a multiplexer with more than two data input ports the space requirement of the integrated circuit arrangement and reduced thereby the cost of production. Also the power consumption the integrated according to the invention Circuit arrangement with an integrated multiplexer with more as two data input ports versus an integrated one Circuit arrangement with an integrated multiplexer with more as two data input ports according to the status of technology less. The lower power consumption leads to one less heating of the integrated circuit arrangement.

In addition, the problem of synchronization between the data signals of the multiplexer stage and the clock signals of the clocking unit is less in the integrated circuit arrangement according to the invention with an integrated multiplexer. The integrated circuit arrangement according to the invention with an integrated multiplexer is only less susceptible to shifts in the phase relationship of these two signals because of the short duration of the clock signals than a multiplexer according to the state of the art.

Preferred developments of the invention result themselves from the dependent Claims.

Furthermore, the invention is integrated Circuit arrangement with a multiplexer described in more detail.

The pulse generator preferably has an AND logic level which is set up so that it has the plurality of third Clocks generated.

The clock divider is preferably such set up that he has exactly two second bars with predeterminable, preferably fixed phase relationship to each other.

Also preferred is the clock divider a Q / I clock divider.

The pulse generator also preferably generates exactly four third bars with a fixed phase position.

Also preferred are the two second bars by a phase of π des first measure shifted to each other. That the phase shift between a first second cycle and a second second cycle is preferably 180 °, i.e. half a measure, the first measure. In other words, there the second bars have twice the period of the first bar, are the second clock signals, which are shifted by π / 2 against each other are.

Also preferred are the four third bars by a phase of π des first measure shifted to each other. That a second third bar is opposite a first third measure preferably by a phase of π or otherwise expressed by 180 ° of first measure shifted. A third third bar is opposite one second third cycle preferably by a phase of π of the first Measure shifted and a fourth third measure is opposite a third third cycle preferably shifted by a phase of π of the first cycle.

Preferably the integrated one Multiplexer a single-stage 4: 1 multiplexer.

Also preferred is each one of the four third clocks as a control signal for one of the four inputs of the 4: 1 multiplexers used.

Preferably, the integrated Circuit arrangement exactly one current source, which is the multiplexer stage powered.

Furthermore, the first is preferably Clock frequency 15 GHz.

Transistors are preferably the Multiplexer stage CMOS transistors.

An integrated according to the invention Circuit arrangement with an integrated 4: 1 multiplexer is by means of a multiplexer stage realized. A tree-like structure, like it is used in a 4: 1 multiplexer according to the prior art is not according to the invention more needed. In addition, in the circuit arrangement according to the invention the 4: 1 multiplexer stage is powered by a single power source. The number of power sources reduces the space requirement of the integrated Circuitry and reduces the cost of production. Also is the power consumption of the integrated circuit arrangement according to the invention with an integrated 4: 1 multiplexer compared to an integrated circuit arrangement with an integrated 4: 1 multiplexer according to the state of the art about 50% less.

An embodiment of the invention is shown in the figures and is explained in more detail below.

Show it:

1 a schematic block diagram of an integrated circuit arrangement according to the invention with a single-stage 4: 1 multiplexer;

2 a schematic diagram of a 4: 1 multiplexer according to the invention;

3 a schematic signal waveform diagram of the integrated circuit arrangement according to the invention with a 4: 1 multiplexer;

4 a schematic diagram of a 2: 1 multiplexer according to the prior art; and

5 a schematic structure of a 4: 1 multiplexer according to the prior art.

Referring to 1 An integrated circuit arrangement with an integrated multiplexer according to an embodiment of the invention is described in more detail.

The integrated circuit arrangement 100 has a Q / I clock divider 101 a pulse generator 102 and a 4: 1 multiplexer stage 103 on. The Q / I clock divider 101 has an input port 104 and a first output port 106 and a second output port 107 on. The input port 104 is with a clocking unit 105 coupled and is used to supply a primary input clock, from which the Q / I clock divider 101 generates a first output clock CLK / 2-I and a second output clock CLK / 2-Q. The first output clock CLK / 2-I and the second output clock CLK / 2-Q are connected to the first output connection 106 or the second output connection 107 on. The first output clock CLK / 2-I is shifted from the second output clock CLK / 2-Q by -π of the primary input clock, with both the first output clock CLK / 2-I and the second output clock CLK / 2-Q being half the frequency , ie have twice the period of the primary input clock. Ie the second output clock CLK / 2-Q is shifted from the first output clock by a phase of π or in other words by 180 ° of the first clock. Since the two output clocks CLK / 2-I and CLK / 2-Q have half the frequency as the primary input clock, the two output clocks have a phase shift of π / 2 of their own period against each other.

The pulse generator 102 has a second input port 108 , a third input connector 109 and a fourth input port 110 on. It also instructs a third exit Enough 111 , a fourth output connector 112 , a fifth output connector 113 and a sixth output port 114 on. The second input port 108 is with the first output connector 106 coupled, the third input connection 109 is with the second output connector 107 coupled and the fourth input connector 110 is with the clocking unit 105 coupled. The pulse generator 102 generated by an AND operation of the three clock signals, CLK / 2-I, CLK / 2-Q and the primary input clock signal, which on its three input terminals 108 . 109 and 110 are present, four output signals clock1, clock2, clock3 and clock4, which at the four output connections 111 . 112 . 113 respectively. 114 issue.

The 4: 1 multiplexer stage has a fifth clock input connection 115 , a sixth clock input connector 116 , a seventh clock input connector 117 and an eighth clock input connector 118 on. These clock input ports 115 . 116 . 117 respectively. 118 are with the four output connections 111 . 112 . 113 respectively. 114 of the pulse generator coupled. Furthermore, the 4: 1 multiplexer stage has a ninth data input connection 119 , a tenth data input connector 120 , an eleventh data input connector 121 and a twelfth data input port 122 on. These four data input ports 119 . 120 . 121 and 122 form data inputs of the 4: 1 multiplexer. By means of these data inputs, the 4: 1 multiplexer receives four differential data signals D1, D1 ; D2, D2 ; D3, D3 and D4, D4 supplied, from which the 4: 1 multiplexer stage a data output signal Q, Q generated, which at the seventh serial output connection 123 is applied.

Referring to 2 the structure of the 4: 1 multiplexer stage according to the invention is explained in detail. A first data input 224 is with the gate of a first transistor 225 coupled, the first source / drain region with a first node 226 is coupled and its second source / drain region with a second node 227 is coupled. The first knot 226 is with a first source / drain region of a second transistor 228 coupled. The gate of the second transistor 228 is with a second data input 229 coupled, which is differential to the first data input 224 is. Different from one another means that when a signal is present at a first connection, the inverse signal is present at a second connection that is differential to this first connection. A second source / drain region of the second transistor 228 is with a sixth knot 230 coupled. Furthermore, the first node 226 with a first source / drain region of a third transistor 231 coupled. The gate of the third transistor 231 is with a first clock input 232 coupled. The second source / drain region of the third transistor 231 is with a third knot 233 coupled. The third knot 233 is with an eighth knot 234 coupled. The eighth knot 234 is with a connection of a power source 235 and with a first source / drain region of a fourth transistor 236 coupled. The gate of the fourth transistor 236 is with a second clock input 237 coupled. The second source / drain region of the fourth transistor 237 is with a fourth knot 238 coupled. The fourth knot 238 is with a first source / drain region of a fifth transistor 239 and with a first source / drain region of a sixth transistor 240 coupled. The gate of the fifth transistor 239 is with a third data input 241 coupled. A second source / drain region of the fifth transistor 239 is with a fifth knot 242 coupled. The gate of the sixth transistor 240 is with a fourth data input 243 coupled, which to the third data input 241 is differential. A second source / drain region of the sixth transistor 240 is with a seventh knot 244 coupled.

The second knot 227 is with the fifth knot 242 coupled. Furthermore, the second node 227 using a first impedance 245 to a connection of a voltage source 266 coupled.

The sixth knot 230 is with the seventh knot 244 coupled. Furthermore, the sixth node is by means of a second impedance 246 to the connection of the voltage source 266 coupled.

A fifth data input 247 is with the gate of a seventh transistor 248 coupled, the first source / drain region with a ninth node 249 is coupled and its second source / drain region with a tenth node 250 is coupled. The tenth knot 250 is with the fifth knot 252 coupled. The ninth knot 249 is with a first source / drain region of an eighth transistor 251 coupled. The gate of the eighth transistor 251 is with a sixth data input 252 coupled, which is differential to the fifth data input 247 is. A second source / drain region of the eighth transistor 251 is with an eleventh knot 253 coupled. The eleventh knot 253 is with the seventh knot 244 coupled. Furthermore, the ninth knot 249 with a first source / drain region of a ninth transistor 254 coupled. The gate of the ninth transistor 254 is with a third clock input 255 coupled. The second source / drain region of the ninth transistor 254 is with a twelfth knot 256 coupled. The twelfth knot 256 is with the eighth knot 234 coupled. The twelfth knot 256 is with a first source / drain region of a tenth transistor 257 coupled. The gate of the tenth transistor 257 is with a fourth clock input 258 coupled. The second source / drain region of the tenth transistor 257 is with a thirteenth knot 259 coupled. The thirteenth knot 259 is with a first source / drain region of an eleventh transistor 260 and with a first source / drain region of a twelfth transistor 261 coupled. The gate of the eleventh transistor 260 is with a seventh data input 262 coupled. A second source / drain region of the eleventh transistor 260 is with a fourteenth knot 263 coupled. The fourteenth knot 263 is with the tenth knot 250 coupled. The gate of the twelfth transistor 261 is with an eighth data input 264 coupled, which to the seventh data input 262 is differential. A second source / drain region of the twelfth transistor 261 is with a fifteenth knot 265 coupled. The fifteenth knot 265 is with the eleventh knot 253 coupled.

The fourteenth knot 263 is coupled to an output port of the 4: 1 multiplexer and the fifteenth node 265 is coupled to a second output connection of the 4: 1 multiplexer. The signals which are present at the first output connection of the 4: 1 multiplexer and the second output connection of the 4: 1 multiplexer are different from one another.

In the described embodiment, the first impedance 245 and the second impedance 246 a value of 70 Ω with an inductance of 0.25 nH. The impedances can be, for example, resistors, resistors which are connected in series with an inductor, or MOS transistors. The one from the power source 235 provided current is 6 mA. The one from the voltage source 266 The voltage provided is 1.5 V. The primary clock has a frequency of 15 GHz. The first 225 , second 228 , fifth 239 , sixth 240 , seventh 248 eighth 251 , eleventh 260 and the twelfth transistor 261 have a gate length of 120 nm and a gate width of 20 μm, while the third 231 , the fourth 236 , the ninth 254 and the tenth transistor 257 have a gate length of 120 nm and your gate width of 30 μm.

Referring to 3 the time course of the signals in the integrated circuit arrangement according to the invention is shown in detail.

The first line from above shows schematically the time profile of the first data signal D1 and the data signal which is differential to it D1 shown.

In the second line from the top, the time profile of the second data signal D2 and the differential data signal is schematic D2 shown.

In the third line from the top, the time profile of the third data signal D3 and the data signal which is differential thereto is shown schematically D3 shown.

In the fourth line from the top, the time profile of the fourth data signal D4 and the differential data signal are shown D4 shown.

The first four lines of the 3 The data signals shown are each delayed by a phase of π of the primary clock and the duration of the data signals D1, D2, D3 and D4 are two periods of the primary clock signal CLK. Furthermore, the four data signals D1, D2, D3 and D4 are the data signals which are at the data inputs 224 . 241 . 247 respectively. 262 of the 4: 1 multiplexer are created. The differential data signals for this D1 . D2 . D3 respectively. D4 are the data signals which are at the data inputs 229 . 243 . 252 respectively. 264 of the 4: 1 multiplexer are created.

In the fifth line from the top is the temporal course of the primary clock signal CLK, which serves as an input signal for the Q / I clock divider.

The sixth line from the top is schematically the time course of the first output signal CLK / 2-I and the second output signal CLK / 2-Q of the Q / I clock divider. These two output signals are around a phase of n of the primary clock signal CLK shifted against each other and have half the frequency or in other words, the double period of the primary clock signal CLK on.

In the seventh to tenth lines from the top, four output signals clock1, clock2, clock3 and clock4 of the pulse generator are shown, which are the clock signals which are at the four clock inputs 232 . 234 . 255 respectively. 258 of the 4: 1 multiplexer are created. The four output signals clock1, clock2, clock3 and clock4 are generated by ANDing the primary clock signal and the two output signals CLK / 2-I and CLK / 2-Q, which are generated by the Q / I clock divider.

In the eleventh row from the top in the 3 the course of the signals at the first output connection and the signals at the second output connection, which are different from the signals at the first output connection, of the 4: 1 multiplexer is shown schematically. It can be seen that the first data signal D1 is present at the output exactly when the first clock signal Clock1 is present at the 4: 1 multiplexer. The second data signal D2 is present at the output precisely when the second clock signal Clock2 is present at the 4: 1 multiplexer. The third data signal D3 is present at the output precisely when the third clock signal Clock3 is present at the 4: 1 multiplexer. The fourth data signal D4 is present at the output precisely when the fourth clock signal clock 4 is present at the 4: 1 multiplexer.

This is the parallel / serial conversion the one at the four entrances parallel signals, in other words the merging of the four input signals to a common output signal, which is provided at the output of the 4: 1 multiplexer. The multiplexer functionality is thus implemented.

On 3 it can also be seen that the 4: 1 multiplexer according to the invention is less susceptible to a relative phase shift of the data signals to the clock signals than a 4: 1 multiplexer according to the prior art. Since the data signals D1, D2, D3 and D4 are four times as long as the clock signals clock1, clock2, clock3 and clock4 used, a phase shift between the data signals and the clock signals is less critical than in a 4: 1 multi plexer according to the prior art.

In summary, the Invention created an integrated circuit arrangement, which has a 4: 1 multiplexer. This 4: 1 multiplexer is a one-stage multiplexer, while according to the state the technology a 4: 1 multiplexer from three tree-like coupled together 2: 1 multiplexers is built. The integrated according to the invention Circuit arrangement is a circuit arrangement with little need of electrical power and is for multiplexing four data signals a data signal up to the highest Data rates (gigabit circuits) in any semiconductor technology, such as. SiGe, InP, GaAs or other compound semiconductors.

In the exemplary embodiment according to the invention shows the entire multiplexer stage (single-stage 4: 1 multiplexer) only one power supply, which creates the integrated circuit arrangement across from the prior art can be reduced.

In the circuit arrangement according to the invention is the total number to achieve the same functionality of components less than in a circuit arrangement according to the prior art of technology, this leads to a lower power consumption of the circuit arrangement according to the invention with a 4: 1 multiplexer opposite a circuit arrangement with a 4: 1 multiplexer according to the prior art of the technique.

The circuit according to the invention can also in High speed input / outputs of DRAMs can be used.

24

first Data input

25

first transistor

26

first node

27

second node

28

second transistor

29

second Data input

30

sixth node

31

third transistor

32

first Clock input

33

third node

35

power source

36

fourth transistor

37

second Clock input

38

fourth node

39

fifth transistor

40

sixth transistor

41

third Data input

42

fifth knot

43

fourth Data input

44

seventh node

45

first impedance

46

second impedance

50

1: 2 clock divider

51

first 2: 1 multiplexer

52

second 2: 1 multiplexer

53

Master / Slave Flip-flop

54

Master / Slave / Master Flip-flop

55

third 2: 1 multiplexer

66

voltage source

100

integrated circuitry

101

Q / I clock divider

102

pulse generator

103

4: 1 multiplexer

104

first input port

105

clocking unit

106

first output port

107

second output port

108

second input port

109

third input port

110

fourth input port

111

third output port

112

fourth output port

113

fifth output connector

114

sixth output port

115

fifth clock input connector

116

sixth Clock input terminal

117

seventh Clock input terminal

118

eight Clock input terminal

119

ninth Data input terminal

120

tenth Data input terminal

121

eleventh Data input terminal

122

twelfth data input connection

123

seventh serial output connector

224

first Data input

225

first transistor

226

first node

227

second node

228

second transistor

229

second Data input

230

sixth node

231

third transistor

232

first Clock input

233

third node

234

eight node

235

power source

236

fourth transistor

237

second Clock input

238

fourth node

239

fifth transistor

240

sixth transistor

241

third Data input

242

fifth knot

243

fourth Data input

244

seventh node

245

first impedance

246

second impedance

247

fifth data input

248

seventh transistor

249

ninth node

250

tenth node

251

eight transistor

252

sixth Data input

253

eleventh node

254

ninth transistor

255

third Clock input

256

twelfth knot

257

tenth transistor

258

fourth Clock input

259

thirteenth node

260

eleventh transistor

261

twelfth transistor

262

seventh Data input

263

fourteenth node

264

eight Data input

265

fifteenth node

266

voltage source

Claims (12)

Integrated circuit arrangement with an integrated multiplexer, which has:  a clock divider, which is set up in this way is that it has a plurality of second measures from a first measure generated which have a predeterminable phase relationship to one another; a multiplexer; and a pulse generator, which between the clock divider and the multiplexer stage is switched and which pulse generator is set up such that it consists of the first bar and the plurality of second measures, generates a plurality of third measures, which one have predeterminable phase relationship to one another and by means of which the multiplexer stage is controllable. Integrated circuit arrangement with an integrated multiplexer according to claim 1, wherein the pulse generator has an AND logic stage, which is set up so that it has the plurality of third bars generated. Integrated circuit arrangement with an integrated multiplexer according to claim 1 or 2, with the clock divider exactly two second bars with predeterminable Phases generated to each other. Integrated circuit arrangement with an integrated multiplexer according to one of claims 1 to 3, the clock divider being a Q / I clock divider. Integrated circuit arrangement with an integrated multiplexer according to one of claims 1 to 4, the pulse generator being exactly four third cycles with predeterminable Phase position generated. Integrated circuit arrangement with an integrated multiplexer according to one of claims 3 to 5, the two second clocks by a phase of π of the first Clock are shifted to each other. Integrated circuit arrangement with an integrated multiplexer according to claim 6, the four third clocks by a phase of π of the first clock are shifted towards each other. Integrated circuit arrangement with an integrated multiplexer according to one of claims 5 to 7, with the integrated multiplexer being a single-stage 4: 1 multiplexer is. Integrated circuit arrangement with an integrated multiplexer according to claim 8, wherein one of the four third clocks as a control signal for each one of the four entrances of the 4: 1 multiplexer is used. Integrated circuit arrangement with an integrated multiplexer according to one of claims 1 to 9, the integrated circuit arrangement being exactly one current source which supplies the multiplexer stage with current. Integrated circuit arrangement with an integrated multiplexer according to one of claims 1 to 10, the first clock frequency being 15 GHz. Integrated circuit arrangement with an integrated multiplexer according to one of claims 1 to 11, where transistors of the multiplexer stage CMOS transistors are.