DE10219782C1 - Method and auxiliary device for testing a RAM memory circuit - Google Patents

Abstract

The invention relates to the testing of a RAM memory circuit which contains a multiplicity of memory cells, each of which can be selected in groups of n> = 1 memory cells by means of address information applied, in order to write or read groups of n data thereon. According to the invention, a plurality i = j È m of the memory cell groups is selected in a test write cycle, where j and m are each integers> = 2, and the same date is written on all memory cells of each m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in such a sequence that the data groups read out of m memory cell groups, on which the same date has been written in, are simultaneously or immediately provided as a read data block which m È n data included. When a read data block is provided, a compressed test result is determined and made available, which indicates whether all of the data in the read data block provided match the date written.

Description

The invention relates to a method and an auxiliary device device for testing a RAM memory circuit according to the Ober Concept of patent claim 1 or patent claim 2.

The acronym "RAM" (derived from "Random Access Memory") is usually used to designate a data file chers, which has a plurality of memory cells, the each can save a date and on which by means of a Selection device can be accessed selectively and directly can either write or read data. The Memory cells are in one or more separate cells fields, so-called "banks", summarized. The selecti onseinrichtung contains address decoder, a network of Selekti onsleitung and a network of data paths and is more common wise together with the memory cells and other auxiliary integrated circuits on one and the same chip. The so ge formed entire RAM memory circuit has external connections to input and output the data to be written or read to create address information for identification the memory to be selected for writing or reading cells, as well as other external connections for command signals and clock signals to initiate and control various Operations.

The selection device mentioned speaks in each case created address information to identify the hereby th ("addressed") memory cells for a write or Select reading mode. This selection is made in the print zip in that the selection device depending on the Address information selected selection lines excited to to operate assigned switches in the data path network and there through data transmission paths between the addressed Spei  through cells and an internal data bus leads to the external data connections.

As a result of this selection process, write data that when a write command appears on the data bus are provided, their way into the addressed storage cell len, and when a read command appears, the find in the addressed memory cells contain their way to Data bus. The data bus is typically a parallel bus for simultaneous transfer of n data, and the selection device is designed so that with an address information each address a group of n memory cells simultaneously can be selected and selected for writing or reading.

To check the functionality of a RAM memory circuit are different tests in different stages of manufacture necessary. In principle, such tests exist therein, a specific date in each memory cell to be registered and checked during subsequent read accesses whether the read data with the previously written Data match. Especially during the final inspection on the fer term chip, it may be appropriate to preselect the same Date in a subset of memory cells ben that select at least one group of n at the same time baren includes memory cells. With each read access, because all n memory cells of such a group at the same time read out, and it is checked whether all n read out data of this group match the selected date or Not. With each read access, there are n memory cells len checked at the same time.

Memory tests are carried out with the help of external test devices leads who work according to a selectable test program the respective address and data information for the Se lesson of the memory cells and for the data to be written to provide, also command bits for specifying the to deliver the respective operating mode of the memory circuit and  Generate strobe signals for querying the test results. The working speed of such test devices is up limited. This applies in particular to the maximum follow-up rate sequence of strobe signals. Because with advancing development storage technology, the data rates of memories are getting higher the problem arises that the strobe signals from existing test devices at the rate of read access on Memory can no longer follow.

Under the term "data rate", which is used to specify a Belongs to the memory circuit, one understands the repetition frequency, with which data or groups of parallel data bits in succession on and off at the data connections of the memory circuit can be given. For RAMs with a simple data rate (SDR) work, the data rate corresponds to the access clock rate, d. H. the repetition frequency with which different Spei memory cells (or memory cell groups) one after the other Write or read can be selected. For RAMs that work with multiple data rate, corresponds to the data rate an integer multiple of the access clock rate play double (DDR) or even quadruple (DDR-II) this clock rate.

Test equipment is very expensive (on the order of a few) Million euros), and the more, the higher their maximum Working speed is. To the acquisition cost for save faster test equipment and with a slow test until now, compromises have had to be made sen. A possible compromise would be to test the memory with a data rate lower than the nominal value ben, which has the disadvantage that the test actually The intended conditions of use of the memory are not taken into account. Another compromise is the memory in the Operate test mode with its fast nominal data rate and design the test program so that the queries the test results within a test run single read Accesses are skipped by the test results only  every second (or only every third or fourth, etc.) Le can be queried. However, this has the disadvantage that the test run be repeated once (or several times) must to check the skipped read access after pick up.

US Pat. No. 4,860,259 describes a method for testing a RAM Memory circuit and a corresponding test auxiliary device known in which to write data in groups of Memory cells created by address information are selectable, the procedure is as follows. In one Write cycle a memory cell group is selected and then that in all memory cells of the memory cell group same date registered. Then in one Read cycle the memory selected in the write cycle cell group read out to a corresponding read data block to provide, in addition a compressed Test result is determined and provided, which indicates whether the data of the read data block provided with the registered data match.

From DE 198 18 045 A1 it is also known to parallel n Write groups of m data in n × m memory cell, then read out this data again in parallel and read the n to check the data groups read, whether they are compatible with the registered data match.

Both of these compromises naturally mean that the total time for a complete memory test is relatively long. The object of the invention is to provide egg ner technology that makes it possible to shorten this total time without having to increase the frequency of the query of the test results. This object is achieved by the method specified in claim 1 and the features specified in claim 2 of a Testhilfseinrich device (the symbol used stands for multiplication).

Accordingly, the invention is implemented by a method to test a RAM memory circuit that a variety of Contains memory cells, each in groups of n ≧ 1 Selek memory cells by an applied address information are animalable to include groups of n data on them write or read. According to the invention, this includes Proceed as follows: First, one Write cycle a plurality i = j.m of the memory cell groups selected, where j and m are integers ≧ 2, and on all memory cells of each selected m The same date is written into memory cell groups. In a subsequent read cycle, the im Write cycle selected i memory cell groups in one such a sequence selected and read out that the read data groups from m Memory cell groups on which the same date is entered has been written, simultaneously or immediately after other than a read data block are provided which m.n Data includes. Each time you provide one Read data block becomes a compressed test result determined and provided, which indicates whether all m.n Data of the read data block provided with the registered date  voices.

The invention is also implemented by a test aid direction for testing a RAM memory circuit, the one Variety of memory cells, an input / output device for receiving and outputting memory data and an address contains the input for creating address information and has a selection device to groups of each n ≧ 1 memory cells depending on the address information created tion to be selected and at the selected memory cell group to write in or out a group of n data to read. According to the invention, a test control device and an evaluation device is provided, the test control direction is designed to create such tax, Da ten- and address information to the selection device that a plurality i = j.m of the memory cell in a write cycle len groups is selected, where j and m are whole numbers len ≧ 2, and on all memory cells of each m selek the same date was written into the memory cell groups ben, and that in a subsequent read cycle the im Write cycle selected i memory cell groups in one such a sequence are selected and read out that the read data groups from m memory cell groups pen on which the same date was registered, simultaneously or in immediate succession as a read data block are provided, which includes m.n data. The out value device is designed so that it with each loading provision of a read data block a compressed test result determined and provided, which indicates whether all m.n data of the read data block provided with the one written date match.

The invention has the advantage that fast storage under Operation with a high clock permitted according to the specification rate in a correspondingly short time also by means of relatively long test devices can be tested. So it is possible Lich, the slower to test the most modern memory, already  to test existing or cheaper to buy test equipment without having to buy the long test times that were previously common to have to take.

Advantageous embodiments of the invention are in Unteran sayings marked. For a more detailed explanation standing examples described with reference to drawings ben.

Fig. 1 shows a block diagram schematically an arrangement containing an SDR-DRAM memory circuit with a test aid device according to the invention and a connected test device;

Fig. 2 shows a timing diagram for explaining the operation of the arrangement of Fig. 1;

Fig. 3 shows a block diagram schematically an arrangement containing a DDR-DRAM memory circuit with a test aid device according to the invention and a connected tester;

Fig. 4 shows a timing diagram for explaining the operation of the arrangement of Fig. 3;

The memory circuit 70 shown schematically in FIG. 1 is a dynamic type (SDR-DRAM) designed for simple data rate (SDR) and forms with all its parts drawn within the dashed frame an integrated circuit on a single semiconductor chip. On the right, a DRAM memory bank 10 is shown schematically and in fragments, containing a plurality of memory cells (not shown) which are arranged in a matrix in rows and columns. The memory cells can be selectively accessed by means of a selection device 11 in order to write in or read out data. The selection device 11 is designed so that it can select a group of n memory cells at a time. The respective memory cell group can be specified by address information, consisting of a plurality of row address bits, which are supplied from a row address buffer 12 via a row address bus 13 , and a plurality of column address bits, which are derived from a column address buffer 14 can be supplied via a column address bus 15 . The row and column address bits are applied to the address buffers 12 and 14 from the outside via address connections A [0: k] of the chip. The selection device 11 contains a row and a column address decoder (not shown) in order to decode the address bits and to derive suitable activation and control signals for the selection of the memory cells.

As is known per se, measures are taken in the memory circuit 70 according to FIG. 1 in order to internally generate a "burst" of a plurality of successive addresses from address information which is input from the outside at the address connections A [0: k] that after entering the external address information, several memory cell groups can be selected one after the other. For this purpose, an address changer in the form of an address counter is usually provided, which can be actuated in time with the read or write operation in order to advance individual bits of the row address and / or the column address via different bit patterns at its binary counter value outputs. In Fig. 1, this address counter is symbolically represented by a block 22 by way of the address buses 13 and 14 . The address counter 22 can be preset by a "burst start" signal BST for the delivery of a start address, which is determined by the external address information, and then counts under the control of a switching signal S3 in the form of counting pulses with the clock rate CLKi in order to to deliver the following addresses of the burst to the selection device 11 . The so-called "burst length" indicates how many addresses are delivered per burst. With SDR memory circuits, the burst length also indicates how many memory cell groups are selected per external address information.

For the input and output of data, n data connections D [1: n] are provided, which are connected via a switchable bidirectional data port, which is symbolically represented as an n-pole line switch 16 , to an internal data bus 17 which contains n parallel data lines. The data bus 17 is connected to the selection device 11 via an n-bit latch 18 , which holds the write data supplied via the data bus 17 or the read data supplied by the selection device 11 until new write or read data arrive in each case.

To control the operations for writing and reading data, a control part 19 is provided, which has an input for receiving an internal clock signal CLKi and also has the usual command inputs for receiving c external command bits CB [1: c]. The internal clock signal CLKi is supplied by an internal clock generator 20 , which is synchronized by an external clock signal CLK, which, like the control commands mentioned, can be supplied via assigned control connections on the chip.

In response to the internal clock signal CLKi and the command dobits CB [1: c], the control part 19 delivers the necessary control signals to the selection device 11 via a bundle of control lines 21 for the time-controlled execution of the various switching operations by the row and column addresses Selectively connect memory cell groups to the latch 18 for writing and reading data. The control part also provides a test mode setting signal TM, the already mentioned burst start signal BST and also a write operation signal WRD and a read operation signal RDD. The structure and operation of the control part 19 and the selection device 11 need not be discussed in detail here, since suitable implementations are generally known.

In order to test whether a memory circuit outputs the written data in an unadulterated manner, test devices are used which can be connected to the address, control and data connections of the memory circuit in order to write and read data on the memory cells in accordance with a selectable test program to organize. A typical test device is shown schematically in the lower part of FIG. 1 and is designated overall by the reference number 90 . It contains its own clock generator 91 for supplying the clock signal CLK to the clock control connection of the memory circuit to be tested, a sequence control device 92 and a signaling circuit 93 . The sequence control device 92 supplies the control commands and the address information for the read and write operation to the relevant connections of the memory circuit and a test data information at a test data output TD for specifying the respective data to be written in under time control by the clock signal CLK and in accordance with the respective test program. The notification circuit 93 has a test result input TR in order to receive a test result from the memory circuit, which indicates whether a test is “passed” or “not passed”. The reporting circuit also has a scanning input for receiving a strobe signal STR, which is supplied by the sequence control device 92 in order to cause the reporting device 93 to report the received test result after each individual test procedure.

Memory testers such as B. the test device 90 usually only provide the external command and data information for the storage mode and the clock signal CLK for synchronizing the storage mode with the testing device, while the determination of the test results is carried out by a separate device, which is specific to the architecture and the specifications of the memory circuit are matched and preferably integrated on the same chip as the memory circuit. In the newer memory circuits, which are designed for increasingly higher operating speeds, the said test auxiliary device is also designed for a correspondingly high speed. As already mentioned at the beginning, however, it is often not sensible for economic reasons to purchase correspondingly fast memory test devices.

The present invention provides a memory circuit to operate in a test mode such that the memory cell len are checked just as quickly as the corresponds to the data rate to be provided for normal operation on the other hand, the test results determined during the test ready in real time and seamlessly with a repetition frequency that is significantly lower than the data rate. So even a slow test device can keep up and a complete scan of all test results provided create.

A test mode according to the invention is first described below using the example of the memory circuit 70 shown in FIG. 1, which, as said, is a DRAM memory circuit working with a simple data rate (SDR-DRAM). To implement the test mode in the memory circuit 70 , an auxiliary device is provided, the elements 30-46 of which are described together with the time diagram shown in FIG. 2, which illustrates the operational sequences of the test mode.

The test mode is activated by the effective state of the test mode setting signal TM, which is decoded by the control part 19 from the command bits CB [1: c] supplied by the test device 90 . The test mode includes a write mode and a subsequent read mode with evaluation of the read data. The address, control and clock information are derived from the internal address buffer 12 , the internal control part 19 and the internal clock 20 , which in turn are connected to the test device 90 which specifies the test program. The clock CLK of the tester, who is also the synchronized in-internal clock 20 is set at half the frequency of the signal supplied by the internal clock 20 in-internal clock signal CLKi, which in turn adjusts the data rate be. The clock 20 is set by the active test mode setting signal TM so that it generates the internal clock signal CLKi with twice the frequency of the external clock signal CLK.

First, the write operation of the test mode will be explained. The test write operation, the sequence of which is illustrated in the left part of FIG. 2, runs for the duration of a write operation signal WRD provided by the control part 19 . During the test write operation, the n-pole line switch 16 is opened by a switching signal S1, so that the data bus 17 is disconnected from the data connections D [1: n]. In time with the external clock signal CLK, the test device 90 supplies successive test write data q1, q2, q3, etc., each consisting of a single bit with the binary value "0" or "1", to the data input D1. From there, this data passes through a line 31 bridging the open switch 16 and an n-pole switch 32 , which is only kept closed during the test write operation by a switching signal S2, in each case given to all n lines of the data bus 17 . The n-bit latch 18 thus provides each of the data for the duration of two periods of the fast internal clock signal, specifically as an n-bit data word in which all bits have the value of the test date. Thus, in each case in two successive periods of the fast clock signal CLKi, the same data "0" or "1" can be written in all memory cells of two different groups.

In order to select the individual memory cell groups in this fast test write operation, the addresses placed on the selection device 11 must be changed according to plan and following the fast clock CLKi. Since the Testge advises 90 consecutive address information via the address connections A [0: k] only with the slow clock CLK, two different addresses must be derived quickly from each address information supplied in succession. This can be done in a simple manner, for. B. happen by using the address counter 22 described above, wherein the burst length is set to a value r ≧ 2. In the exemplary embodiment described here, the value r = 2 is selected for the burst length. That is, the address counter 22 is set to a start address in accordance with this address information each time external address information is created and, after a period of the internal fast clock CLKi, is switched on once by the signal S3 in order to provide a subsequent address.

With a first clock pulse of the fast clock signal CLKi, the first data item q1 is written into all n memory cells of a first group G1 _{1 of} a first memory cell group pair, corresponding to the start address, which is specified by the first external address information. With the next clock pulse, the first data q1 is written in all memory cells of a second group G1 _{2 of} the first group pair G1. Then, in a similar manner, the second date q2 is first registered in a first group G2 ₁ and then in a second group G2 _{2 of} a second group pair G2. This continues until after a total of i cycles several or all memory cell groups of the matrix 10 have been filled in pairs (and with the same date "0" or "1" within each of the i pairs).

After this test write operation begins the test read operation described below, the sequence of which is illustrated on the right in FIG. 2. During the test read mode, which runs for the duration of a read signal RDD provided by the control part 19 , the switch 16 remains open, but the switch 32 is closed. A white further n-pole switch 41 , which was open during the test write operation, is kept closed by a switching signal S4 in order to now connect the data bus 17 to an n-bit signal input of a comparator 42 . The switch 41 and the comparator 42 are part of an evaluation device 40 with further elements to be written.

Also in test read mode, the test device 90 supplies successive address information in the slow clock CLK. Simultaneously with the address information, it supplies the associated test data q1, q2, etc. with the rising edges of the clock signal CLK, from its test data output TD to the data connection D1. The test program ensures that the assignment of the binary value of this test data to the address information is the same as in the test write operation described above. From the D1 circuit, the test data does not reach the data bus 17 because of the open state of the switches 16 and 32 , but via a line 46 to a reference input of the comparator 42 .

The address counter 22 is controlled by the fast clock signal CLKi in the same way as in the test write operation. Thus, when the first address information is created, the data of all n memory cells of the first group G1 _{1 of} the memory cell group pair G1 are first loaded into the latch 18 as an n-bit data word R1 ₁ , and then the data of all n memory cells of the second group G1 ₂ of group pair G1 is loaded into latch 18 as n-bit data word R1 ₂ . Subsequently, when the second address information is created, the data of all n memory cells of the first group G2 _{1 of} the second group pair G2 are first loaded into the latch 18 as n-bit data word R2 ₁ , and then the data of all n memories cells of the second group G2 ₂ second group pair G2 loaded as an n-bit data word R2 ₂ in the latch 18 . This game continues, so that the latch 18 provides the clock signal CLKi successively read n-bit data words R1 ₁ , R1 ₂ , R2 ₁ , R2 ₂ , R3 ₁ , R3 ₂ , etc.

The stream of these n-bit data words reaches the n-bit signal input of the comparator 42 via the data bus 17 and the closed switch 41 . The comparator 42 delivers a logic "1" at its output if and only if all n bits at the signal input have the same value as the test data bit at the reference input. This test data bit is present for the duration of an entire period of the slow clock signal CLK, during which two consecutive data words arrive at the n-bit signal input and are read out from two memory cell groups which have previously been filled with the same test date.

The comparator 42 first compares the data word R1 ₁ with the test data q1. If there is no error, then all n bits of R1 _{1 are} equal to q1, and the comparator supplies the first partial result X1 _{1 with} a "1"("testpassed") at its output, otherwise a "0" is returned ("Test failed"). Then, at the next clock cycle of CLKi, the comparator 42 compares the data word R1 ₂ with the test date q1. If there is no error, then all n bits of R1 _{2 are} equal to q1, and the comparator returns "1" as the second partial result X1 ₂ ; otherwise a "0" will be delivered. This game is continued in a similar manner to successively compare data words R2 ₁ , R2 ₂ with test date q2, then compare data words R3 ₁ , R3 ₂ with test date q3, etc.

For the purpose of further evaluation, the evaluation device 40 additionally contains an RS flip-flop 44 whose S input (S input) is connected to receive the burst start signal BST. The output of the comparator 42 is inverted with the R input (reset input) of the RS flip-flop 44 . At the beginning of each address burst, that is, with the placement of external address information at the beginning of each full period of the slow external clock signal CLK, the signal BST appears, whereby the output of the flip-flop is set to "1". As long as the output of the comparator 42 is at "1" and thus indicates partial results "test passed", the R input of the flip-flop 44 remains at "0" and the flip-flop does not change its state. As soon as the comparator delivers a partial result "failed" (ie a "0"), the R input of flip-flop 44 goes to "1", and the output of flip-flop 44 goes to "0" and retains this state until End of the started period of the slow external clock CLK. Only at the beginning of the next period of the slow external clock CLK, that is to say at the beginning of the next address burst, is the flip-flop 44 set again by the burst start signal BST.

The output of the flip-flop 44 thus shows the common "compressed" test result TR of a block of 2 read data words, which stem from two data accesses, each for the duration of the second half period of the slow clock CLK. The output of the flip-flop 44 is connected via the data connection Dn to the test result input TR of the test device 90 . The sampling of the test result can be done at the reporting circuit 93 in every second half period of the slow clock CLK by the correspondingly slow strobe signal STR with half the frequency of the data accesses, and yet none of the data accesses is ignored.

In order to generate the switching signals S1, S2, S4 for the switches 16 , 32 , 41 and the counting pulses S3 for the address counter 22 , the test auxiliary device contains a switching signal generator 30 , which is caused by the test mode setting signal TM, these switching signals from the internal clock signal CLKi and from the write and read operating signals WRD and RDD, respectively, which in turn are supplied by the control part 19 of the memory circuit 70 . In normal operation of the memory circuit 70 , the signal TM is kept ineffective, so that the internal clock CLKi runs freely or (in the case of a synchronous DRAM) is synchronized by an external fast clock or is set. This causes the internal clock 20 to generate CLKi at the same frequency as CLK, and the switching signal generator 30 is caused to generate the switching signals so that switches 32 and 41 are kept open and switch 16 (data port) in is keyed in a manner synchronized with the clock CLKi in order to clock the input and output of the data.

A test mode according to the invention is described below using the example of the memory circuit 80 shown in FIG. 3, which is a DRAM memory circuit operating at double data rate (DDR-DRAM).

The memory circuit 80 is integrated on a semiconductor chip, the boundaries of which are illustrated by the dashed frame and which, in a similar manner to the memory circuit 70 according to FIG. 1, has data connections D1 to Dn for the parallel input and output of n parallel data streams, addresses sen connections A0 to Ak for applying address bits, a connection for applying an external clock signal CLK and inputs for command bits CB [1: c].

The known components of the memory circuit 80 include: a memory bank 10 with a plurality of memory cells arranged in rows and columns, divided into two memory areas 10 a and 10 b; a data port symbolically represented as an n-pole line switch 16 between the data connections D [1: n] and an internal data bus 17 for the parallel transmission of n-bit data streams; a demultiplexer / multiplexer shown as an n-pole switch 23 for connecting the data bus 17 either with a first n-bit branch bus 17 a, which leads to a first n-bit latch 18 a, or with a second n-bit Branch bus 17 b, which leads to a second n-bit latch 18 b; Row and column address buffers 12 and 14 for providing the row and column address bits received via the address connections A [0: k] on a row and a column address bus 13 and 15 , respectively; one responsive to the clock signal CLK and the mentioned command bits, the control part 19 for supplying various control signals; a selection device 11 , which responds to control signals from the control part and to the address bits provided in each case, in order to establish connections between selected memory cells in the areas 10 a and 10 b and the latches 18 a and 18 b for writing and reading out memory data via the branch buses 17 a or 17 b.

In addition to these known components, the memory circuit 80 contains a test auxiliary device according to the invention, consisting of a switching signal transmitter 50 , two n-pole line switches 52 a and 52 b and an evaluation device 60 , which contains a 2n-pole line switch 61 and a comparator 62 . The switching signal generator 50 can be brought into a test mode by a test mode setting signal TM, in which it delivers switching signals in a time-controlled manner for actuating the switches 16 , 52 a, 52 b and 62 for a test operation. If the signal TM is ineffective, the switching signal generator 50 is in a “normal mode” in which it supplies the switching signals in a different timing in order to allow normal storage operation. The time diagram drawn in FIG. 4 illustrates the normal operation in its upper half and the test operation of the memory circuit 80 in its lower half.

In normal operation of the memory circuit 80 , the switches 52 a, 52 b and 60 are kept open. The normal operation of a DDR DRAM memory circuit of the type shown in Fig. 3 is well known and therefore need not be explained in detail. Therefore, here is just a brief summary of this normal operation:
In normal write operation, the data to be stored are created in the form of n-bit parallel words at the data connections D [1: n] with a data rate (repetition frequency of the data words) which is twice the rate of the clock CLK. The switch 16 is keyed synchronously with the data rate by being temporarily closed both with the rising edge and with the falling edge of the clock signal CLK in order to pass the data words one after the other onto the data bus 17 . From there, the data words reach the n-pole changeover switch 23 , which in this case works as a demultiplexer and is controlled by a switching signal S23 in a manner synchronized with the clock signal CLK. Syn chronized with the rising clock edges, the switch 23 goes into the bold position a, in which it connects the data bus 17 to the branch bus 17 a. Synchronized with the falling clock edges, the changeover switch goes into the position b shown in dashed lines, in which it connects the data bus 17 to the branch bus 17 b. Thus, the data words are loaded alternately into the latch 18 a and the latch 18 b. Within every second half of the cycle, that is, with a sequence frequency corresponding to the simple clock rate, the selection device 11 is caused by the control part 19 via control lines 21 , an n-bit write connection from the latch 18 a to a selected group of n memory cells in the area 10 a to produce and at the same time to produce an n-bit write connection from the latch 18 b to a selected group of n memory cells in the area 10 b, the selection taking place as a function of the address bits which are provided in this regard with regard to the address buses 13 and 15 , In this way, two successively received n-bit data words are written simultaneously to different memory cell groups in the memory matrix 10 .

In normal reading operation, the selective accesses also take place with the simple clock rate of CLK, and in each case simultaneously to two different memory cell groups (one in the area 10 a and the other in the area 10 b), similar to that in the writing mode. Thus, in the two lat ches 18 a and 18 b there are always two read data words for the duration of one clock period, each one after the other via the changeover switch 23 , which in this case acts as a multiplexer, with the double clock rate to the data connections D [1: n] ge can be delivered.

The test operation of the memory circuit 80 according to the invention will now be described. The already mentioned auxiliary device, the elements of which are identified by the reference numbers 50-66 , is used to implement the test operation. The test mode is implemented by connecting a test device 90 , as has already been described with reference to FIG. 1, and by applying the test mode setting signal TM to the switching signal transmitter 50 .

The test mode includes a write mode and a subsequent read mode with evaluation of the read data. The address, control and clock information are derived from the connected test device 90 via the internal address buffers 12 , 14 and the internal control part 19 . The clock CLK of the test device is half as fast as the data rate for which the memory circuit 80 is specified.

First, the write operation of the test mode will be explained. The test write operation, the sequence of which is illustrated in the lower left part of FIG. 4, runs for the duration of a write operation signal WRD provided by the control part 19 . This signal causes the switching signal generator 50 to keep the scarf ter 16 and 61 open by means of the switching signals S1 and S6 and to keep the switches 52 a and 52 b closed by means of the switching signal S5. Thus, all data connections D [1: n] are separated from the data bus 17 , and the data connection D1 is via a bridging line 51 and the closed switches 52 a and 52 b simultaneously with all n lines of the first branch bus 17 a and with all n lines of the second Connected branch bus. In time with the clock signal CLK, the test device 90 supplies successive test write data q1, q2, q3, etc., each consisting of a single bit with the binary value "0" or "1", to the data input D1 and successive address information to the address connections A [ 0: k].

Each test write data q1, q2, q3 arrives from the data connection D1 via the line 51 and the two closed switches 52 a and 52 b in each case simultaneously on all n lines of the branch bus 17 a and on all n lines of the branch bus 17 b. The latches 18 a and 18 b thus simultaneously provide two n-bit data words for the duration of one clock period, the bits of which all have the same value "0" or "1", depending on the binary value of the respective test write date. Thus, in each period of the clock signal CLK, the respective test date is simultaneously written in all memory cells of those memory cell groups in the areas 10 a and 10 b, which are determined by the respective address information.

After several or all (generally: a plurality i) of memory cell pair pairs of the matrix 10 having the same date "0" or "1" within each pair have been filled in this manner, the test read operation described below begins, the flow of which is on the right 4 is illustrated below in FIG . During the test read operation, which runs for the duration of a read operation signal RDD provided by the control part 19 , the switch 16 remains open, and the switches 52 a and 52 b are also open. Of the 2n-pole switch 61 is closed to all 2n INTR the two branch buses gen 17 a and 17 b now with a 2n-bit signal input of the comparator 62 to be connected.

In test read mode, the test device 90 in turn delivers the successive test data q1, q2, q3, etc. from its test data output TD at the CLK clock rate to the data connection D1, and at the same rate it delivers the respective address information to the connections A [0: k]. The test program ensures that the assignment of the binary value of this test data to the address information is the same as in the test write operation described above. From the terminal D1, the test data arrive because of the open state of the switches 16 , 52 a and 52 b, however, neither on the data bus 17 nor on the branch buses 17 a and 17 b, but via a line 66 to a reference input of the comparator 62 .

In the first CLK clock period of the read operation, a first pair of memory cell groups is selected in the two memory areas 10 a and 10 b by the first address information, specifically the pair in whose memory cells the first test data q1 has been written. These two memory cell groups are read out simultaneously, and the n read data of the group of the area 10 a arrive as an n-bit data word R1a in the latch 18 a, while the n read data of the group of the area 10 b as an n-bit data word R1b in the Latch 18 b arrive. Then, in the second clock period, when the second address information is created, a second pair of memory cell groups is selected in the two memory areas 10 a and 10 b, specifically the pair in whose memory cells the second test date q1 has been written. These two memory cell groups are read out simultaneously, and the n read data of the group of the area 10 a arrive as an n-bit data word R2a in the latch 18 a, while the n read data of the group of the area 10 b as an n-bit data word R2b in the Latch 18 b arrive. This game continues, so that the latch pair 18 a, 18 b one after the other provides a single 2n-bit read data blocks of 2 simultaneously appearing n-bit data words R1a + R1b, R2a + R2b, R3a + R3b, etc. ,

The flow of this 2n-bit blocks of data passes via the branch buses 17 a and 17 b and the closed 2n-pole switch 61 to 2n-bit signal input of the comparator 62nd The comparator delivers a logic "1" at its output if and only if all 2n bits at the signal input have the same value as the test data bit at the reference input. Thus, the comparator 62 compares the 2n-bit data block R1a + R1b with the test data q1 in the first CLK clock period. If there is no error, then all 2n bits of this data block are equal to q1, and the comparator delivers as the first test result X1 a logical "1"("testpassed") via a line to the data connection Dn, which is connected to the test result input TR of the Tester 90 is connected; otherwise a "0" is returned as test result X1 ("test not passed"). Then, in the next clock period, the comparator 62 compares the data block R2a + R2b with the test date q2 and delivers a "1" or a "0" as the next test result X1, depending on whether all n bits of the data block match the test date q1 match or not.

This game continues in a similar manner with the following 2n bit data blocks and test data. Thus, "compressed" test results of two data accesses appear at the rate of the clock signal CLK at the test result input TR of the test device 90 . The sampling of the test result at the signaling circuit 93 can thus be carried out by the strobe signal STR at the CLK rate, and although the memory circuit 80 runs as fast as in normal operation, ie performs two data accesses in each clock period, none of the data accesses is ignored.

Since in the test mode according to the invention the function of the multiplex switch 23 is neither necessary during reading nor during writing, this switch is preferably kept in idle state during the entire test mode. This shutdown in test mode can be initiated by a corresponding Si signal from the switching signal generator 50 .

The invention is of course not based on the figures described embodiments, the only Examples are. Modifications are possible, among other things obviously the number m of data accesses or memory cells groups, each from a single compressed test result to be included. This number m is described in the Examples above are equal to 2, but can also be higher preferably an integer power of 2. Correspondingly the ratio of the clock rates is of course multiplied from CLKi and CLK and the burst length in the case of one for one times the data rate designed memory circuit and the number the branch buses and the width of the comparator signal input in the case of a memory designed for multiple data rates circuit.  

In the case of a memory circuit designed for multiple data rates, a test auxiliary device according to the invention can of course also use an internal address counter, as is indicated in FIG. 3 with the address counter 22 shown in broken lines. In such a case, the comparator 61 in the evaluation circuit 60 can be followed by a similar arrangement to an RS flip-flop 44 (indicated by dashed lines in FIG. 3), as described above with reference to FIG. 1. In such an embodiment, the "compression factor" m, that is the number of memory cell groups that comprise the compressed test result, is not equal to the number of branch buses, but additionally increased by a multiplier that is equal to the burst length r of the address counter 22 counted address bursts. That is, the "compression factor" m is equal to the product pr if p is the number of branch buses and r is the burst length.

Instead of the RS flip-flop 44 shown in FIGS. 1 and 3, any other circuit arrangement can also be used to link the r partial results of a burst of r in succession to one another in such a way that the compressed test result is available after all these partial results have been obtained. It is also possible to save all r partial results of a burst, for example by entering them in an r-stage shift register, and to link them in parallel in an AND gate at the end of the burst.

For all embodiments, the order of the ad Test reading is not necessarily exactly the same che must be like the test write operation. The important thing is that the same test data bit be with each read address is provided on the same as in the previous letter Address.

The inherent system delays due to run times and  Settling processes are in the description and in the slides For the sake of simplicity and clarity, taken into account. In practice, the expert is of course ge common compensation delays in the signal clock and Da pathways to ensure accurate and correct timing to ensure the switching functions.

In the case of multiple memory banks within the memory shell The line and column addresses are of course added a bank address to the individual banks for test operation to address selectively.

The line and changeover switches used are symbolically represented in FIGS. 1 and 3 as mechanical switches. In reality, semiconductor switches are used, mostly in a MOSFET structure.

LIST OF REFERENCE NUMBERS

10

memory bank

11

selection means

12

Row address buffer

13

row address bus

14

Column address buffer

15

Spaltenadressenbus

16

line switch

17

bus

17

a,

17

b Branch buses

18

.

18

a,

18

b Latches

19

control part

20

clock

22

address counter

30

Switching signal generator

31

bypass line

32

line switch

40

evaluation

41

line switch

42

comparator

44

RS flip-flop

46

Test data line

50

Switching signal generator

51

bypass line

52

a,

52

b Line switch

61

line switch

62

comparator

66

Test data line

90

tester

91

Test sequence controller

92

Test Clock

93

register circuit

Claims (7)

1. A method for testing a RAM memory circuit which contains a plurality of memory cells, each of which can be selected in groups of n ≧ 1 memory cells by an applied address information in order to write or read groups of n data each, characterized by the following steps :
in a write cycle, a plurality i = jm of the memory cell groups is selected, where j and m are each integers ≧ 2, and the same data is written on all memory cells of each m selected memory cell groups;
in a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read out in such a sequence that the data groups read out of m memory cell groups, on which the same date has been written in, are simultaneously or immediately provided as a read data block, which includes mn data;
Each time a read data block is provided, a compressed test result is determined and made available, which indicates whether all the mn data of the read data block provided matches the written date. 2. Test auxiliary device for testing a RAM memory circuit, which has a multiplicity of memory cells, an input / output device (D [1: n], 16) for receiving and outputting memory data and an address input (A [0: k]) for creating address information and having a selection device ( 11 ) to select groups of n ≧ 1 memory cells depending on the address information applied and to write or read out a group of n data on the respectively selected memory cell group, marked by
a test control device ( 30-34 ; 50-52 ) for applying such control, data and address information to the selection device ( 11 ) that a plurality i = jm of the memory cell groups is selected in a write cycle, j and m being integers in each case ≧ 2, and the same data (e.g. q1) is written to all memory cells of every m selected memory cell groups, and that in a subsequent read cycle the i memory cell groups selected in the write cycle are selected and read out in such a sequence that the read out data groups, each consisting of m memory cell groups, on which the same date has been written in, are provided simultaneously or immediately in succession as a read data block which comprises mn data;
an evaluation device ( 40 ; 60 ) which, each time a read data block is provided (e.g. R1 ₁ , R1 ₂ ; R1a, R1b), ascertains and provides a compressed test result (e.g. X1) which indicates whether all mn data of the read data block provided coincide with the registered date. 3. Test auxiliary device according to claim 2 for testing a RAM memory circuit, which has a clock ( 20 ) for generating a clock signal (CLKi) and is designed for normal operation with a data rate equal to the rate of the clock signal and in which the input / output -Device (D [1: n], 16) via an n-bit data bus ( 17 ) can be connected to the selection device ( 11 ), characterized by
an address changer ( 22 ) which generates a sequence of m different addresses for the selection of m different memory cell groups from the address information at the rate of the clock signal (CLKi),
Switching means ( 32 , 41 ) which connect all lines of the data bus ( 17 ) in the write cycle to a test data connection (Dn) for applying a test data bit and connect them to the evaluation device ( 40 ) in the read cycle,
Means ( 42-46 ) in the evaluation device ( 40 ) in the read cycle with the same all bits of the n-bit data words that appear in m directly on successive periods of the clock signal (CLKi) on the data bus ( 17 ) Compare test data bit and provide the result at the end of this comparison process as a compressed test result. 4. Test auxiliary device according to claim 2 for testing a RAM memory circuit, which is designed for normal operation with a data rate equal to m times the rate of a clock signal (CLK) of the clock signal and in which m parallel n-bit branch buses ( 17 a, 17 b) are provided which lead to the selection device ( 11 ) and can be cyclically connected to the input / output device (D [1: n], 16) via a multiplexer ( 23 ) which can be switched with the data rate, the selection device ( 11 ) at the rate of the clock signal (CLK) is controllable to simultaneously from m disjoint areas ( 10 a, 10 b) of the memory bank ( 10 ) each have a memory cell group for each of the m branch buses ( 17 a, 17 b) select, marked by
a comparator ( 62 ), which has an mn-bit signal input and a reference input for receiving a test data bit and shows at the output as a compressed test result whether all bits of the mn-bit signal input match the test data bit,
Switching means ( 52 a, 52 b, 61 ) which connect all lines of all m branch buses ( 17 a, 17 b) in the write cycle to a test data connection (Dn) for applying a test data bit and in the read cycle to the nm bit signal input of the comparator ( 42 ) connect the evaluation device ( 40 ). 5. test auxiliary device according to one of claims 2 to 4, characterized in that m is 2 or an integer other potency is <1 of 2. 6. Test auxiliary device according to claim 2 for testing a RAM memory circuit, which is designed for normal operation with a data rate equal to p times the rate of a clock signal (CLK) of the clock signal and in which p parallel n-bit branch buses ( 17 a, 17 b) are provided which lead to the selection device ( 11 ) and can be cyclically connected to the input / output device (D [1: n], 16) via a multiplexer ( 23 ) which can be switched with the data rate, the selection device ( 11 ) at the rate of the clock signal (CLK) is controllable to simultaneously from p disjoint areas ( 10 a, 10 b) of the memory bank ( 10 ) each have a memory cell group for each of the p branch buses ( 17 a, 17 b) select, marked by
an address changer ( 22 ) which generates from each address information a sequence of r different addresses at the rate of the clock signal (CLKi) for the selection of r different memory cell groups in each of the p areas ( 10 a, 10 b) of the memory bank ( 10 ),
a comparator ( 62 ) which has a pn-bit signal input and has a reference input for receiving a test data bit and displays a partial result "test passed" at the output precisely when all bits of the pn-bit signal input match the test data bit,
Switching means ( 52 a, 52 b, 61 ) which connect all lines of all p branch buses ( 17 a, 17 b) in the write cycle to a test data connection (Dn) for applying a test data bit and in the read cycle to the pn bit signal input of the comparator ( 42 ) connect the evaluation device ( 40 ),
means ( 43-46 ) which, as a compressed test result, indicates whether all the r partial results which have been delivered in r directly following consecutive periods of the clock signal (CLKi) indicate "test passed". 7. test auxiliary device according to one of claims 2 to 6, characterized in that it is compatible with all parts of the memory Cherschaltung is integrated on the same semiconductor chip.