DE10216909C1 - Transistor voltage level converter circuit for memory decoding circuits has input and output lines and outputs voltage level lower than low state and voltage level higher than high state - Google Patents

Abstract

The circuit outputs voltage levels lower than the low state and higher than the high state. Two transistors of a first conductivity type have first connections connected to a supply voltage higher than a positive supply voltage. A negative supply voltage is connected to a third transistor of a second type. Fourth and fifth transistors of the second type have first connections connected to a voltage lower than the negative supply voltage. The circuit has input and output lines and outputs a voltage level lower than the low state and a voltage level higher than the high state. First and second transistors (P1,P2) of a first conductivity type have first connections connected to a supply voltage (VPP) higher than a positive supply voltage (VDD). A negative supply voltage (VSS) is connected to a third transistor (N3) of a second conductivity type and fourth and fifth transistors (N1,N2) of the second type have first connections connected to a low voltage lower (VWL) than the negative supply voltage.

Description

The invention relates to a voltage level converter circuit for an input signal for driving a word line ei integrated memory.

Integrated memories have memory cells, the matrix are arranged in a shape and over word lines and bit lines conditions can be described or read out. At the address sation of a memory cell becomes a word line address ü Decoded via an address decoding circuit, so that depending on One word line from all word lines apply to the address is selected.

The address decoding circuits are preferably on the edge of the arranged cell arrays formed by the memory cells. First of all, it is necessary for the address decoding circuit to the grid of the cell array in two or quadruple stacking needs to adjust. Second, it is necessary dig that voltage level available on the word lines can be set, their low level more negative than a low supply voltage potential of the logic circuits and its high level is more positive than a high supply voltage potential is VDD.

The need for one versus the low supply voltage potential a reduced voltage level for the To provide low state of the word lines, he results from the fact that the selection transistor of the DRAM Must uniquely lock the memory cell. This is particularly so with decreasing control voltage differences for Spei transistor become necessary. By the degraded Voltage level on the word lines must have a negative gate Source voltage at the selection transistor of the memory cell  so that even with low supply Tensions locks.

The need for one versus the high supply span voltage potential increased voltage on the word line for ver to provide, it follows that the full cell information is written back into the memory cells have to. This is particularly possible if the Spei chertransistor between a storage capacity and the bit lines switched through completely. The switching through will usually with the help of an increased control voltage on Memory transistor reached.

There is also a need to increase the percentage of the periphery circuits, d. H. Circuits for controlling the cells field, to keep it as low as possible in order to efficiency. Address decoding circuits belong to such peripheral circuits and can make up about 10% of the total take up chip area. Since the address decoding circuits for each word line has an individual selection circuit, affects there in particular the reduction in the number of Components positive for the space requirements of the periphery circuits off. Furthermore, the area of the selection scarf can also be reduced by the fact that only a few crosses make wiring within such a circuit are. This determines the need for a simple ting, double or quadruple staggering in the layout.

Address decoding circuits are usually used for control purposes Word lines of a memory circuit with two of mutually separate voltage level converters that built each have an output line. The first exit Line sets for the high state versus the high Supply voltage potential (VDD) increased voltage potential tial available, with the low span the low span voltage level about the low supply voltage potential, z. B. corresponds to the ground potential. The second exit line  device adjusts to the low supply voltage low voltage potential available where at the high voltage level about the high supply voltage potential corresponds. When controlling the two Output lines are especially the internal timing between the signals on the output lines, d. H. the signals on the output lines must not differ overlap so that a time reserve must be planned whereby the speed of random access to the Memory circuit is reduced. It also requires a structure of such an address decoding circuit with two Voltage level converter circuits a large number of tran sistors that take up a large area in the layout. Wei a switch must also be provided, which depending on the Be either the first or the second output line to the word line.

A voltage level is known from the publication US Pat. No. 5,617,369 converter circuit for driving a word line driver for driving a word line of a memory circuit known. The voltage level converter circuit includes an on gangsleitung and an output line, being on the off a lower span compared to the low state voltage level and a higher voltage than the high state voltage level can be output.

It is an object of the present invention to provide a voltage pe gel converter circuit for driving a word line to provide that takes up little space and that Control signal available on only one output line provides a drive signal with an increased span voltage level and a reduced voltage level is posed.

This task is accomplished by the voltage level converter circuit solved according to claim 1.  

The voltage level converter circuit according to the invention serves the control of a word line of the integrated memory and provides an output signal that consists of a Input signal is generated, and in a high state one compared to the high supply voltage potential or the high state of the input signal increased voltage level and in the low state one compared to the low supply voltage potential or the low state reduced span level.  

There are a first and a second transistor with a first th conductivity type provided, the first connections with increase compared to the high supply voltage potential ten voltage levels are connected. The output line of the Voltage level converter circuit is with a second on circuit of the first transistor and a control input of the second transistor connected. A second connection of the second transistor is connected to a control terminal of the first Transistor and with a first terminal of a third Transistor connected to a second conductivity type. On a second connection of the third transistor is low supply voltage potential and at a control input the input of the third transistor. It is a fourth and a fifth transistor of the second Conductivity type provided, the first connections with the compared to the low supply voltage Voltage levels are connected. The output line is with a second connection of the fourth transistor and with a Control input of the fifth transistor connected. A second Connection of the fifth transistor is with a control circuit of the fourth transistor and with a first on circuit of a sixth transistor with the first conductive connected type. On a second connector of the sixth Transistor is the high supply voltage and on one Control input of the sixth transistor on the input signal placed.

The circuit according to the invention contains only one voltage pe gel converter circuit, which in contrast to the previous Voltage level converter circuits used to drive Word lines are used with fewer transistors has. As a result, the voltage level Converter circuit according to the invention less space on the Integrated circuit required and is therefore the Percentage of area of peripheral circuits in integrated memory to reduce circuits. In addition, he points out  inventive voltage level converter circuit only one Output line on, which increases the switching speed can be because of an internal timing between two signals on two different output lines that do not overlap pending may no longer be necessary.

The use of the circuit according to the invention resulted in a smaller space requirement of approx. 6% based on the total Chip because a smaller number of transistors are used becomes.

The line routing from the word line decoding circuit to Word line driver only exists in one output line instead of two. Thus, the cross wiring effort can be re be reduced and thereby reduce the capacitive load be tied. This is particularly interesting for a shared Row decoder variant, i. H. to control one cell each lenfeld with only one address decoding circuit and one Voltage level converter for two word line drivers that are lying opposite.

The voltage difference between the high level and the low Output signal level is greater than each of the separate ones Level of the two output lines of the previous voltage pe gel conversion circuits. This will become the word line drivers transistors better controlled, so either the width the word line driver transistors with the same Access time can be reduced or stay the same the width of the transistors the access time can be reduced can, in which the edge steepness of the output signal on the Output line is improved. In addition, he can voltage level converters according to the invention are compatible with the up to be used, so that in existing designs the improved solution can be installed without An control signals in their logical and temporal function countries.  

Advantageous embodiments of the invention are in the depend given claims.

According to a further embodiment of the invention, a seventh transistor with the first conductivity type hen between the output line and the second line circuit of the first transistor is arranged. On his An inverted input signal is applied to the control connection. The voltage level converter circuit also has one eighth transistor with the second conductivity type on between the output line and the second connection of the fourth transistor is arranged, being at its Steueran finally the inverted input signal is applied.

The provision of the seventh and eighth transistor has the Advantage that the switching behavior, especially the edges steepness of the voltage level converter circuit and the span difference VPP-VDD or VWL-VSS is improved. So can the driver strength of the third or sixth transistor at Provision of the seventh and eighth transistor less planned than when the seventh and eighth transis are omitted tors because the third or sixth transistor is not as strong must drive against the second or fourth transistor in order to switch the voltage level converter circuit chen. It is preferably provided that an input driver circuit for driving the input signal with two ge mutually connected inverter circuits is provided. This is due to an input of the input driver circuit inverted input signal at and at the output of the input driver circuit the output signal. Preferably that is inverted input signal from a word line deco The circuit is provided, used to the to drive the seventh or eighth transistor. This eliminates the need to add another inverter within the To provide voltage level converter circuit, thereby further Chip area can be saved.  

It can preferably also be provided that, on the basis of its the same size of the first and the seventh transistor or the fourth and the eighth transistor in a dual-gate Transistor are summarized. This allows the wiring processing costs can be further reduced, thereby reducing chip area can be saved.

The preferred embodiment of the invention will follow the explained in more detail with reference to the accompanying drawings. It demonstrate:

FIG. 1 shows an inventive voltage level conversion circuit according to a first embodiment of the invention;

Fig. 2 is a circuit diagram of voltage level converting circuit according to a second embodiment of the invention; and

Fig. 3 is a circuit diagram of a voltage level converter circuit according to a third embodiment of the invention.

In Fig. 1, a voltage level converter circuit is to control to a word line WL for an integrated SpeI cher, shown in particular for a DRAM memory. The voltage level converter circuit is located between an address decoding circuit 1 and a word line driver 2 , with which the output signal from the voltage level converter circuit is driven to the corresponding word line WL.

The voltage level converter circuit is essentially composed of a first, second and third transistor P1, P2, P3 of a first conductivity type and a fourth, fifth and sixth transistor N1, N2, N3 of a second conductivity type. The p-type first transistor P1 is connected with its first connection to a supply voltage VPP which is higher than the supply voltage VDD which is customary in the integrated memory circuit. A second connection of the first transistor P1 is connected to the output line A, which is connected to an input of the word line driver 2 . The word line driver amplifies the signal present on the output line A for driving the word line WL and additionally performs a partial decoding, ie the word line driver not only serves to amplify the signal but also for decoding the selection of the word lines.

A first connection of the second p-type transistor P2 is also ver with the increased supply voltage VPP prevented. A second connection of the second transistor P2 is at the same time with a control input of the first transistor P1 and a first connection of the sixth n-type transistor tors N3 connected. A second connection of the n-type sixth transistor N3 is with the low supply voltage potential connected VSS, which is usually in the Memory circuitry is used and is usually grounded potential GND is. A control input of the second p- conductive transistor P2 is connected to the output line A prevented.

A first connection of the n-type fourth transistor N1 is with a compared to the low supply voltage VSS reduced supply voltage VWL connected. A second Connection of the fourth transistor N1 is at the output line device A connected. A first connection of the n-type fifth transistor N2 is also with the lowered Supply voltage potential VWL connected. A second type circuit of the fifth transistor N2 is both with a control er input of the n-type fourth transistor N1 and with egg nem first connection of the p-type third transistor P3 connected. A second port of the p-type third Transistor P3 is at the high supply voltage potential VDD connected to the logic circuits of the integrier th memory circuit usually provided is.

Control inputs of the third p-type transistor P3 and the sixth n-type transistor N3 are connected via an inverter circuit 3 to the word line decoding circuit 1 . The inverter circuit 3 has two mutually connected inverters 4 and 5 . The mutually connected inverters 4 , 5 firstly have the effect that the edge steepness of the inverted signal EI is improved compared to the input signal E coming from the word line decoding circuit 1 , and secondly that the row address can be stored, since the voltage level converter circuit also has a memory function has. The inverter circuit 3 is necessary because the word line driver circuit inverts the output signal present at the input on the output line A. In this way, a non-inverted signal can be given to the word line driver 2 on the output line A of the voltage level converter circuit compared to the input signal E generated by the word line decoding circuit 1 .

The voltage level converter circuit either switches it increased supply voltage potential VPP over the first train sistor P1 or the reduced supply voltage potential VWL via the fourth transistor N1 to the output line by. An output signal is therefore available that the high voltage level VPP and the low voltage level VWL in the low state has.

This has the advantage that the stroke of the output signal increases the output line A is larger than the stroke of usual Voltage level converter circuits that have two separate off have passage lines. There is one line each either just an elevated high or a lowered Low state provided. By the enlarged The output of the output signal becomes the word line driver sistors controlled better, so that there either the width of the transistors with the same access time to the built-in memory can be reduced or the  Access time can be reduced if you look at the breadth of the Maintains transistors.

The switching of the first transistor P1 is on signal applied to the control input. The control of the control input of the first transistor P1 is via the sixth transistor N3 performed. Depending on the in vertical input signal EI at the control input of the sixth transistor N3 becomes the low supply voltage po tential at the control input of the first transistor P1 puts or not. If the sixth transistor N3 is blocked, i. H. when an inverted input signal EI is present in the low Condition, so is the increased supply voltage potential via the second transistor P2, which is due to the low state of the output signal is switched through. So lies above that second transistor P2 the increased supply voltage potential tial at the control input of the first transistor P1, so that it is blocked due to its p-conductivity.

The low state of the inverted input signal EI causes that the high supply voltage potential VDD over the third transistor P3 at the control input of the fourth Tran Sistor N1 is applied so that it is switched through. As a result, the reduced supply voltage potential is VWL via the fourth transistor N1 on the output line sets. So that the third transistor P3 not against the fifth Must drive transistor N2, is the fifth transistor N2 its control input with the output line, d. H. with the Low state of the output signal connected, so that this ge is locked.

Accordingly, there are reversed switching states if that inverted input signal is in the high state, see above that the third transistor N3 is turned on and that low supply voltage potential VSS at the control units Gear of the first transistor P1 is present and thereby turns on. Then there is the increased supply voltage po  potential VPP on the output line A; the fourth transis gate N1 is due to the blocked transistor P3 and turned on transistor N2 turned off.

The voltage level converter circuit according to the invention has versus voltage level converter circuits for word lines according to the prior art, a significantly smaller number of transistors so that their area is reduced can. This is particularly advantageous because such Voltage level converter circuits in large numbers, namely for each word line, the integrated memory circuit for Must be made available.

Such a voltage level converter circuit is compared to that State-of-the-art voltage level converter circuit with two output lines faster, since not pay attention to it It must be ensured that the output signals do not overlap pen. In addition, such a voltage level Converter circuit compatible with the existing voltage pe gel converter circuits, since the control signals are in their logical and temporal function do not change. So can the voltage level converter circuit according to the invention in be standing designs can be incorporated without problems.

In FIG. 2, a further embodiment of a fiction, modern voltage level converter circuit is shown. The embodiment shown in FIG. 2 differs from the first embodiment according to FIG. 1 in that the second connection of the first transistor P1 is not connected directly to the output line A, but via a seventh p-type transistor P4 to the output line A. is. For this purpose, a first terminal of the seventh transistor P4 is connected to the second terminal of the first transistor P1. The second terminal of the seventh transistor P4 is connected to the output line. In the same way, the second connection of the fourth transistor N1 is not connected directly to the output line, but via an eighth n-type transistor N4 to the output line. The control inputs of the seventh transistor P4 and the eighth transistor N4 are connected to the inverted input signal via an inverter 6 , so that the non-inverted input signal is essentially present at the control inputs.

In the first embodiment, the dimensioning of the sixth transistor with respect to the second transistor P2 be careful that the driver strength of the sixth Transistor N3 compared to the driver strength of the second Tran transistor P2 is significantly higher. The same applies to the third th transistor P3 compared to the fifth transistor N2. The sixth transistor N3 must be switched on, for example tem second transistor P2 the level of the control input of pull first transistor P1 to VSS. So that this quickly The driver strength of the sixth transistor versus the driver strength of the second Transistor P2 can be significantly increased. A higher driver strength ke is achieved by larger transistors.

By providing the seventh transistor P4 and the eighth Transistor N4 is the switching behavior of the voltage level Supported converter that already before the scarf th of the first transistor P1 and the fourth transistor N1 these are separated from the output line and thereby help that the sixth transistor N3 and the third Tran sistor P3 not against the second transistor P2 or the fifth transistor N2 must work. The transistors P2 and N3 as well as P3 and N2 can therefore have the same driver strength be dimensioned, which saves additional space leaves.

In addition, the seventh transistor and the eighth tran support sistor a faster switching of the signal on the output line because the current paths through the first transistor P1 and the fourth transistor N1 are disconnected faster, so  that a significantly faster rise time on the output line can be provided.

In a third embodiment, which is shown in Fig. 3, the inverter 6 is dispensed with by the input signal from the address decoding circuit 1 being connected directly to the control inputs of the seventh transistor and the eighth transistor. By replacing the inverter 6 with a cross connection between the input signal E and the control inputs of the seventh and eighth transistors P4, N4, further area can be saved, which further reduces the overall space requirement of the voltage level converter.

The first transistor can be used to save further area and the seventh transistor P1, P4 as well as the fourth transistor gate and the eighth transistor N1, N4 as a dual gate Transistors are running so that more area that would otherwise be necessary for the wiring, who saved that can.

Because the inverter 6 is not used, the seventh transistor and the eighth transistor switch before the input signal is present as an inverted input signal at the control inputs of the third transistor and the real transistor. This results in a further reduction in the switching time of the voltage level converter circuit.

Claims (8)

1. Voltage level converter circuit for driving a word line of a memory circuit via a word line device driver, the voltage level converter circuit comprising an input line and an output line, a voltage level which is lower than the low state and a voltage level which is higher than the high state can be output on the output line is characterized in that a first (P1) and a second transistor (P2) of a first conductivity type are specified, the first connections of which are connected to a supply voltage (VPP) which is higher than a high supply voltage (VDD), with an output line (A) is connected to a second terminal of the first transistor (P1) and a control input of the second transistor (P2), and wherein a second terminal of the second transistor (P2) is connected to a control terminal of the first transistor (P1) and to a first th connection of a third transistor (N3) of a two th conductivity type is connected, a low supply voltage (VSS) being applied to a second connection of the third transistor (N3) and the input signal (Ei) being applied to a control input of the third transistor (N3), and a fourth (N1) and a fifth transistor (N2) of a second conductivity type, the first connections of which are connected to a supply voltage (VWL) which is lower than the low supply voltage (VSS), the output line (A) having a second connection of the fourth transistor (N1) and is connected to a control input of the fifth transistor (N2), and wherein a second terminal of the fifth transistor (N2) is connected to a control terminal of the fourth transistor (N1) and to a first terminal of a sixth transistor (P3) of the first conductivity type is, at a second connection of the sixth transistor (P3) the high supply voltage (VDD) and at a control input of the sixth Most transistor (P3) the input signal (Ei) is applied. 2. Voltage level converter circuit according to claim 1, the egg a seventh transistor (P4) of the first conductivity typs that between the output line (A) and the second connection of the first transistor (P1) is arranged, with a control connection of the seventh Transistor (P4) an inverted input signal sets is, and the one eighth transistor (N4) of the second conductive type of connection between the output line (A) and the second connection of the fourth transistor (N1) is arranged, with a control connection of the eighth Transistor (N4) applied the inverted input signal is. 3. voltage level converter circuit according to claim 2, the egg ne input driver circuit ( 3 ) for driving the one input signal (E) with two mutually connected in verterschaltungen ( 4 , 5 ), wherein at an input of the input driver circuit ( 3 ), the input signal (E ) is present and at the output of the input driver circuit the inverted input signal (Ei). 4. voltage level converter circuit according to claim 3, wherein the input signal (E) from a word line decoding circuit ( 1 ) is provided. 5. Voltage level converter circuit according to one of the claims 2 to 4, the first (P1) and the seventh transistor (P4) and / or the fourth transistor (N1) and the eighth Transistor (N4) combined in a dual gate transistor are composed.   6. Voltage level converter circuit according to one of the claims 1 to 5, the potential of increased supply voltage (VPP) is chosen to be at least as large as the voltage the word lines (WL) connected selection transistor switch through completely. 7. Voltage level converter circuit according to one of the claims 1 to 6, the potential of the lowered Supply voltage (VWL) chosen at least as small is to the connected to the word lines To completely block the selection transistors. 8. Use of a voltage level converter switching according to ei nem of the preceding claims for controlling a Word line in a memory circuit.