DE102023206603A1 - Method for processing a semiconductor wafer and mounting template - Google Patents

Abstract

The invention relates to a method for processing a wafer (100) with providing the wafer with structures for a plurality of chips (120) and a first surface and a second surface opposite the first surface, providing a template (300) with a base (320) and one or more support structures (310) arranged thereon, separating the wafer into chips, each chip having a surface (122b) to be protected, removing the chips from the wafer, placing at least some of the removed chips on the one or more support structures of the template in order to achieve a desired arrangement of the placed chips such that the surfaces to be protected are directed towards the base of the template and are not in direct contact with the one or more support structures, and then connecting the placed chips to a common component, wherein the arrangement of the placed chips relative to one another is maintained.

Description

The present invention relates to the field of manufacturing chips from wafers, in particular for microelectromechanical devices, and concerns a method for processing a wafer and a template for placing chips.

State of the art

Devices with microelectromechanical systems (MEMS), such as micromirror arrays or micromirror actuators, are used today in a wide range of devices, for example in smartphones, projectors, head-up displays, barcode readers, mask exposure devices in semiconductor production and microscopes. Corresponding micromirror arrays are known, for example, from the documents DE 10 2013 208 446 A1 , EP 0 877 272 A1 and WO 2010/049076 A2 known. The DE 10 2006 032 195 A1 describes a process for the production of MEMS structures. In the DE 10 2009 029 202 A1 A micromechanical system and a method for producing a micromechanical system are disclosed. DE 10 2015 206 996 A1 The so-called EPyC process (EPyC: epitaxial polysilicon cycle) is known for the production of microelectromechanical structures with large vertical extension, which uses epitaxial polysilicon as functional and sacrificial material and builds up a layer structure of epitaxial polysilicon layers (EpiPoly layers) by means of repeating cycles.

When manufacturing individual microelectromechanical systems based on wafers, continuous protection of the microelectromechanical structures of these systems must be ensured in order to avoid unwanted damage to the MEMS chips. For this reason, surfaces to be protected are typically temporarily protected by suitable protective structures, which, however, greatly reduce the fill factor of the end product, i.e. the manufactured chips.

disclosure of the invention

According to the invention, a method for processing a wafer and a template for placing chips with surfaces to be protected are proposed.

According to a first aspect of the invention, a method for processing a semiconductor wafer (also referred to as wafer for short in the context of this invention) is proposed. The method comprises providing the wafer, which preferably has silicon or is made of silicon. The wafer has structures for a plurality of semiconductor chips (also referred to as chips for short in the context of this invention) as well as a first surface and a second surface opposite the first surface. The first and second surfaces are therefore the two different base surfaces of the wafer. Furthermore, an assembly template (also referred to as template for short in the context of this invention) is provided with a base, for example in the form of a base plate, and one or more support structures arranged thereon. After the wafer has been separated into chips, each chip having a surface to be protected, the chips are removed from the wafer. Each chip is therefore removed from the rest of the wafer (remainder of the wafer). A surface of a chip to be protected is a surface of the chip for which protection is sought. The one or more support structures of the template can, for example, have the shape of continuous or interrupted walls, arches, grids, struts and/or supports, which are preferably arranged in a grid. In particular, the one or more support structures can have the shape of one or more rectangular, triangular, hexagonal and/or trapezoidal frames and/or one or more rectangular, triangular, hexagonal and/or trapezoidal grids. In particular, in the case of several support structures, all support structures of the template can have the same shape, for example the shape of a rectangular, triangular, hexagonal or trapezoidal frame or a rectangular, triangular, hexagonal or trapezoidal grid.

Subsequently, at least some of the removed chips are placed on the one or more support structures of the template in order to achieve a desired arrangement, i.e. a position and alignment, of the placed chips such that the surfaces of the placed chips to be protected are directed towards the bottom of the template and are not in direct contact with the one or more support structures. Subsequently, the placed chips are connected to a common component such as electronics, whereby the arrangement of the placed chips relative to one another is maintained. The proposed method therefore serves to achieve an optimized and defined arrangement of the isolated chips relative to one another by means of a template. The template is preferably designed such that the chips are arranged in a common plane after being placed on the support structures and are leveled in particular with respect to an axis perpendicular to the surfaces to be protected.

Advantageously, the wafer has holding structures and/or before or during of singulating the wafer, forming holding structures in the wafer, wherein the holding structures are designed to restrict possible movements of the chips after singulation in at least one direction perpendicular to the first surface of the wafer. A holding structure can be formed, for example, by suitable projections (catching webs) of the chip and/or the rest of the wafer. A holding structure can be arranged, for example, on an edge of a chip to be released by singulation and/or be part of the rest of the wafer and ensures that the chip hooks onto the rest of the wafer after singulation has been carried out, thereby preventing the chip from moving freely in a direction perpendicular to the first surface of the wafer. In this way, for example, it can be prevented that chips fall out when the wafer is aligned horizontally (i.e. perpendicular to the direction of gravity). In this case, the holding structures, if they are part of the rest of the wafer, are preferably designed such that they do not touch the surface of the chip to be protected if they hook.

Furthermore, before the wafer is singulated, a gap structure enclosing individual chips and locally perforating the wafer can be formed in the wafer with a plurality of gaps, and the singulation can be carried out at least partially along these multiple columns. In this case, by forming the locally perforating gap structure, webs are preferably formed between the columns, which each run horizontally or vertically with respect to the first surface and hold the chips in the wafer. The webs therefore connect the chips to the rest of the wafer. During the singulation of the wafer, a gap structure enclosing individual chips and continuously penetrating the wafer can be formed in the wafer with one or more gaps, and the singulation can be carried out at least partially by forming the gap structure. In the case of a continuously penetrating gap structure, in contrast to a locally perforating gap structure, no webs are formed. A chip to be removed from the wafer is completely (in the case of a continuously penetrating gap structure) or partially (in the case of a locally perforating gap structure) separated from the rest of the wafer by forming the gap structure. This procedure ensures that the chip can later be easily removed from the wafer, for example when removing the chip from the protective device. In the case of the locally perforating gap structure, removing the chips can correspond to singulation, since here the singulation is achieved, for example, by simply breaking the webs; the chip is simply broken out of the wafer. By using a suitable laser cutting process, it is also possible to evaporate the webs. This has the advantage that the webs are completely removed without creating uncontrolled fragments of the webs. In the case of forming a continuously penetrating gap structure, singulation can therefore take place by forming the gap structure. Separate singulation is therefore not necessary. A gap structure can consist of recesses that are not connected to one another. For example, a gap-shaped recess can be guided around each individual chip, enclosing this chip. The entirety of these gaps is referred to as a gap structure in the context of this invention. A locally perforating gap structure is accordingly a gap structure in which the gaps do not form closed shapes, in contrast to a continuously penetrating gap structure. Separating the wafer by forming a gap structure in the wafer is particularly advantageous, since the release of particles that could lead to contamination of sensitive structures on the wafer can be completely avoided.

In the context of this invention, a gap structure is understood to mean one or more recesses in the wafer that completely penetrate it in the vertical direction. Separating a wafer along a locally perforating gap structure means separating it in such a way that several recesses in the gap structure are used to separate a chip from the rest of the wafer by destroying, for example breaking, any connections that still exist (for example in the form of webs) between the chip and the rest of the wafer. Gaps in gap structures can deviate from simple gaps that run vertically through the wafer, i.e. rectangular recesses and gaps; for example, areas of the gap that run horizontally, i.e. parallel to the first surface of the wafer, are conceivable. In particular, the gaps can be designed in such a way that at least locally holding structures are formed which, as described above, continue to fix the individual chips in the wafer after it has been separated, i.e. they specifically restrict the movement of the individual chips in a certain direction after separation, for example in order to prevent the individual chips from accidentally falling out of the wafer when the wafer is moved. Holding structures can exist both in the presence of a locally perforating gap structure and a continuously penetrating gap structure.

Preferably, the gaps and thus also the continuously penetrating gap structure and/or the locally perforating gap structure are formed by means of an etching process. The etching process used here can be, for example, reactive deep reactive ion etching (DRIE). Such an etching process is preferably combined with an etching process for exposing chip structures such as MEMS structures, for example a silicon sacrificial layer etching (also known as sacrificial layer etching), so that in one process step both the continuously penetrating gap structure and/or the locally perforating gap structure are formed and the chip structures are exposed. For example, the EPyC process can be used to create complex structures such as holding structures, which are exposed as part of such a sacrificial layer etching.

The structures for the chips preferably have MEMS structures for microelectromechanical systems (MEMS), wherein the surfaces to be protected are part of the MEMS structures. A chip with MEMS structures is referred to as a MEMS chip in the context of this invention. The MEMS structures are exposed before or during the separation of the wafer by sacrificial layer etching and preferably together with the formation of a gap structure that encloses individual chips and penetrates the wafer locally or continuously. It is particularly advantageous if these open MEMS structures comprise MEMS structures for a micromirror array.

According to a second aspect of the invention, a template for placing chips with surfaces to be protected is proposed, preferably for use in a method as described above. The template comprises a base, for example in the form of a base plate, and one or more support structures arranged thereon. The support structures are designed such that the chips can be placed on the one or more support structures such that the surfaces of the chips to be protected are not in direct contact with the one or more support structures.

Preferably, the one or more support structures have the shape of one or more rectangular, triangular, hexagonal and/or trapezoidal frames and/or one or more rectangular, triangular, hexagonal and/or trapezoidal grids, thereby defining recesses in the template that serve to place the chips and protect surfaces to be protected, for example MEMS structures. In particular, in the case of multiple support structures, all support structures of the template can have the same shape, for example the shape of a rectangular, triangular, hexagonal or trapezoidal frame or a rectangular, triangular, hexagonal or trapezoidal grid. The recesses defined by the one or more frames and/or the one or more grids preferably have one or more walls (for example a side wall or a bottom) with one or more channels that are suitable for applying a negative pressure or a vacuum in order to suck in the chips placed on the recesses. With the exception of such optional channels, the walls of the recesses are preferably gas-tight or have only a low permeability.

It is also conceivable that at least parts of the base of the stencil or preferably the entire base or the entire stencil are at least partially transparent to light in a wavelength range. In general, a stencil can have both transparent and non-transparent materials in a certain wavelength range. Light here means electromagnetic radiation in the visible range of the electromagnetic spectrum as well as ultraviolet and infrared radiation. This makes it possible to carry out optical tests and measurements on the individual chips. Accordingly, it is advantageous to use a material that is transparent in a desired wavelength range or at a desired wavelength for parts of the stencil, for example the base or parts of the base. Possible wavelength ranges are, for example, the UV range, the visible range and the IR range. Depending on the wavelength, the material can be selected so that transparency is achieved. Examples of suitable optical measuring methods are measurements with a white light interferometer (for example in the wavelength range from 400 to 800 nm) or with a laser vibrometer (for example at wavelengths of 633 or 1550 nm). At least part of the base of the template and preferably the entire base or the entire template can consist of glass or have glass. Examples of possible glasses are boron silicate glass, quartz glass or sapphire glass. Other transparent materials are also conceivable as an alternative to glass. For example, silicon can be used as an IR-transparent material for measurements in the IR range.

Advantages of the invention

The invention discloses a method and a device which are suitable for protecting semiconductor chips, for example MEMS chips, from damage and/or contamination in a manufacturing process of an assembly and at the same time ensuring a high fill rate.

The assembly template proposed and used in the process enables the chips to be separated from the underlying To arrange wafers in a predetermined manner and then process them further, for example to connect them to another common component. Such a process also enables a higher yield of the assembly to be produced, since the chips can be selected before being connected to the common component. If the stencil is optically transparent, the chips can be subjected to optical tests before and/or after being connected to another common component, for example using wafer level tests. Furthermore, an appropriately designed stencil enables the chips to be leveled in the axis perpendicular to the surfaces to be protected.

A further advantage is that a joining process such as gluing or bonding the chips to the stencil is typically not required. This means that the support structures can be made narrower than would be necessary, for example, if a protective cap were glued or bonded. This enables a higher fill factor than with many approaches known from the prior art. If desired, the stencil can be designed in such a way that a negative pressure or vacuum can be applied to temporarily fix the chips. By changing the stencil design, the arrangement of the chips in relation to one another and thus the layout of the assembly to be produced can also be adjusted cost-effectively.

Short description of the drawings

Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

• 1 eine schematische Darstellung eines Querschnitts eines Wafers mit Chips zur Veranschaulichung eines erfindungsgemäßen Verfahrens;
• 2 eine schematische Darstellung eines Querschnitts eines Wafers mit Chips bei Entnehmen der Chips entsprechend dem erfindungsgemäßen Verfahren;
• 3 eine schematische Darstellung von Chips bei einem Platzieren auf einer erfindungsgemäßen Schablone entsprechend dem erfindungsgemäßen Verfahren;
• 4 eine schematische Darstellung eines Querschnitts von in einer erfindungsgemäßen Schablone platzierten Chips, die entsprechend des erfindungsgemäßen Verfahrens mit einem gemeinsamen Bauelement verbunden werden; und
• 5 in schematischer Form als Flussdiagramm ein beispielhaftes erfindungsgemäßes Verfahren zum Verarbeiten eines Wafers.

They show:

• 1 a schematic representation of a cross section of a wafer with chips to illustrate a method according to the invention;
• 2 a schematic representation of a cross-section of a wafer with chips during removal of the chips according to the method according to the invention;
• 3 a schematic representation of chips being placed on a template according to the invention in accordance with the method according to the invention;
• 4 a schematic representation of a cross-section of chips placed in a template according to the invention, which are connected to a common component according to the method according to the invention; and
• 5 in schematic form as a flow chart an exemplary inventive method for processing a wafer.

embodiments of the invention

In the following description of the embodiments of the invention, identical or similar elements are designated with identical reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only represent the subject matter of the invention schematically. Furthermore, in the 1 to 4 For the sake of clarity, the individual elements shown are only partially provided with reference symbols when they occur multiple times.

The 1 shows a schematic representation of a cross section of a wafer 100 with chips 120 to illustrate a method according to the invention for processing the wafer 100. The chips 120, which in this example are MEMS chips 120, are shown in different variants of the separation. Here, the wafer 100 is shown after a sacrificial layer etching, by which structures 122 were exposed and recesses 110 and gap structures 180a, 180b, 180c with gaps 182a, 182b, 182c were created. The structures 122 can comprise MEMS structures 122', for example for micromirror arrays, which have a surface 122b to be protected, such as a mirror surface. The original shape of the wafer 100 before the sacrificial layer etching is indicated by a dashed line 101, which also illustrates the original course of a first surface 100a and a second surface 100b of the wafer 100.

The left chip 120a and the middle chip 120b of the MEMS chips 120 each have webs 150a, 150b that connect them to a remainder 105 of the wafer 100. The chip 120a is connected to the respective remainder 105 of the wafer 100 via the vertical webs 150a and the chip 120b is connected to the respective remainder 105 of the wafer 100 via the horizontal webs 150b. In contrast, the right chip 120c is already completely separated; it is not held in the wafer 100 by webs. The gap structures 180a, 180b with the gaps 182a, 182b are accordingly locally perforating gap structures. The gap structure 180c can be a continuously penetrating gap structure 180c with a gap 182c enclosing the chip 120c, through which the chip 120c was detached from the wafer 100. However, the movement of the chip 120c in a direction 140 perpendicular to the first surface 100a of the wafer 100, illustrated in the drawing by a corresponding arrow, is restricted by means of holding structures 160 in the form of projections in the remainder 105 of the wafer 100. which protrude into the gap 182c. These holding structures 160 block the path of the chip 120c when moving in the direction 140, wherein the holding structures 160 are designed such that they only come into contact with areas of the chip 120c that are not part of the surface 122b to be protected.

Also shown are metal contacts 124 with which the wafer 100 was provided, which can serve for electrical contact with other components, for example to electronically control the MEMS chips 120.

2 now shows a schematic representation of a cross section of the wafer 100 of the 1 with the MEMS chips 120 when removing the MEMS chips 120 according to the method according to the invention. The removal can be carried out, for example, by means of a device 200 for pick-and-place (pick-and-place device, for example a pick-and-place robot), which generates a negative pressure for moving the MEMS chips 120. In the 2 The left chip 120a is currently being removed, which is accompanied by a separation by breaking the vertical webs 150a.

In 3 The MEMS chips 120 are shown schematically during or after placement by the pick-and-place device 200 on a template 300 according to the invention in accordance with the method according to the invention. This template 300 has a base 320 in the form of a base plate 320 on which support structures 310 are located. These support structures 310 can, for example, have the form of rectangular frames. The support structures 310 form a plurality of recesses 350 with the base plate 320, which serve to accommodate the MEMS structures 122' and their surfaces 122b to be protected. The recesses 350 thus have side walls 352, which simultaneously form the support structures 310, and each have a base 354, which represents a part of the base plate 320.

The template 300 thus protects the surfaces 122b of the MEMS chips 120 that are to be protected, for example during subsequent steps of a manufacturing process for an assembly based on the chips. The template 300 also achieves a defined arrangement of the MEMS chips 120. For better fixing of the MEMS chips 120, we can 3 As shown, the recesses 350 created by the base plate 320 and the support structures 310 can be provided with channels 360 in a wall, here in the base 354 of the respective recess 350, which can serve to apply a negative pressure or vacuum. As shown, the MEMS chips 120 can be placed on the template 300 with a small distance from one another. This makes it possible to achieve a high fill factor of the MEMS chips 120.

As in 4 As shown, the MEMS chips 120 placed in this way can be connected to a common component 400, for example by soldering the metal contacts 124. This common component 400 can be, for example, an assembly with electronic components for controlling the MEMS chips 120. An electrical connection can be made after soldering, for example via the now soldered metal contacts 124'.

5 Finally, in schematic form as a flow chart, an exemplary method according to the invention for processing a wafer 100 is shown. First, in step 510a, a wafer 100 with a first surface 100a and a second surface 100b opposite the first surface 100a is provided. This wafer 100 has structures 122 for a plurality of chips 120, for example MEMS chips 120, each with a surface 122b to be protected. Furthermore, in step 510b, a template 300 with a base 320 and one or more support structures 310 arranged thereon is provided.

Before the wafer 100 is singulated 520, a gap structure 180a, 180b with a plurality of gaps 182a, 182b can be formed 512 in the wafer 100, enclosing individual chips 120 and locally perforating the wafer 100. The singulation 520 then takes place at least partially along these multiple gaps 182a, 182b, wherein the formation 512 of the locally perforating gap structure 180a, 180b preferably forms webs 150a, 150b between the gaps 182a, 182b, which run horizontally or vertically with respect to the first surface 100a and hold the chips 120 in the wafer 100. Such a step, which is typically carried out by means of etching, can be combined with a clearance 514 of possibly existing MEMS structures 122' before the dicing 520 of the wafer 100.

After a separation 520 of the wafer 100 into the chips 120, which typically takes place after or with a sacrificial layer etching, the chips 120 can be removed from the wafer 100 in step 530.

Finally, in step 540, at least a portion of the removed chips 120 is placed on the one or more support structures 310 of the template 300 in order to achieve a desired arrangement, i.e. a desired position and orientation, of the placed chips 120. Here the surfaces 122b to be protected are directed towards the bottom 320 of the stencil 300. They do not come into direct contact with the one or more support structures 310. The placed chips 120 are then connected 550 to a common component 400, the arrangement of the placed chips 120 relative to one another being maintained.

The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, a large number of modifications are possible within the scope specified by the claims, which are within the scope of expert action.

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.

Cited patent literature

• DE 10 2013 208 446 A1 [0002]
• EP 0 877 272 A1 [0002]
• WO 2010/049076 A2 [0002]
• DE 10 2006 032 195 A1 [0002]
• DE 10 2009 029 202 A1 [0002]
• DE 10 2015 206 996 A1 [0002]

Claims (11)

Method for processing a wafer (100) with the following steps: a. Providing (510a) the wafer (100) with structures (122) for a plurality of chips (120) and a first surface (100a) and a second surface (100b) opposite the first surface (100a); b. Providing (510b) a template (300) with a base (320) and one or more support structures (310) arranged thereon; c. Singling (520) the wafer (100) into the chips (120), each chip (120) having a surface (122b) to be protected; d. Removing (530) the chips (120) from the wafer (100); e. Placing (540) at least a portion of the removed chips (120) on the one or more support structures (310) of the template (300) in order to achieve a desired arrangement of the placed chips (120) such that the surfaces (122b) to be protected are directed towards the bottom (320) of the template (300) and are not in direct contact with the one or more support structures (310); and f. subsequently connecting (550) the placed chips (120) to a common component (400), wherein the arrangement of the placed chips (120) relative to one another is maintained. procedure according to claim 1 , wherein the wafer (100) has holding structures (160) and/or before or during the singulation (520) of the wafer (100) a formation (512) of holding structures (160) takes place in the wafer (100), wherein the holding structures (160) are designed to restrict possible movements of the chips (120) after the singulation (520) in at least one direction (140) perpendicular to the first surface (100a) of the wafer (100). Method according to claim one of the preceding claims, wherein prior to the singulation (520) of the wafer (100), a formation (512) of a gap structure (180a, 180b) enclosing individual chips (120) and locally perforating the wafer (100) takes place in the wafer (100), and the singulation (520) takes place at least partially along these multiple columns (182a, 182b), wherein the formation (512) of the locally perforating gap structure (180a, 180b) preferably forms webs (150a, 150b) between the columns (182a, 182b), which each run horizontally or vertically with respect to the first surface (100a) and hold the chips (120) in the wafer (100). Method according to one of the preceding claims, wherein during the singulation (520) of the wafer, a formation (512) of a gap structure (180c) enclosing individual chips (120) and continuously penetrating the wafer (100) with one or more gaps (182c) takes place in the wafer (100), and the singulation (520) takes place at least partially by the formation of the gap structure (180c). Method according to one of the preceding claims, wherein the structures (122) for the chips (120) comprise MEMS structures (122') for microelectromechanical systems and the surfaces (122b) to be protected are part of the MEMS structures (122'), wherein a release (514) of the MEMS structures (122') takes place before the dicing (520) of the wafer (100). procedure according to claim 5 , wherein the open MEMS structures (122') comprise MEMS structures for a micromirror array. Template (300) for placing chips (120) with surfaces (122b) to be protected, preferably for use in a method according to one of the preceding claims, wherein the template (300) comprises a base (320) and one or more support structures (310) arranged thereon, wherein the support structures (310) are designed such that the chips (120) can be placed on the one or more support structures (310) such that the surfaces (122b) to be protected are not in direct contact with the one or more support structures (310). template (300) after claim 7 , wherein the one or more support structures (310) have the shape of one or more rectangular, triangular, hexagonal and/or trapezoidal frames and/or one or more rectangular, triangular, hexagonal and/or trapezoidal grids, thereby defining recesses (350) in the template (300) which serve to place the chips (120) and to protect the surfaces to be protected (122b). template (300) after claim 8 , wherein the recesses (350) defined by the one or more frames and/or the one or more grids each have a wall (352, 354) with a channel (360) suitable for applying a negative pressure or a vacuum in order to suck in the chips (120) placed on the recesses. Template (300) according to one of the Claims 7 until 9 , wherein at least parts of the bottom (320) of the template (300) are at least partially transparent to light in a wavelength range. Template (300) according to one of the Claims 7 until 10 , wherein at least parts of the bottom (320) of the template (300) consist of a glass or have a glass.

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