DE102021212644A1 - CIRCUITS INTEGRATED INTO A FRONT END WITH DIFFERENT SILICON-ON-INSULATOR TECHNOLOGIES - Google Patents

Abstract

SOI-based technology platforms are described that provide fully front-end integrated circuits (FEICs) with switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick-film area of the integrated circuit, creating a partially depleted PA based on silicon-on-insulator technology, and the switches and LNAs can be built in a thin-film area of the integrated circuits, creating fully-depleted silicon-on -Isolator technology based low noise amplifier devices and switches are emerging. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film domain and/or the thin film domain.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from U.S. Provisional Application No. 63/112,951 , filed November 12, 2020 and entitled FRONT END INTEGRATED CIRCUITS INCORPORATING DIFFERING SILICON-ON-INSULATOR TECHNOLOGIES, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Area

The present disclosure generally relates to front end integrated circuits for high frequency applications.

Description of related art

Front-end modules (FEMs) are built-in modules that are integrated with various functional components used in wireless front-end circuits of wireless devices. Front-end modules can be designed to process radio frequency (RF) signals adapted to various wireless transmission protocols, such as broadband cellular technologies (e.g. 3G, 4G, 5G, Long Term Evolution (LTE), etc.), wireless network technologies (e.g. Wi- Fi), short-range wireless technologies (e.g. BLUETOOTH®) and global positioning systems (GPS) technologies. Front-end modules typically have circuitry and electrical components between the antenna and a digital baseband system that is sufficient to receive and transmit radio frequency signals. Certain FEMs may include all of the filters, low-noise amplifiers (LNAs), and down-converter mixers necessary to process the modulated signals received at the antenna into signals suitable for input to a baseband analog analog-to-digital converters (ADCs). FEMs may also include power amplifiers (PAs) and other transmitter circuitry to process signals for transmission over the antenna. FEMs may be surface mount technology (SMT) modules, multi-chip modules (MCMs), or the like. FEMs may include PA blocks, LNA blocks, input and output adjustments, MIPI standard digital control blocks, filters, duplexers, multiplexers, antenna switches, band select switches, and the like. A front end integrated circuit (FEIC) is a single semiconductor die that includes the functionality of an FEM.

SUMMARY

According to a number of implementations, the present disclosure relates to a circuit integrated in a front end, which has a substrate, an insulating layer on the substrate and a semiconductor layer on the insulating layer, of which the semiconductor layer forms a thin film region and a thick film region, of which the thin film region is a or has multiple fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) devices and one or more FDSOI switch devices and the thick film region has one or more partial partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) devices.

In some embodiments, the isolation layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick and 50 nm or less thick. In some further embodiments, the semiconductor layer in the thick film region is at least 50 nm thick and 180 nm or less thick.

In some embodiments, the insulating layer is a buried oxide layer. In some embodiments, the semiconductor layer in the thin film region is 1/4 of a gate length of the one or more FDSOI LNA devices. In some embodiments, the circuit integrated into the front end further comprises one or more passive devices built in the thin film portion of the semiconductor layer. In some embodiments, the circuit integrated into the front end further comprises one or more passive devices built into the thick film portion of the semiconductor layer.

In some embodiments, the thin film portion of the semiconductor layer is created by local thinning. In some embodiments, the thick film portion of the semiconductor layer is formed by selective epitaxial growth.

According to a number of implementations, the present disclosure relates to a method of manufacturing a front end integrated circuit. The method includes forming an insulating layer on a substrate. The method further includes forming a semiconductor layer on the insulating layer. The Ver Driving further includes building one or more fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) devices based on silicon-on-insulator technology in the semiconductor layer. The method further includes building a FDSOI switch device in the semiconductor layer. The method further includes increasing the thickness of a portion of the semiconductor layer to form a thick film portion of the semiconductor layer. The method further includes building a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device in the thick film region of the semiconductor layer such that the FDSOI LNA device and the FDSOI switch device are located in a thin film region of the semiconductor layer and the PDSOI PA device is located in the thick film region of the semiconductor layer.

In some embodiments, the isolation layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick and 50 nm or less thick. In some further embodiments, the semiconductor layer in the thick film region is at least 50 nm thick and 180 nm or less thick.

In some embodiments, the semiconductor layer in the thin film region is 1/4 of a gate length of the FDSOI LNA device. In some embodiments, the method further comprises building one or more passive devices in the thin film portion of the semiconductor layer. In some embodiments, the method further comprises building one or more passive devices in the thick film portion of the semiconductor layer. In some embodiments, increasing the thickness is done by selective epitaxial growth.

According to a number of implementations, the present disclosure relates to a method of manufacturing a front end integrated circuit. The method includes forming an insulating layer on a substrate. The method further includes forming a semiconductor layer on the insulating layer. The method further includes building a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device in the semiconductor layer. The method further includes reducing the thickness of a portion of the semiconductor layer to form a thin film portion of the semiconductor layer. The method further includes building a fully depleted silicon-on-insulator (FDSOI) low noise amplifier (LNA) device based on silicon-on-insulator technology in the thin-film region of the semiconductor layer. The method further includes building a FDSOI switch device in the thin film region of the semiconductor layer such that the PDSOI PA device is in a thick film region of the semiconductor layer and the FDSOI LNA device and the FDSOI switch device are in a thin film region of the semiconductor layer.

In some embodiments, the isolation layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick and 50 nm or less thick. In some further embodiments, the semiconductor layer in the thick film region is at least 50 nm thick and 180 nm or less thick.

In some embodiments, the semiconductor layer in the thin film region is 1/4 of a gate length of the FDSOI LNA device. In some embodiments, the method further comprises building one or more passive devices in the thin film portion of the semiconductor layer. In some embodiments, the method further comprises building one or more passive devices in the thick film portion of the semiconductor layer. In some embodiments, the thickness reduction is done by local thinning.

According to a number of implementations, the present disclosure relates to a method of manufacturing a front end integrated circuit. The method includes forming an insulating layer on a substrate. The method further includes forming a semiconductor layer having a first thickness on the insulating layer. The method further includes increasing the thickness of a portion of the semiconductor layer to form a thick film portion of the semiconductor layer while another portion of the semiconductor layer having the first thickness forms a thin film portion. The method further includes building high voltage analog circuits in the thick film area. The method further includes building low voltage analog circuits in the thin film region.

In some embodiments, the isolation layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick and 50 nm or less thick. In some further embodiments, the semiconductor layer in the thick film region is at least 50 nm thick and 180 nm or less thick.

In some embodiments, the high-voltage analog circuits include a low-drop voltage regulator. In some embodiments, the high-voltage analog circuits include a high-voltage power amplifier. In some embodiments, the method further includes building digital circuits in the thin film region.

According to a number of implementations, the present disclosure relates to a method of manufacturing a front end integrated circuit. The method includes forming an insulating layer on a substrate. The method further includes forming a semiconductor layer having a first thickness on the insulating layer. The method further includes reducing the thickness of a portion of the semiconductor layer to form a thin film portion of the semiconductor layer while another portion of the semiconductor layer having the first thickness forms a thick film portion. The method further includes building a radio frequency (RF) device in the thick film region. The method further includes building analog or digital circuits in the thin film area.

In some embodiments, the isolation layer is at least 100 nm thick. In some embodiments, the semiconductor layer in the thin film region is at least 5 nm thick and 50 nm or less thick. In some further embodiments, the semiconductor layer in the thick film region is at least 50 nm thick and 180 nm or less thick.

In some embodiments, the RF device in the thick film region includes a power amplifier (PA) device. In some other embodiments, the PA device comprises a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device.

In some embodiments, the digital circuitry includes logic gates.

Certain aspects, advantages, and novel features have been described herein in order to summarize the disclosure. It should be noted that not all of these advantages may necessarily be achieved in accordance with any particular embodiment. Thus, the disclosed embodiments may be implemented or performed in a manner that achieves or optimizes one or a group of advantages as taught herein, without necessarily achieving other advantages as taught or suggested herein.

character list

• 1A FIG. 12 illustrates a front end integrated circuit (FEIC) fabricated using silicon-on-insulator (SOI) fabrication technology.
• 1B Figure 12 illustrates another fully integrated FEIC fabricated using SOI fabrication technology.
• 2A , 2 B , 2C and 2D illustrate an example FEIC at different stages of a manufacturing process.
• 3A , 3B , 3C and 3D illustrate a modification of the manufacturing process for those related to 2A-2D described FEIC.
• 4A , 4B , 4C and 4D illustrate another exemplary FEIC at different stages of a manufacturing process.
• 5A , 5B , 5C and 5D illustrate a modification of the manufacturing process for those related to 4A-4D described FEIC.
• 6A and 6B illustrate methods of constructing an integrated FEIC with a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device, a fully-depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device, and an FDSOI switching device.
• 7A and 7B illustrate other methods of building an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The subheadings, if any, used herein are all for guidance purposes and do not necessarily affect the scope or meaning of the claimed subject matter.

overview

A front end integrated circuit (FEIC) is a single semiconductor die that has the functionality of a front end module (FEM). It would be desirable to have a technology platform for a To create FEIC in order to be able to satisfy the ever-increasing needs for higher performance, smaller installation space sizes and lower costs. Typically, chip performance is determined by analog circuitry, which includes elements such as low noise amplifiers (LNAs), switches, power amplifiers (PAs), passive devices, analog circuitry (e.g., level shifters, summers, current mirrors, etc.), include digital circuits (eg, logic gates), regulators (eg, low-drop voltage regulators), charge pumps, and the like. A fully integrated radio frequency FEIC, HF-FEIC, as used in the present disclosure, includes both elements for transmission and reception in a single chip. These elements include PAs, LNAs, and switches, and may include appropriate passive devices, analog and digital circuitry, controllers, and the like.

Promising approaches to fabricating fully integrated RF FEICs include silicon-on-insulator (SOI) process technologies. SOI refers to the fabrication of silicon semiconductor devices in a layered silicon-insulator-silicon substrate to reduce parasitic capacitance within the devices, thereby increasing their performance. SOI process technologies can provide improved characteristics of RF FEICs (e.g. higher bandwidth, LNA performance with lower noise (NF), high linearity, energy efficiency, small footprint, low insertion loss, etc.). SOI can be distinguished from bulk process technologies that use trenches of doped silicon that extend deep into the substrate rather than stopping at an insulating layer over the substrate layer. Transistors or bulk devices include devices in which the source and drain are built into the silicon substrate and dopants are added to the substrate to affect its conductivity properties. As device size shrinks (e.g., below about 28 nm), bulk transistors become increasingly complex and it is then advantageous to build transistors using SOI technology.

The SOI structure comprises a silicon film (eg crystalline silicon) separated from the bulk substrate by a thin insulator layer (eg buried oxide or BOX). The BOX layer is designed to improve isolation, reduce short channel effects, prevent current leakage, and improve switching speeds, at least in part due to reduced drain-to-main body capacitance. In SOI wafers, the insulator is usually a thermal silicon dioxide (SiO ₂ ) layer and the substrate is a silicon wafer. Depending on the type of application, the silicon film can vary in thickness (eg, from less than about 50 nm to several tens of microns). The thickness of the BOX layer can also vary depending on the type of application (eg from tens of nanometers to several micrometers). SOI fabrication technologies include Separation by Implanted Oxygen (SIMOX), SOI by Bonding and Etchback (BESOI), Epitaxial Layer Transfer (ELTRAN®), NANOCLEAVE®, SMART CUT™, etc.

SOI technology can be implemented with complementary metal oxide semiconductors (CMOS). SOI-CMOS involves the construction of metal oxide semiconductor field effect transistors (MOSFETs) on the thin semiconductor layer (e.g. silicon or germanium). The thin semiconductor layer is separated from the substrate by an insulating layer (e.g. buried oxide) to electrically isolate the devices from the underlying semiconductor substrate and from each other. The thickness of the isolation layer of an SOI device can be anywhere from about 5 nm to about 400 nm and the thickness of the semiconductor film can be anywhere from about 5 nm to about 240 nm.

The MOSFETs on an SOI wafer include a channel depletion layer between the source and drain. SOI devices can be classified into two types based on the extent of the channel depletion layer compared to the thickness of the silicon film: partially depleted SOI devices (PDSOI) and fully depleted SOI devices (FDSOI). PDSOI devices include devices in which the silicon film is thicker than the maximum gate depletion width, and such devices exhibit the floating main body effect. FDSOI devices include devices in which the silicon film is thin enough to be fully depleted before the threshold condition is reached.

FDSOI devices comprising an ultra-thin insulating layer (buried oxide or BOX) disposed on the substrate and a very thin silicon film is used to form a transistor channel. FDSOI devices typically use an undoped or only lightly doped channel. Typically, the layer of thin silicon film is between about 5 nm and about 50 nm thick, or usually 1/4 the gate length. Additionally, the BOX insulating layer may be thick (eg, between about 100 nm and about 400 nm) or ultra-thin (eg, between about 5 nm and about 50 nm). In FDSOI devices, the silicon layer under the gate insulator is thin enough that it is completely depleted of mobile carriers, so it is a device "completely depleted". In other words, the depletion region reaches the buried oxide during switching of the FDSOI device from off to on state.

The semiconductor film is very thin in FDSOI devices, so the depletion region covers the entire film. In FDSOI devices, the gate oxide (GOX) carries fewer depletion charges than the bulk device, so its increase in inversion charges leads to higher switching speeds. Depletion charge limiting by the BOX produces depletion capacitance suppression and hence a significant reduction in subthreshold offset, allowing FDSOI MOSFETS to operate at lower gate biases and hence lower power.

PDSOI devices include a thicker silicon layer on top of the BOX layer compared to FDSOI devices. Typically, the top silicon layer is between about 50 nm and about 180 nm thick. The silicon under the channel is partially depleted of mobile carriers, making the resulting device "partially depleted". Typically, the BOX layer is between about 100 nm and about 400 nm thick.

Due to its high integration capability and lower cost, CMOS technology is one of the most promising candidates for fully integrated FEICs. Typically, the most difficult device to build with CMOS technology is the high power PA device, which traditionally employs laterally diffused MOSFETs (LDMOS) or extended drain MOSFETs (EDMOS) in high power, low frequency applications. LDMOS and EDMOS PAs are usually easier to build with bulk technology or SOI thick film technology. However, when the device size is small (e.g., about 28 nm or less), difficulties arise. For example, because the silicon film is relatively thin, fabrication typically requires etching through the BOX layer on the wafer. Accordingly, the resulting PA becomes more comparable to a thick film or a bulk device than to an FDSOI device. Existing CMOS technologies - be it bulk CMOS, thick film SOI CMOS or thin film SOI CMOS - all have disadvantages either in integrating switches and LNAs with LDMOS PAs or in the higher cost of integrating these elements.

Accordingly, to address these and other issues, SOI-based technology platforms are described herein that provide fully integrated FEICs with switches, LNAs, and PAs. The PAs can be built in a thick film area of the integrated circuit, resulting in a PDSOI PA, and the switches and LNAs can be built in a thin film area of the integrated circuit, resulting in FDSOI switches and LNAs. The emerging fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film domain, the thin film domain, or both domains. In some implementation forms, an FEIC includes one or more power amplifiers in the thick film portion of the RF circuitry with RF circuitry in the thin film portion. In some implementation forms, an FEIC includes high-voltage analog circuitry in the thick-film domain and low-voltage analog circuitry in the thin-film domain. In certain implementation forms, an FEIC includes an RF device in the thick film domain and analog and/or digital circuitry built in the thin film domain.

Attempts to build a fully integrated FEIC have included building each device (PAs, LNAs, switches) using bulk technologies or building each device using PDSOI technologies. Attempts have also included building bulk LDMOS PAs (e.g. by removing the BOX layer) with FDSOI LNAs and switches. Attempts also included building PDSOI LDMOS PAs with LDMOS LNAs in a thick film area and switches in a locally thinned thin film area.

In contrast to these approaches, fully integrated FEICs with FDSOI switches and LNAs in addition to PDSOI PAs are disclosed herein. In the disclosed embodiments, in contrast to the approaches described above, the BOX layer is not removed. Instead, switches and LNAs are built in a thin film area and the PAs are built in a thick film area. This can be achieved by starting with a thin film, building the switches and LNAs, building a thick film region (eg, using selective epitaxial growth or SEG), and building the PAs in the thick film built region. This can also be achieved by starting with a thick film, building the PAs in the thick film area, using local thinning to create a thin film area, and building the switches and LNAs in the built thin film area. This can also be achieved by preparing the BOX layer and the thin film layer, increasing the thickness of part of the thin film area to create a thick film area, and then placing the FDSOI LNA and switch devices in the thin film area and the PDSOI PAs in the thick film area. This can also be achieved by preparing the BOX layer and the thick film layer, reducing the thickness of part of the thick film area to create a thin film area, and then placing the PDSOI PAs in the thick film area and the FDSOI LNA and switch devices in the thin film area.

The disclosed FEICs are therefore fully integrated CMOS circuits built into a front end, which have improved performance and reduced cost. Some embodiments of the resulting structure of the disclosed FEIC include a thin film region with one or more FDSOI switches and one or more FDSOI LNAs and a thick film region with one or more PDSOI PAs (e.g. LDMOS PAs or EDMOS PAs). In the disclosed FEICs, passive components can be built in the thick film domain (with the PAs), the thin film domain (with the switches and the LNAs), or in both domains. In some embodiments, the disclosed FEICs include one or more thick film devices that form a high voltage analog circuit, which may include a high voltage power amplifier and/or a low dropout voltage regulator. In some embodiments, the disclosed FEICs include an RF device (e.g., a PA) in the thick film region and low voltage analog and/or digital circuitry in the thin film region.

Advantageously, the disclosed FEICs reduce parasitic effects for the PAs compared to bulk solutions. This results in higher active device performance as well as other overall performance benefits of FEICs. Another advantage of the disclosed FEICs is that there is no need to remove part of the buried oxide layer to build up the devices (e.g. PAs) in the thick film area. Accordingly, the integrated circuit may have a thicker silicon film or layer in the thick film area compared to certain forms of implementation of integrated circuits with FDSOI-PAs or PAs in a thin film area. As a result, the performance of the active devices is more stable and the performance of the passive devices becomes better in the thick film area. This improves the overall performance of the disclosed FEICs.

Circuit structure integrated into a front end

1A FIG. 12 illustrates a front-end fully integrated circuit (FEIC) 100a fabricated using silicon-on-insulator (SOI) processing technologies. The FEIC 100a includes a substrate 102 (e.g., a carrier wafer) and an insulating layer 104 (e.g., buried oxide (BOX)) on the substrate 102, and an active device layer or silicon layer 106 (e.g., a silicon film such as crystalline silicon) on the insulating layer 104. In some embodiments, the BOX layer can be between about 100 nm and about 400 nm thick. The silicon layer 106 forms a thick film region 108a and a thin film region 108b. In some embodiments, thick film portion 108a may have a thickness between about 50 nm and about 180 nm. In some embodiments, the thin film region 108b can have a thickness between about 5 nm and about 50 nm. In certain implementation forms, the thick film region 108a is at least about twice as thick as the thin film region 108b, or at least about two and a half times as thick and/or as or less than twenty times thick, or at least about five times as thick and/or as thick as or less than fifteenfold.

A partially depleted SOI power amplifier (PDSOI-PA) device 110 is formed in the thick film region 108 . A fully depleted low noise amplifier SOI (FDSOI-LNA) device 120 and a FDSOI switch device 130 are formed in the thin film region 108b. The PDSOI PA device 110, the FDSOI LNA device 120 and the FDSOI switch device 130 may each comprise an n-MOSFET and/or a p-MOSFET.

The PDSOI-PA device 110 includes a MOSFET having a gate structure with a gate conductor 112 (eg, polysilicon) and a gate insulator 119 (eg, an oxide). One or more spacers can also be used. The PDSOI-PA device 110 includes a source diffusion 114 and a drain diffusion 116. In certain implementation forms, the source diffusion 114 and/or the drain diffusion 116 may extend through the depth of the silicon layer 106 to reach or nearly reach the isolation layer. In some embodiments, drain diffusion 116 may be designed such that PDSOI-PA device 110 is a laterally diffused MOSFET (LDMOS) or an extended drain MOSFET (EDMOS). The PDSOI PA device 110 includes a channel 118 under the gate insulator 119 between the source diffusion 114 and the drain diffusion 116. The channel 118 can be doped to achieve targeted performance characteristics. The channel 118 can be designed to have a thickness where the depletion layer partially covers the space to the gate insulator 119 when the PDSOI-PA device 110 is in the activated state. That's why the PDSOI-PA device 110 is at least partially depleted, at least in part due to its being incorporated into thick film region 108a.

The FDSOI LNA device 120 is similar to the PDSOI LNA device 110 in that it has a gate with a gate conductor 122 and a gate insulator 129 , a source diffusion 124 , a drain diffusion 126 and a channel 128 under the gate insulator 129 . In the FDSOI LNA device 120, the channel 128 is designed to have a thickness sufficient for the depletion layer to cover the space under the gate insulator 129 when the FDSOI LNA device 120 is in an activated operating state. Therefore, the FDSOI LNA device 120 is completely depleted, at least in part due to the fact that it is built in the thin film region 108b. In some embodiments, channel 128 is undoped or only lightly doped.

The FDSOI switch device 130 is similar to the FDSOI LNA device 120 in that it has a gate with a gate conductor 132 and a gate insulator 139 , a source diffusion 134 , a drain diffusion 136 and a channel 138 under the gate insulator 139 . The channel 138 is designed to have a thickness sufficient for the depletion layer to cover the space under the gate insulator 139 when the FDSOI switch device 130 is in an activated operating state. Therefore, the FDSOI switch device 130 is completely depleted, at least in part due to the fact that it is built in the thin film region 108b. In some embodiments, channel 138 is undoped or only lightly doped.

The FEIC 100a includes a substrate 102, an insulating layer 104 on the substrate 102, and a semiconductor layer 106 on the insulating layer 104. The semiconductor layer 106 forms a thin film region 108b and a thick film region 108a. Thin film region 108b includes one or more FDSOI LNA devices 120 and one or more FDSOI switch devices 130. Thick film region 108a includes one or more PDSOI PA devices 110. Thus, semiconductor layer 106 is thinner in LNA device 120 and in of the switch device 130 than in the PA device 110.

1B FIG. 11 illustrates another fully integrated FEIC 100b fabricated using SOI processing technology. The FEIC 100b has the same structure as the FEIC 100a in that it has the substrate 102, the insulating layer 104 on the substrate 102, and the semiconductor layer 106 on the insulating layer 104. FIG. The semiconductor layer 106 forms the thin film portion 108b and the thick film portion 108a. The thick film region 108a includes various thick film devices 140. FIG. In some embodiments, thick film devices 140 may include analog circuitry (eg, high voltage PAs, LDOs, high voltage protection, ESD protection, charge pumps, high power switches, power controller, etc.). Thin film region 108b includes various thin film devices 150. FIG. In some embodiments, thin film devices 150 may include analog circuitry (eg, low voltage analog circuitry, level shifters, summers, current mirrors, etc.) and/or digital circuitry (eg, logic gates). Thus, the semiconductor layer 106 is thinner in the area of the thin film devices 150 than in the area of the thick film devices 140. In some embodiments, the thick film area 108a of the FEIC 100b is used for high voltage analog circuits. In such embodiments, the thin film region 108b can be used for RF circuitry. In certain embodiments, the thick film portion 108a of the FEIC 100b will be used for RF circuitry (eg, PAs) and the thin film portion 108b will be used for analog (eg, high voltage analog circuitry) and/or digital circuitry (eg, logic gates).

2A , 2 B , 2C and 2D 12 illustrate an example FEIC 200 at different stages of a manufacturing process. FEIC 200 is similar to FEIC 100a in that it includes a substrate 102 and an insulating layer 104 on substrate 102 . The substrate 102 may be a silicon carrier wafer or a handle wafer. The insulating layer 104 may be a buried oxide, such as silicon dioxide. In some embodiments, the isolation layer 104 may have a thickness between about 100 nm and about 400 nm.

In 2A FEIC 200 has an active layer or silicon layer 206 of substantially uniform thickness. The silicon layer 206 can be a silicon film. The thickness of silicon layer 206 may be appropriate for building FDSOI devices. For example, the thickness of the silicon layer 206 can be between about 5 nm and about 50 nm, or about 1/4 the gate length of an FDSOI device to be built in the silicon layer 206 .

In 2 B the FEIC 200 comprises a FDSOI-LNA device 220 and a FDSOI switch device 230. The FDSOI-LNA device 220 is the FDSOI-LNA device 120 of FIG 1A similar in that it has a gate structure with a gate conductor 222 over a gate insulator 229, a source diffusion 224, a drain diffusion 226 and a channel 228. The FDSOI switches device 230 is the FDSOI switch device 130 of FIG 1A similar in that it has a gate structure with a gate conductor 232 over a gate insulator 239, a source diffusion 234, a drain diffusion 236 and a channel 238. Although only a single FDSOI LNA device 220 is shown, it should be understood that a variety of FDSOI LNA devices can be fabricated in silicon layer 206 . Also, while only a single FDSOI switch device 230 is shown, it should be understood that a variety of FDSOI switch devices may be constructed in silicon layer 206 .

In 2C For example, the FEIC 200 has a built-up region 207 that increases the thickness of the silicon film 206 in a predefined range. The built-up region 207 can be built up on the silicon film 206 using any suitable process. An example of a process for building a silicon film is selective epitaxial growth (SEG). For example, using SEG, a portion of the silicon layer 206 can be constructed that does not have an FDSOI device.

The built-up region 207 creates a thick film portion 208a of the silicon layer 206 that has a greater thickness than a thin film portion 208b of the silicon layer 206. The resulting thickness of the thick film portion 208a may be suitable for building PDSOI devices therein. For example, the thickness of the silicon layer 206 in the thick film region 208a can be between about 50 nm and about 180 nm. This built-up region 207 is shown as a shaded area on top of silicon layer 206, but it should be understood that the resulting increase in thickness of silicon layer 206 does not necessarily result in an additional layer on top of silicon layer 206. Rather, the additional thickness of the built-up region 207 represents an increase in the thickness of the silicon layer 206 itself.

In 2D FEIC 200 includes a PDSOI-PA device 210 built in thick film region 208a of silicon layer 206. FIG. The PDSOI-PA device 210 is the PDSOI-PA device 110 of the 1A similar in that it has a gate structure with a gate conductor 212 over a gate insulator 219, a source diffusion 214, a drain diffusion 216 and a trench 218. The PDSOI PA device 210 may be an LDMOS PA device or an EDMOS PA device. It should be understood that while only a single PDSOI-PA device 210 is illustrated, a variety of PDSOI-PA devices may be constructed in the silicon layer 206. FIG. The FEIC 200 may have passive devices in both the thick film area 208a and the thin film area 208b.

By way of example, a suitable method of fabricating the FEIC 200 may include forming the insulating layer 104 on top of the substrate 102 . The method includes forming a semiconductor layer 206 on top of the insulating layer 104. The method includes building the FDSOI LNA device 220 in the semiconductor layer 206. The method includes building the FDSOI switch device 230 in the semiconductor layer 206. The method includes increasing the thickness of part of the semiconductor layer 206 to form a thick film region 208a of the semiconductor layer 206. The method includes building the PDSOI-PA device 210 in the thick film region 208a of the semiconductor layer 206 such that the FDSOI-LNA device 220 and the FDSOI switch device 230 are in the thin film region 208b of the semiconductor layer 206 and the PDSOI-PA device 210 is located in the thick film region 208a of the semiconductor layer 206.

3A , 3B , 3C and 3D illustrate a modification of the method of fabricating the FEIC 200 used in connection with FIG 2A until 2D has been described. In this modification, the construction of the FEIC 200 starts with a thin silicon layer 206, as in FIG 3A shown. In 3B the built-up region 207 of the FEIC 200 is formed prior to forming devices in the thin film region 208b. The built-up region 207 can be built up on the silicon film 206 using any suitable process, such as SEG. The built-up region 207 provides that the thick film portion 208a of the silicon layer 206 has a greater thickness than the thin film portion 208b of the silicon layer 206. The resulting thickness of the thick film portion 208a may be suitable for building PDSOI devices, e.g. between about 50 nm and approximately 180 nm. This built-up region 207 is shown as a shaded area on top of silicon layer 206, but it should be understood that the resulting increase in thickness of silicon layer 206 does not necessarily result in an additional layer on top of silicon layer 206. Rather, the additional thickness of the built-up region 207 represents an increase in the thickness of the silicon layer 206 itself. Once the thick film region 208a has been formed, the devices 210, 220, 230 can be formed in the thick film region 208a and the thin film region 208b, as described herein connection with the 2 B and 2D described. 3C illustrates that source diffusions 214, 224, 234 and drain diffusions 216, 226, 236 are formed along with channels 218, 228, 238 can become. Illustrated in some embodiments after formation thereof 3D that the gate insulators 219, 229, 239 are formed between the respective source diffusions and drain diffusions, with the gate conductors 212, 222, 232 being formed over the respective gate insulators. In certain implementations, the mask used to construct the gate insulator 219 may be shared with the mask used for the gate insulators 229,239. Similarly, the mask used to construct gate conductor 212 can be shared with the mask used for gate conductors 222,232.

4A , 4B , 4C and 4D 12 illustrate another example FEIC 300 at different stages of a manufacturing process. FEIC 300 is similar to FEIC 100a in that it includes a substrate 102 and an insulating layer 104 on substrate 102 . The substrate 102 may be a silicon carrier wafer or a handle wafer. The insulating layer 104 may be a buried oxide, such as silicon dioxide. In some embodiments, the isolation layer 104 may have a thickness between about 100 nm and about 400 nm.

In 4A FEIC 300 has an active layer or silicon layer 306 of substantially uniform thickness. The silicon layer 306 can be a silicon film. The thickness of silicon layer 306 may be suitable for building PDSOI devices. For example, the thickness of the silicon layer 306 can be between about 50 nm and about 180 nm.

In 4B FEIC 300 includes a PDSOI-PA device 310 built of silicon layer 306 . The PDSOI-PA device 310 is the PDSOI-PA device 110 of the 1A similar in that it has a gate structure with a gate conductor 312 over a gate insulator 319, a source diffusion 314, a drain diffusion 316 and a trench 318. The PDSOI PA device 310 may be an LDMOS PA device or an EDMOS PA device. It should be understood that while only a single PDSOI-PA device 310 is illustrated, a variety of PDSOI-PA devices may be fabricated in the silicon layer 306. FIG.

In 4C , the FEIC 300 has a region 307 representing a portion of the silicon layer 306 that has been removed to reduce the thickness of the silicon layer 306 in a predefined area. The ablated region 307 can be removed from the silicon film 306 using any suitable process. An example of a process to remove a portion of a silicon film is local thinning. For example, using local thinning, a portion of the silicon layer 306 not having a PDSOI device may be removed.

The removed portion 307 creates a thick film portion 308a of the silicon layer 306 that has a greater thickness than a thin film portion 308b of the silicon layer 306. The resulting thickness of the thin film portion 308b may be suitable for building FDSOI devices therein. For example, the thickness of the silicon layer 206 in the thin film region 308b may be between about 5 nm and about 50 nm, or about 1/4 the gate length of an FDSOI device to be built in the thin film region 308b.

In 4D the FEIC 300 comprises a FDSOI-LNA device 320 and a FDSOI switch device 330. The FDSOI-LNA device 320 is the FDSOI-LNA device 120 of FIG 1A similar in that it has a gate structure with a gate conductor 322 over a gate insulator 329, a source diffusion 324, a drain diffusion 326 and a channel 328. The FDSOI switch device 330 is the FDSOI switch device 130 of FIG 1A similar in that it has a gate structure with a gate conductor 332 over a gate insulator 339, a source diffusion 334, a drain diffusion 336 and a channel 338. Although only a single FDSOI LNA device 320 is shown, it should be understood that a variety of FDSOI LNA devices can be fabricated in silicon layer 306 . Also, while only a single FDSOI switch device 330 is shown, it should be understood that a variety of FDSOI switch devices can be constructed in silicon layer 306 . The FEIC 300 may include passive devices in both the thick film area 308a and the thin film area 308b.

By way of example, a suitable method of fabricating the FEIC 300 may include forming the insulating layer 104 on top of the substrate 102 . The method includes forming a semiconductor layer 306 on top of the insulating layer 104. The method further includes building the PDSOI-PA device 310 in the semiconductor layer 306. The method further includes reducing the thickness of a portion of the semiconductor layer 306 around the thin film region 308b of the semiconductor layer 306 to be formed. The method further includes building the FDSOI LNA device 320 in the thin film region 308b of the semiconductor layer 306. The method further includes building the FDSOI switch device 330 in the thin film region 308b of the semiconductor layer 306. The PDSOI PA device 310 is in the thick film region 308a of the semiconductor layer 306 and the FDSOI LNA device 320 as well as the FDSOI switch device 330 reside in the thin film region 308b of the semiconductor layer 306.

5A , 5B , 5C and 5D illustrate a modification of the method of fabricating the FEIC 300 used in connection with FIG 4A until 4D has been described. In this modification, the construction of the FEIC 300 starts with a thick silicon layer 306, as in FIG 5A shown. In 5B the FEIC 300 includes an area 307 representing a portion of the silicon layer 306 which has been removed to reduce the thickness of the silicon layer 306 in a predefined area. The ablated region 307 can be removed from the silicon film 306 using any suitable process, such as local thinning. The removed portion 307 provides that the thick film portion 308a of the silicon layer 306 has a greater thickness than the thin film portion 308b of the silicon layer 306. The resulting thickness of the thin film portion 308a may be suitable for building FDSOI devices, for example between about 5 nm and about 50 nm or about 1/4 the gate length of an FDSOI device to be built in the thin film region 308b. Once the thin film region 308b has been formed, the devices 310, 320, 330 can be formed in the thick film region 308a and the thin film region 308b, as described herein in connection with FIGS 4B and 4D described. 5C 1 illustrates that source diffusions 314, 324, 334 and drain diffusions 316, 326, 336 can be formed along with channels 318, 328, 338. FIG. Illustrated in some embodiments after formation thereof 5D that the gate insulators 319, 329, 339 are formed between the respective source diffusions and drain diffusions, with the gate conductors 312, 322, 332 being formed over the respective gate insulators. In certain implementations, the mask used to construct the gate insulator 319 may be shared with the mask used for the gate insulators 329,339. Similarly, the mask used to construct gate conductor 312 can be shared with the mask used for gate conductors 322,332.

Production of circuits integrated in a front end

6A illustrates a method 600 for constructing an integrated FEIC with a partially depleted silicon-on-insulator (PDSOI) power amplifier (PA) device, a fully-depleted silicon-on-insulator (FDSOI) low-noise amplifier (LNA) device, device and a FDSOI switching device. 2A until 2D 12 illustrate examples of an FEIC fabricated using steps corresponding to the steps of method 600. FIG.

In block 605, a substrate is prepared with a buried oxide layer (BOX) and a thin film silicon layer. The substrate with the BOX layer and the thin film silicon can take the form of a silicon-on-insulator (SOI) wafer, for example. Preparing the SOI wafer may be done in a separate process, such that the step in block 605 includes receiving or providing the SOI wafer rather than fabricating the SOI wafer. Preparing may also include any step comprising preparing the structure to enable active devices to be built in the thin film silicon layer. 2A represents an example of the FEIC in block 605.

The substrate can be a carrier wafer. The BOX layer can be any suitable insulator, such as thermal silicon dioxide (SiO ₂ ). The thin film silicon layer can be a thin film deposited over the BOX, such as crystalline silicon. The thickness of the BOX layer can be anything between about 5 nm and about 400 nm, and can be at least about 100 nm and/or equal to or less than about 200 nm. The BOX layer is sometimes referred to as a thick BOX layer, in contrast to a thin or ultra-thin BOX layer, which is typically between about 5 nm and 50 nm thick. The thickness of the thin film silicon layer can be between about 5 nm and about 50 nm, or about 1/4 the gate length of an active device to be built in the thin film silicon layer. Any suitable process can be used to prepare the SOI wafer, including separation by implanted oxygen (SIMOX), SOI by bonding and etch-back (BESOI), epitaxial layer transfer (ELTRAN@), NANOCLEAVE®, SMART CUT™, etc.

In block 610, one or more FDSOI LNA devices and one or more FDSOI switch devices are built in the thin film silicon layer. These active devices can be constructed with no channel doping between their source and drain diffusions, or their channel can only be lightly doped. The thickness of the thin film silicon can be chosen such that the channel is fully depleted when the active devices are in their activated operating state. 2 B Figure 12 illustrates an example of a FEIC in block 610.

In block 615, a region of thin film silicon is increased in thickness to create a thick film region that does not contain active FDSOI has devices. Accordingly, the portion of the thin film silicon that is not subjected to the process of increasing the thickness of the silicon film layer may be referred to as the thin film portion of the silicon layer that includes the one or more FDSOI LNA devices and the one or more FDSOI switch devices. The thickness of the resulting thick film region can range from about 50 nm to about 180 nm. 2C represents an example of the FEIC in block 615.

Epitaxial deposition process, or epitaxy, can be used to increase the thickness of the silicon layer. These processes can be used to grow a layer of silicon (e.g. crystalline silicon) over a silicon film (e.g. crystalline silicon) or substrate. Selective epitaxial growth (SEG) is one such exemplary process that can be used to grow silicon on exposed silicon areas of a silicon film. Areas where silicon growth is not desired can be masked with a dielectric film, typically silicon dioxide or silicon nitride. Epitaxial growth can involve condensation of liquid or gaseous precursors to form a film on a substrate. Gaseous precursors can be obtained, for example, by chemical vapor deposition and/or laser ablation.

In block 620, one or more PDSOI-PA devices are built in the thick film region. The one or more PDSOI PA devices may be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon can be arranged such that the channel is partially depleted when the active devices are in the activated operational state. 2D Figure 12 illustrates an example of the FEIC at block 620. Optionally, at block 625, passive devices may be built in the thin film domain, the thick film domain, or both of these domains.

The method 600 offers a number of advantages. For example, in SOI-based LDMOS PA devices and EDMOS PA devices, the associated parasitic effects are less than forms of implementation using bulk technologies. This leads to improved or better performance of active devices. As another example, the buried oxide layer may be a thick BOX layer (rather than an ultra-thin layer) to achieve desired performance characteristics. This results in more stable active device performance, higher performance and improved passive device performance. As another example, the resulting FEIC has the advantages of both active FDSOI devices (e.g., the switch devices and the LNA devices) and active PDSOI devices (e.g., the PA devices).

6B FIG. 6 illustrates a method 650 for building an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device. 3A until 3D 12 illustrate examples of an FEIC fabricated using steps corresponding to the steps of method 650. FIG. It should be noted that method 650 is essentially the same as that associated with 6A described method 600 is the same and thus shares the advantages with the method 600. A difference between methods 600 and 650 is the order of the steps of the methods, such that method 650 prepares the substrate before building devices. In particular, method 650 reverses the steps of building devices in the thin film area and increasing the thickness of a portion of the thin film area to create the thick film area. Accordingly, the description of method 650 is abbreviated and reference is made to the description of method 600 to provide the details of method 650.

In block 655, a substrate having a buried oxide layer (BOX) and a thin film silicon layer is prepared and may be in the form of an SOI wafer, for example. 3A represents an example of the FEIC in block 655.

In block 660, a region of thin film silicon is increased in thickness to create a thick film region. Accordingly, the portion of the thin film silicon which is not subjected to the process of increasing the thickness of the silicon film layer can be referred to as the thin film portion of the silicon layer. The thickness of the resulting thick film region can range from about 50 nm to about 180 nm. 3B represents an example of the FEIC in block 660.

In block 665, one or more FDSOI LNA devices and one or more FDSOI switch devices are built in the thin film portion of the silicon layer. These active devices can be constructed with no channel doping between their source and drain diffusions, or their channel can only be lightly doped. The thickness of the thin film silicon can be chosen such that the channel is fully depleted when the active devices are in their activated operating state. In block 670, one or more PDSOI-PA devices are built in the thick film region. The one or more PDSOI-PA devices may be LDMOS and/or be EDMOS PA devices. The thickness of the thick film silicon can be arranged such that the channel is partially depleted when the active devices are in the activated operational state. Optionally, in block 675, passive devices can be built in the thin film domain, the thick film domain, or both of these domains.

3C and 3D 12 illustrates an example of the FEIC at blocks 665 and 670. It should be understood that while blocks 665 and 670 indicate that the devices are built first in the thin film region and then in the thick film region, other implementation forms of method 650 involve partial building of the devices in the thin film domain and the thick film domain (e.g. as illustrated in 3C ) and then the devices in both areas (e.g. as shown in 3D ) to get finished. In some implementation forms, split masks can be used to complete the devices as described herein. This may also apply to method 600, where devices are partially built in the thin film region and the thick film region and then completed in a separate step, possibly with split masks utilized in some cases.

7A FIG. 7 illustrates a method 700 for building an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device. 4A until 4D 12 illustrate examples of an FEIC fabricated using steps corresponding to the steps of method 700. FIG.

In block 705, a substrate is prepared with a buried oxide layer (BOX) and a thick film silicon layer. The substrate with the BOX layer and the thick film silicon can take the form of a silicon-on-insulator (SOI) wafer, for example. Preparing the SOI wafer may be done in a separate process, such that the step in block 705 includes receiving or providing the SOI wafer rather than fabricating the SOI wafer. Preparing may also include any step comprising preparing the structure to enable active devices to be built in the thick film silicon layer. 4A Figure 12 shows an example of the FEIC in block 705.

The substrate can be a carrier wafer. The BOX layer can be any suitable insulator, such as thermal silicon dioxide (SiO ₂ ). The thin film silicon layer can be a thin film deposited over the BOX, such as crystalline silicon. The thickness of the BOX layer can be anything between about 5 nm and about 400 nm, and can be at least about 100 nm and/or equal to or less than about 200 nm. The BOX layer is sometimes referred to as a thick BOX layer, in contrast to a thin or ultra-thin BOX layer, which is typically between about 5 nm and 50 nm thick. The thickness of the thick film silicon layer can be between about 50 nm and about 180 nm. Any suitable process can be used to prepare the SOI wafer, including separation by implanted oxygen (SIMOX), SOI by bonding and etch-back (BESOI), epitaxial layer transfer (ELTRAN@), NANOCLEAVE®, SMART CUT™, etc.

In block 710, one or more PDSOI-PA devices are built in the thick film silicon layer. The one or more PDSOI PA devices may be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon can be arranged such that the channel is partially depleted when the active devices are in the activated operational state. 4B Figure 12 illustrates an example of the FEIC in block 710.

In block 715, a region of thick film silicon is reduced in thickness to create a thin film region that has no active PDSOI devices. Accordingly, the portion of the thick film silicon that does not undergo the process of thinning the silicon film layer may be referred to as the thick film portion of the silicon layer comprising the one or more PDSOI-PA devices. The thickness of the resulting thin film region can be between about 5 nm and about 50 nm, or about 1/4 the gate length of an active device to be built in the thin film region. 4C Figure 12 shows an example of a FEIC in block 715.

Reducing the thickness of the thick film silicon layer may include any suitable local thinning process. For example, thinning may include mechanical grinding, chemical-mechanical planing, wet planing, atmospheric downstream plasma dry chemical etching (ADP DCE), and so on.

In block 710, one or more FDSOI LNA devices and one or more FDSOI switch devices are built in the thin film silicon layer. These active devices can be constructed with no channel doping between their source and drain diffusions, or their channel can only be lightly doped. The thickness of the thin film region can be chosen such that the channel is fully depleted when the active devices in their activated operating condition. 4D 14 illustrates an example of an FEIC at block 720. Optionally, passive devices may be constructed at block 725 in the thin film domain, the thick film domain, or in both of these domains.

The method 700 offers a number of advantages. For example, in SOI-based LDMOS PA devices and EDMOS PA devices, the associated parasitic effects are less than forms of implementation using bulk technologies. This leads to improved or better performance of active devices. As another example, the buried oxide layer may be a thick BOX layer (rather than an ultra-thin layer) to achieve desired performance characteristics. This results in more stable active device performance, higher performance and improved passive device performance. As another example, the resulting FEIC has the advantages of both active FDSOI devices (e.g., the switch devices and the LNA devices) and active PDSOI devices (e.g., the PA devices). In addition, method 700 may be less expensive than method 600 since thinning is typically a less expensive process than epitaxial growth or deposition.

7B FIG. 7 illustrates a method 750 for building an integrated FEIC with a PDSOI PA device, a FDSOI LNA device, and a FDSOI switch device. 5A until 5D 12 illustrate examples of an FEIC fabricated using steps corresponding to the steps of method 750. FIG. It should be noted that method 750 is essentially that associated with 7A described method 700 is the same and thus shares the advantages with the method 700. A difference between methods 700 and 750 is the order of the steps of the methods, such that method 750 prepares the substrate before building devices. In particular, method 750 reverses the steps of building devices in the thick film area and reducing the thickness of a portion of the thick film area to create the thin film area. Accordingly, the description of method 750 is abbreviated and reference is made to the description of method 700 to provide the details of method 750.

In block 755, a substrate having a buried oxide layer (BOX) and a thick film silicon layer is prepared and may be in the form of an SOI wafer, for example. 5A represents an example of the FEIC in block 755.

In block 760, a region of thick film silicon is reduced in thickness to create a thin film region. Accordingly, the portion of the thick film silicon which is not subjected to the process of reducing the thickness of the silicon film layer can be referred to as the thick film portion of the silicon layer. The thickness of the resulting thin film region can range from about 5 nm to about 50 nm. 5B represents an example of the FEIC in block 760.

In block 765, one or more PDSOI-PA devices are built in the thick film region. The one or more PDSOI PA devices may be LDMOS and/or EDMOS PA devices. The thickness of the thick film silicon can be arranged such that the channel is partially depleted when the active devices are in the activated operational state. In block 770, one or more FDSOI LNA devices and one or more FDSOI switch devices are built in the thin film portion of the silicon layer. These active devices can be constructed with no channel doping between their source and drain diffusions, or their channel can only be lightly doped. The thickness of the thin film silicon can be chosen such that the channel is fully depleted when the active devices are in their activated operating state. Optionally, in block 775, passive devices can be built in the thin film domain, the thick film domain, or both of these domains.

5C and 5D 12 illustrates an example of the FEIC at blocks 765 and 770. It should be understood that while blocks 765 and 770 indicate that the devices are built first in the thick film region and then in the thin film region, other implementation forms of method 750 involve partial building of the devices in the thin film domain and the thick film domain (e.g. as illustrated in 5C ) and then the devices in both areas (e.g. as shown in 5D ) to get finished. In some implementation forms, split masks can be used to complete the devices as described herein. This may also apply to method 700, where devices are partially built in the thin film region and the thick film region and then completed in a separate step, possibly with split masks utilized in some cases.

In addition, it should be noted that the methods 600, 650, 700, 750 can be used to convert the FEIC 100b described in 1 B is shown to manufacture. The modification of methods 600, 650, 700, 750 would be to include the steps of building specific PDSOI-PA devices, Swap FDSOI LNA devices and/or FDSOI switches with other circuits associated with 1B have been described.

Additional Embodiments and Terminology

The present disclosure describes various features, none of which are solely responsible for the advantages described herein. It is to be understood that various features described herein may be combined, altered, or omitted as would be apparent to one skilled in the art. Combinations and sub-combinations other than those specifically described herein will be apparent to those skilled in the art and are intended to form a part of this disclosure. Different methods are described below in connection with different flowchart steps and/or phases. It goes without saying that in many cases certain steps and/or phases can be combined with one another, so that several steps and/or phases illustrated in the flowcharts can be carried out as a single step and/or phase. Additionally, certain steps and/or phases may be broken down into further sub-components that need to be performed separately. In some cases, the order of the steps and/or phases may be rearranged and certain steps and/or phases may be omitted altogether. The methods described herein are also to be understood as open, so that in addition to those illustrated and described herein, further steps and/or phases can also be carried out.

Unless the context clearly dictates otherwise, the words "comprise," "comprehensive," and the like in the specification and claims are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is, in the sense of "including but not limited to." The word "coupled," as used generically herein, refers to two or more elements that can be either directly connected to one another or connected through one or more intermediate elements. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to a specific portion of this application. In the above detailed description, where the context permits, words containing the singular or plural number may also include the plural or singular number. The word "or" in relation to a list of two or more items, where that word covers any of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word "exemplary" is used herein solely to "serve as an example, instance, or illustration." Any implementation that is described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

The disclosure is not intended to be limited to the implementations presented herein. Various changes to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention contained herein may be applied to other methods and systems and are not limited to the methods and systems described above, and elements and steps of the various embodiments described above may be combined to form further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or changes as would come within the scope and spirit of the disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63/112951 [0001]

Claims (40)

A front-end integrated circuit, FEIC, (100a; 100b; 200; 300) comprising: a substrate (102); an insulating layer (104) on the substrate (102); and a semiconductor layer (106; 206; 306) on the insulating layer, of which the semiconductor layer (106; 206; 306) forms a thin film region (108b; 208b; 308b) and a thick film region (108a; 208a; 308a) of which the thin film region (108b ; 208b; 308b) one or more fully depleted silicon-on-insulator technology based low noise amplifier devices, FDSOI LNA devices, (120; 220; 320) and one or more FDSOI switch devices (130; 230; 330). , and of which the thick film region (108a; 208a; 308a) comprises one or more partially depleted silicon-on-insulator technology based power amplifier devices, PDSOI-PA devices (110; 210; 310). The FEIC (100a; 100b; 200; 300) according to claim 1 , wherein the insulating layer (104) is at least 100 nm thick. The FEIC (100a; 100b; 200; 300) according to claim 1 or 2 , wherein the semiconductor layer (106; 206; 306) in the thin film region (108b; 208b; 308b) is at least 5 nm thick and 50 nm or less thick. The FEIC (100a; 100b; 200; 300) according to claim 3 , wherein the semiconductor layer (106; 206; 306) in the thick film region (108a; 208a; 308a) is at least 50 nm thick and 180 nm or less thick. The FEIC (100a; 100b; 200; 300) according to any one of Claims 1 until 4 , wherein the insulating layer (104) is a buried oxide layer. The FEIC (100a; 100b; 200; 300) according to any one of Claims 1 until 5 wherein the semiconductor layer (106; 206; 306) in the thin film region (108b; 208b; 308b) is 1/4 of a gate length of the one or more FDSOI LNA devices (120; 220; 320). The FEIC (100a; 100b; 200; 300) according to any one of Claims 1 until 6 , further comprising one or more passive devices constructed in the thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306). The FEIC (100a; 100b; 200; 300) according to any one of Claims 1 until 7 , further comprising one or more passive devices constructed in the thick film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306). The FEIC (100a; 100b; 200; 300) according to any one of Claims 1 until 8th , wherein the thin-film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306) is produced by local thinning. The FEIC (100a; 100b; 200; 300) according to any one of Claims 1 until 9 , wherein the thick-film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306) is produced by selective epitaxial growth. A method (600) for manufacturing a front-end integrated circuit, FEIC, (100a; 100b; 200; 300), comprising: forming (605) an insulating layer (104) on a substrate (102); forming (605) a semiconductor layer (106; 206; 306) on the insulating layer (104); building (610) a fully depleted silicon-on-insulator technology based low noise amplifier device, FDSOI-LNA device (120; 220; 320) in the semiconductor layer (106; 206; 306); building (610) a FDSOI switch device (130; 230; 330) in the semiconductor layer (106; 206; 306); increasing (615) the thickness of a portion of the semiconductor layer (106; 206; 306) to form a thick film portion (108a; 208a; 308a) of the semiconductor layer (106; 206; 306); and building (620) a partially depleted silicon-on-insulator technology based power amplifier device, PDSOI-PA device (110; 210; 310) in the thick film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306), such that the FDSOI LNA device (120; 220; 320) and the FDSOI switch device (130; 230; 330) are located in a thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306) and the PDSOI-PA device (110; 210; 310) is located in the thick film region (108a; 208a; 308a). The method (600) according to claim 11 , wherein the insulating layer (104) is at least 100 nm thick. The method (600) according to claim 11 or 12 , wherein the semiconductor layer (106; 206; 306) in the thin film region (108b; 208b; 308b) is at least 5 nm thick and 50 nm or less thick. The method (600) according to Claim 13 , wherein the semiconductor layer (106; 206; 306) in the thick film region (108a; 208a; 308a) is at least 50 nm thick and 180 nm or less thick. The method (600) according to any one of Claims 11 until 14 wherein the thin film portion (108b; 208b; 308b) of the semiconductor layer (106; 206; 306) is 1/4 of a gate length of the FDSOI LNA devices (120; 220; 320). The method (600) according to any one of Claims 11 until 15 , further comprising building (625) one or more passive devices in the thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306). The method (600) according to any one of Claims 11 until 16 , further comprising building (625) one or more passive devices in the thick film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306). The method (600) according to any one of Claims 11 until 17 , wherein increasing (615) the is done by selective epitaxial growth. A method (700) for manufacturing a circuit integrated into a front end, comprising: forming (705) an insulating layer (104) on a substrate (102); forming (705) a semiconductor layer (106; 206; 306) on the insulating layer (104); building (710) a partially depleted power amplifier device based on silicon-on-insulator technology. PDSOI-PA device (110; 210; 310) in the semiconductor layer (106; 206; 306); reducing (715) the thickness of a portion of the semiconductor layer (106; 206; 306) to form a thin film portion (108b; 208b; 308b) of the semiconductor layer (106; 206; 306); building (720) a fully depleted silicon-on-insulator technology based low noise amplifier device, FDSOI-LNA device in the thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306); and Building (720) a FDSOI switch device (130; 230; 330) in the thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306) such that the PDSOI PA device (110; 210; 310 ) is located in a thick film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306) and the FDSOI LNA device (120; 220; 320) and the FDSOI switch device (130; 230; 330) are located in the Thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306). The method (700) according to claim 19 , wherein the insulating layer (104) is at least 100 nm thick. The method (700) according to claim 19 or 20 , wherein the semiconductor layer (106; 206; 306) in the thin film region (108b; 208b; 308b) is at least 5 nm thick and 50 nm or less thick. The method (700) according to Claim 21 , wherein the semiconductor layer (106; 206; 306) in the thick film region (108a; 208a; 308a) is at least 50 nm thick and 180 nm or less thick. The method (700) according to any one of claims 19 until 22 wherein the thin film portion (108b; 208b; 308b) of the semiconductor layer (106; 206; 306) is 1/4 of a gate length of the FDSOI LNA devices (120; 220; 320). The method (700) according to any one of claims 19 until 23 , further comprising building (725) one or more passive devices in the thin film region (108b; 208b; 308b) of the semiconductor layer (106; 206; 306). The method (700) according to any one of claims 19 until 24 , further comprising building (725) one or more passive devices in the thick film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306). The method (700) according to any one of claims 19 until 25 , wherein the thickness reduction (715) is performed by local thinning. A method (650) for manufacturing a circuit integrated into a front end, comprising: forming (655) an insulating layer (104) on a substrate (102); forming (655) a semiconductor layer (106; 206; 306) on the insulating layer (104) with a first thickness; increasing (660) a thickness of part of the semiconductor layer (106; 206; 306) to form a thick film region (108a; 208a; 308a) of the semiconductor layer (106; 206; 306) while another part of the semiconductor layer (106; 206; 306) forming a thin film region (108b; 208b; 308b) with the first thickness; building (670) high voltage analog circuits in the thick film region (108a; 208a; 308a); and building (665) low voltage analog circuits in the thin film region (108b; 208b; 308b). The method (650) according to Claim 27 , wherein the insulating layer (104) is at least 100 nm thick. The method (650) according to Claim 27 , wherein the semiconductor layer (106; 206; 306) in the thin film region (108b; 208b; 308b) is at least 5 nm thick and 50 nm or less thick. The method (650) according to claim 29 , wherein the semiconductor layer (106; 206; 306) in the thick film region (108a; 208a; 308a) is at least 50 nm thick and 180 nm or less thick. The method (650) according to Claim 27 , wherein the high-voltage analog circuits include a low-drop voltage regulator. The method (650) according to Claim 27 wherein the high-voltage analog circuits comprise a high-voltage power amplifier. The method (650) according to Claim 27 , further comprising building digital circuits in the thick film area (108b; 208b; 308b). A method (750) for manufacturing a circuit integrated into a front end, comprising: forming (755) an insulating layer (104) on a substrate (102); forming (755) a semiconductor layer (106; 206; 306) on the insulating layer (104) with a first thickness; reducing (760) a thickness of part of the semiconductor layer (106; 206; 306) to form a thin film portion (108b; 208b; 308b) of the semiconductor layer (106; 206; 306) while forming another part of the semiconductor layer (106; 206; 306) forming a thick film region (108a; 208a; 308a) with the first thickness; building (765) a radio frequency, rf, device in the thick film region (108a; 208a; 308a); and building (770) analog or digital circuits in the thin film area (108b; 208b; 308b). The method (750) according to Claim 34 , wherein the insulating layer (104) is at least 100 nm thick. The method (750) according to Claim 34 or 35 , wherein the semiconductor layer (106; 206; 306) in the thin film region (108b; 208b; 308b) is at least 5 nm thick and 50 nm or less thick. The method (750) according to any one of Claims 34 until 36 , wherein the semiconductor layer (106; 206; 306) in the thick film region (108a; 208a; 308a) is at least 50 nm thick and 180 nm or less thick. The method (750) according to any one of Claims 34 until 37 wherein the RF device in the thick film region (108a; 208a; 308a) comprises a power amplifier device, PA device. The method (750) according to Claim 38 wherein the PA device comprises a partially depleted silicon-on-insulator technology based power amplifier device, PDSOI PA device (110; 210; 310). The method (750) according to any one of Claims 34 until 39 , wherein the digital circuits comprise logic gates.

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