DE102024201175A1 - Method for producing a coupled wafer - Google Patents

Abstract

The invention relates to a method for producing a coupled wafer (100) comprising providing a first MEMS wafer (110), the first MEMS wafer (110) having a first functional layer (112) with first MEMS structures (112'), providing, independently thereof, a TSV wafer (120) with silicon vias (150), and connecting a first side (110a) of the first MEMS wafer (110) to a first side (120a) of the TSV wafer (120) such that a coupled wafer (100) is obtained.

Description

Technical area

The present invention relates to the field of wafer processing and relates to a method for producing a coupled wafer, a coupled wafer, a method for producing MEMS chips and a MEMS chip.

State of the art

Devices with microelectromechanical systems (MEMS), such as micromirror arrays or micromirror actuators, are now used in a wide variety of devices, including smartphones, projectors, head-up displays, barcode readers, mask exposure units in semiconductor manufacturing, and microscopes. Corresponding micromirror arrays are known, for example, from the publications DE 10 2013 208 446 A1 , EP 0 877 272 A1 and WO 2010/049076 A2 known. The DE 10 2006 032 195 A1 describes a process for the production of microelectromechanical structures (MEMS structures). DE 10 2009 029 202 A1 A micromechanical system and a method for producing a micromechanical system are disclosed. DE 10 2015 206 996 A1 The so-called EPyC process (EPyC: epitaxial polysilicon cycle) is known for the production of microelectromechanical structures with a large vertical extent, which uses epitaxial polysilicon as a functional and sacrificial material and builds up a layer structure of epitaxial polysilicon layers (EpiPoly layers) by means of repeating cycles.

Particularly for components that are constructed from a large number of MEMS elements arranged in an array, such as micromirror arrays, the challenge is often to achieve a high yield of functional MEMS components.

Disclosure of the invention

According to the invention, a method for producing a coupled wafer, a coupled wafer, a method for producing MEMS chips and a MEMS chip are proposed.

According to a first aspect of the invention, a method for producing a coupled wafer is proposed. For this purpose, a first MEMS wafer is provided, wherein the first MEMS wafer has a first functional layer with first MEMS structures, for example, for actuators and/or sensors, and a first handle wafer. Such a handle wafer can be an SOI handle wafer/start wafer (SOI: silicon-on-insulator). Independently thereof, a TSV wafer with silicon vias (hereinafter also referred to as Si vias or TSVs for short) is provided, and then a first side of the first MEMS wafer is connected to a first side of the TSV wafer such that a coupled wafer is obtained.

Preferably, the method further comprises providing a second MEMS wafer, for example in the form of an SOI wafer and/or with structures for mirror plates, wherein the second MEMS wafer has a second functional layer with second MEMS structures and a second handle wafer and preferably a silicon dioxide layer arranged between the handle wafer and the functional layer, and connecting a second side of the first MEMS wafer, which is different from the first side, to a side of the second MEMS wafer, preferably via electrically conductive bond connections.

The first structures and/or the second MEMS structures can comprise or be structures for one or more MEMS components to be manufactured, such as MEMS sensors and/or MEMS actuators. In particular, the first and/or the second MEMS structures can be arranged such that the MEMS components to be manufactured have an array-like and in particular rectangular or square arrangement, for example a 2x2, 3x2, 3x3, 3x4, or 4x4 arrangement. The MEMS components can be, for example, MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, and/or MEMS resonators. For example, the first MEMS structures comprise structures for actuators and/or sensors, and the second MEMS structures comprise structures for mirror plates.

The functional layers and the handle wafers of the first and/or second MEMS wafer consist of silicon or comprise it. Metals and/or semiconductor oxides can also be contained in the first and/or second functional layer. Thus, the first and/or second functional layer can comprise sacrificial regions made of a semiconductor such as silicon and/or a semiconductor oxide such as silicon dioxide. In addition to purely mechanical structures, the first and/or second MEMS structures can, for example, include structures for actuators, sensors, mirror surfaces, one or more electronic circuits, integrated circuits (ICs), electrodes and/or vias such as silicon vias. contacts (TSV, through-silicon via).

The TSV wafer can be prepared by first providing a silicon wafer, for example, with a thickness of up to 100 µm, up to 200 µm, up to 300 µm, up to 400 µm, up to 500 µm, or more than 500 µm. This thickness of the silicon wafer is selected according to the desired thickness of the TSV wafer. Subsequently, the silicon wafer is oxidized, for example by thermal oxidation and/or LPCVD (low-pressure chemical vapor deposition), to form a silicon dioxide layer on a surface of the silicon wafer. Oxidation is understood here and below to mean both the induced oxidation of parts of the wafer, for example by thermal oxidation, and the application of an oxide layer from the outside, for example by LPCVD. The surface of the wafer opposite this surface is referred to as the wafer backside. An etching mask is then created by structuring the silicon oxide layer. Penetrating holes for the silicon vias are then created in the silicon wafer using the etching mask, for example, using the Bosch process. These holes extend to a silicon dioxide layer on the underside, i.e., on the back of the wafer, which acts as an etch stop layer. At least partial removal of the silicon dioxide layer on the back of the wafer, which acts as an etch stop layer, for example, using RF vapor phase etching, plasma etching, and/or wet chemical etching, exposes the holes. Furthermore, to prepare the TSV wafer, the preferably already exposed holes are oxidized, for example, using thermal oxidation and/or LPCVD. The oxidation thus creates a passivation layer in the holes, typically in such a way that all exposed silicon surfaces inside and preferably also outside the holes are passivated.

As an alternative to such a procedure, the TSV wafer can also be prepared by providing a silicon wafer, preferably with a thickness of up to 1000 µm, particularly preferably up to 800 µm, and most particularly preferably up to 725 µm, followed by applying an etching mask, such as a photoresist layer and/or an oxide hard mask, to a surface of the silicon wafer. An oxide hard mask is a variant of an etching mask for structuring trenches and/or holes. It can, for example, consist of a metal or comprise a metal. This step is followed by structuring the etching mask and then etching holes into the silicon wafer using the etching mask thus structured. These holes are preferably formed as blind holes; therefore, they do not have to penetrate the wafer after this step. Finally, the silicon wafer is thinned back, for example, by back-grinding, such that the holes completely penetrate the silicon wafer. This opens the blind holes. Through this thinning, for example, by grinding, the target thickness of the TSV can be adjusted, for example, to between 50 µm and 700 µm. Finally, the holes are oxidized, for example, by thermal oxidation and/or LPCVD (low-pressure chemical vapor deposition), preferably in such a way that all exposed silicon surfaces are passivated. Cleaning of the TSV wafer can be performed prior to this step.

In both variants, any required alignment marks can be etched into the raw silicon before the holes are created. In subsequent steps, the alignment marks are protected by the passivation oxide. Alignment marks can be used to bond MEMS wafers and TSV wafers so that structures (e.g., contact areas) are aligned to each other. The alignment marks are used for aligned wafer-to-wafer bonding.

The method according to the invention preferably comprises, as further steps, an at least partial, preferably complete removal of the first handle wafer and thereby exposing a surface of the first functional layer and an addition of further first MEMS structures by growing one or more further layers with the further first MEMS structures on the exposed surface.

Furthermore, the first side of the first MEMS wafer is preferably connected to the first side of the TSV wafer before the second side of the first MEMS wafer is connected to the side of the second MEMS wafer.

Preferably, providing the first MEMS wafer and the TSV wafer comprises producing the first MEMS wafer and the TSV wafer, wherein the production of the first MEMS wafer and the TSV wafer occurs at an overlapping time.

Furthermore, by connecting the first side of the first MEMS wafer to the first side of the TSV wafer, one or more connection points, in particular bond connections, are formed, which are used to transmit electrical signals between a rewiring level of the MEMS wafer and at least some of the silicon vias of the TSV wafer.

According to a second aspect of the invention, a coupled wafer is proposed, preferably manufactured according to one of the methods described above, comprising a first MEMS wafer, wherein the first MEMS wafer has a first functional layer with first MEMS structures and a first handle wafer, which may be an SOI handle wafer/start wafer. Furthermore, the coupled wafer comprises a TSV wafer with silicon vias, wherein a first side of the first MEMS wafer is connected to a first side of the TSV wafer.

According to a third aspect of the invention, a method for producing MEMS chips with one or more MEMS components is proposed. This method comprises producing a coupled wafer comprising a coupled wafer according to the invention as just described, and singulating the coupled wafer into a plurality of MEMS chips, such as micromirror chips and/or MMA chips, wherein each MEMS chip can comprise multiple MEMS components. Preferably, the coupled wafer is produced by providing a second MEMS wafer as described above, wherein the coupled wafer further comprises the second MEMS wafer.

After the coupled wafer has been manufactured and before the coupled wafer has been singulated, the first MEMS structures and/or the second MEMS structures can be exposed.

According to a fourth aspect of the invention, a MEMS chip produced by one of the inventive methods for producing MEMS chips is proposed.

Advantages of the invention

The invention describes an approach for providing a TSV wafer in parallel with a MEMS wafer during MEMS chip manufacturing processes and using this wafer for rewiring as a handle wafer and for further processing. The TSV wafer replaces the traditional layer growth process for creating a base plate. This allows for parallelization of processes, as traditional layer growth is avoided. Consequently, the throughput time is shortened and the stability of the MEMS chips is increased. Overall, this also achieves higher yields and high-temperature compatibility, as well as increased flexibility.

A conventional base plate for MEMS chips typically performs the functions of rewiring, stabilization, and signal routing. Constructing such a base plate from individual layers is very time-consuming. According to the invention, the base plate is implemented as a TSV wafer. With such an inventive use of a TSV wafer, a comparatively thin EPyC layer, for example, can be provided for rewiring. This enables a short overall process time. The thickness of the TSV wafer can be adjusted by rethinning, for example, by grinding, to any value between 50 µm and 700 µm or more.

Short description of the drawings

Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

• 1A bis 1E schematische Querschnittsdarstellungen zur Erläuterung eines erfindungsgemäßen Verfahrens zum Herstellen eines gekoppelten Wafers;
• 2A, 2B schematische Querschnittsdarstellung zur Erläuterung eines erfindungsgemäßen Verfahrens zum Bereitstellen eines TSV-Wafers;
• 3A, 3B schematische Querschnittsdarstellungen zur Erläuterung von Details eines erfindungsgemäßen Verfahrens zum Herstellen von MEMS-Baugruppen;
• 4 schematische Querschnittsdarstellungen zur Erläuterung von Details eines erfindungsgemäßen Verfahrens zum Bereitstellen eines TSV-Wafers;
• 5 schematische Draufsicht auf einen erfindungsgemäßen gekoppelten Wafer sowie verschiedene TSV-Querschnittsflächen in ebenfalls schematischer Darstellung; und
• 6 in schematischer Form als Flussdiagramm ein beispielhaftes erfindungsgemäßes Verfahren zum Herstellen eines gekoppelten Wafers und daraus von MEMS-Chips.

They show:

• 1A to 1E schematic cross-sectional views to explain a method according to the invention for producing a coupled wafer;
• 2A , 2B schematic cross-sectional view to explain a method according to the invention for providing a TSV wafer;
• 3A , 3B schematic cross-sectional representations to explain details of a method according to the invention for producing MEMS assemblies;
• 4 schematic cross-sectional representations for explaining details of a method according to the invention for providing a TSV wafer;
• 5 schematic plan view of a coupled wafer according to the invention as well as various TSV cross-sectional areas in a likewise schematic representation; and
• 6 in schematic form as a flow chart an exemplary method according to the invention for producing a coupled wafer and MEMS chips therefrom.

Embodiments of the invention

In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.

The 1A to 1E show schematic cross-sectional views to explain a method according to the invention for producing a coupled wafer.

1A shows a section of a first MEMS wafer 110, wherein the first MEMS wafer 110 has a first functional layer 112 with first MEMS structures 112' and a first handle wafer 114. In this and the following figures, MEMS structures are schematically indicated by horizontal and vertical lines 113, which symbolize, for example, passivation layers.

This first MEMS wafer 110 is now in 1B connected to a TSV wafer 120 with Si vias 150, which are filled, for example, with doped polysilicon, copper, tungsten, and/or metal silicides, which can be applied, for example, using LPCVD (LPCVD: Low Pressure Chemical Vapor Deposition). More specifically, a first side of the first MEMS wafer (110) is connected to a first side 120a of the TSV wafer 120 in such a way that a coupled wafer 100 is obtained. A material layer, for example, a polysilicon layer 124, was created on the TSV wafer 120 by the LPCVD deposition. In the case of LPCVD polysilicon, this can be doped in-situ with both boron and phosphorus.

1C shows the situation after a subsequent complete removal of the first handle wafer 114 and thereby exposing a surface 112a of the first functional layer 112. Further first MEMS structures 116' were added to the coupled wafer 100 by growing one or more further layers 116 with the further first MEMS structures 116' on the exposed surface 112a.

Now, after providing a second MEMS wafer 130, wherein the second MEMS wafer 130 has a second functional layer 132 with second MEMS structures 132' and a second handle wafer 134, it can be connected to the coupled wafer 100, wherein a second side 110b of the first MEMS wafer 110, different from the first side 110a, is connected to a side 130b of the second MEMS wafer 130 via bond connections 180. The result is shown in 1D shown.

As in 1E Finally, as shown, by selectively removing the polysilicon layer 124 and performing metallization, metal contacts 190 can be produced which are in electrical contact with the Si vias 150.

The 2A , 2B now show a schematic cross-sectional illustration to explain a method according to the invention for providing a TSV wafer 120 in two variants, wherein the sequence of steps is illustrated by means of arrows 280.

According to the first variant according to 2A As shown in sub-figure (i), a silicon wafer 210 is provided with a thickness 211 selected according to the desired target thickness of the TSV wafer 120. For example, this thickness 211 can be up to 100 µm, up to 200 µm, up to 300 µm, up to 400 µm, up to 500 µm, or more than 500 µm. After, for example, thermal oxidation of the silicon wafer 210 to form a silicon dioxide layer 220 on a surface of the silicon wafer 210 (sub-figure (iii)), an etching mask 220' is created by structuring the silicon oxide layer 220 on the upper portion of the silicon dioxide layer 220.

Using the etching mask 220', holes 250 penetrating the silicon wafer 210 for the silicon vias 150 can be created, as shown in sub-figure (iii). The underlying portion of the silicon dioxide layer 220 serves as an etch stop layer. This portion is then removed in sub-figure (iv) in the region of the holes 250, thereby exposing these holes 250. They now penetrate the entire thickness 211 of the silicon wafer 210. Finally, the holes 250 are thermally oxidized, for example, to create a passivation layer 122 in the holes 250. The result, the finished TSV wafer 120, is shown in sub-figure (v).

2B shows an alternative of the procedure 2A . Here, a silicon wafer 210 is again provided (partial figure (i), this time for example with a thickness 211 of up to 1000 µm, preferably up to 800 µm, particularly preferably up to 725 µm. An etching mask 220', such as an oxide hard mask 221, is then applied to the upper surface of the silicon wafer 210 in part figure (ii) and then structured. Now, as shown in part figure (iii), holes 250 are etched into the silicon wafer 210 using the structured etching mask 220'. These holes 250 are, in contrast to the holes 250 of the 2A as blind holes, they do not penetrate the silicon wafer 210.

Subsequently, as shown in sub-figure (iv), the silicon wafer 210 can be thinned, for example, ground back. This is done in such a way that the holes 250 completely penetrate the silicon wafer 210. Thus, blind holes are opened. Through this thinning The target thickness of the TSV wafer 120 to be produced is set. Finally, oxidation is performed, for example, thermal oxidation of the thinned silicon wafer 210 or through the use of LPCVD, to passivate all exposed silicon surfaces. The result of this step is shown in sub-figure (v) and represents the finished TSV wafer 120. The oxidation created passivation layers 122 on the walls of the holes 250. All remaining exposed surfaces of the silicon wafer 210 were also passivated by oxidation in this step, as illustrated in sub-figure (v) by additional passivation layers 222 drawn in. Before oxidation, the silicon wafer 210 is preferably cleaned.

3A , 3B now show schematic cross-sectional views to explain details of a method according to the invention for producing MEMS modules. The chronological order of the process steps is, as already shown in the 2A , 2B , indicated by arrows 280.

More precisely, the 3A and 3B Details of the step of connecting a TSV wafer 120 to a MEMS wafer 110, such as an actuator wafer, showing possibilities for designing a redistribution layer 300 and for filling the holes 250. Here, the sub-figures (i) to (iv) of the 3A or the sub-figures (i) to (v) of the 3B each enlarged representation of a 3A , 3B The coupled wafer 100 shown at the top left, with the elements and structures shown in this overall view being further simplified compared to the partial figures. For example, the signal lines 330 of the MEMS wafer 110 have been omitted. Roughly speaking, the situation shown in the overall view most closely corresponds to the partial figures (ii).

Typically, the first MEMS wafer 110 requires only a thin redistribution layer 300. A cover oxide 320 of the redistribution layer 300 of the MEMS wafer 110 on the side of the redistribution layer 300 facing the TSV wafer 120 is polished and structured such that the signal lines 330 are aligned with the holes 250 of the TSV wafer 120. This situation is shown in sub-figure (i), where, in addition to the cover oxide 320, other possible passivation layers 340, 350 of the MEMS wafer 110 are also shown. Subsequently, the wafers 110, 120 are bonded, for example, by hydrophilic _SiO2 - _SiO2 bonding. The signal lines 330 of the MEMS wafer 110 are free of oxides and open and accessible through the holes 250 of the TSV wafer 120 to the backside of the coupled wafer 100. The holes 250 are provided with passivation layers 122. At this point in time (partial figure (ii)), no electrical contact has yet been established between the TSV wafer 120 and the MEMS wafer 110. Any native oxides present on the silicon contact surfaces can be removed by a cleaning step. The electrical contact is then established in the next step (partial figure (iii)) by depositing an electrically conductive material 150, for example, LPCVD-deposited doped polysilicon, although copper, tungsten, and/or metal silicides are also possible. This fill material 150 evenly lines the passivated holes 250 during the process, thus establishing an electrical connection between the signal lines 330 of the first MEMS wafer 110 and the top surface of the TSV wafer 120. Sufficient fill material 150 is deposited until the holes 250 are completely closed in order to achieve a closed plane 124, for example, a polysilicon layer 124, on the top surface of the TSV wafer 120 and to ensure further processability.

To simplify and accelerate the complete closure of the holes 250 with polysilicon, an artificial narrowing of the holes 250 by a previously deposited PECVD oxide (PECVD: plasma-enhanced chemical vapor deposition) can be provided. Such a procedure is described in 4 Here, sub-figure (ii) shows a constriction 410 achieved by means of anisotropic growth by PECVD, whereby this procedure is shown in enlarged form in sub-figures (iii) to (v). 4 The chronological sequence of the individual process steps is indicated by arrows 280.

A combination of LPCVD polysilicon 124 (isotropic growth) with a subsequent epitaxial step (anisotropic growth), or a combination of both, is also possible. This variant is available in 3B Here, a hole 250 is first lined with LPCVD polysilicon 124, but not completely filled (partial figure (iii)). Subsequently, the remaining opening is sealed with an anisotropic passivation layer 360 in an epitaxial step, leaving a shrinkage cavity 322, i.e., a hollow space (partial figure (iv)).

The holes 250 are now, as shown in part figure (iii) of the 3A and sub-figure (iv) of the 3B shown, sealed and the TSV wafer 120 can be used as a handle wafer for further processing of the coupled wafer 100. Compared to 3A , in which the hole 250 is completely filled, the closing of the hole 250 is done in the variant according to 3B by partial filling in combination with a closure.

At an appropriate time, the 150 Si vias, which have been in the process, are electrically isolated from each other. This can be done by metallization to produce metal contacts 190 and subsequent passivation to produce a passivation layer 350 ( 3A , sub-figure (iv)). Alternatively to an isotropic passivation layer 350, as in sub-figure (v) the 3B shown, the anisotropic polysilicon layer 360 is selectively removed to insulate the metal contacts 190.

The process sequence described here is exemplary and can be integrated modularly at any point in the process flow. It is possible to completely complete the TSVs before the first MEMS wafer 110 is fully processed. It is also possible to complete the first MEMS wafer 110 and then bond it to the TSV wafer 120.

The absolute electrical resistance of the Si vias 150 or the filling with filler material can be adjusted via their cross-sectional area (TSV cross-sectional area). In detail, the electrical resistance of a Si via 150 depends on both its cross-sectional area and its length. Thus, with a constant length, i.e., TSV depth, the resistance can be varied across the TSV cross-sectional area. The cross-sectional area of a TSV should be selected so that the TSV can be closed. In addition to classic, round, or rectangular shapes, more complex structures, such as crosses, spirals, and/or meanders, are also conceivable for the shape of a TSV cross-sectional area. The absolute electrical resistance of the Si vias 150 can be specifically adjusted by selecting the TSV cross-sectional area. Corresponding exemplary variants for a TSV cross-sectional area are shown in sub-figure A of the 5 shown, wherein in sub-figure B the arrangement of the Si vias 150 on a coupled wafer 100 is shown as an example for a plurality of MEMS components 510.

6 shows in schematic form as a flow chart an exemplary inventive method for producing 600 a coupled wafer 100. Furthermore, 6 also a method according to the invention for producing MEMS chips 500.

First, a first MEMS wafer 110 is provided 610, wherein the first MEMS wafer 110 has a first functional layer 112 with first MEMS structures 112' and a first handle wafer 114. Independently of this, a TSV wafer 120 with silicon vias 150 is provided 615. In step 620, a first side 110a of the first MEMS wafer 110 is subsequently connected to a first side 120a of the TSV wafer 120 such that a coupled wafer 100 is obtained.

Furthermore, a second MEMS wafer 130 is provided (step 630), wherein the second MEMS wafer 130 has a second functional layer 132 with second MEMS structures 132' and a second handle wafer 134. Next, a second side 110b of the first MEMS wafer 110, different from the first side 110a, is connected 640 to a side 130b of the second MEMS wafer 130, for example, via bond connections 180.

Now, a removal 650 of the first handle wafer 114 and thereby exposing a surface 112a of the first functional layer 112 as well as an addition 660 of further first MEMS structures 116' by growing one or more further layers 116 with the further first MEMS structures 116' on the exposed surface 112 can take place.

After manufacturing 600 the coupled wafer 100, the first MEMS structures 112', 116' and/or the second MEMS structures 132' can be cut out 670. Finally, the coupled wafer 100 is separated 680 into a plurality of MEMS chips 500.

The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art.

QUOTES CONTAINED IN THE DESCRIPTION

This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 10 2013 208 446 A1 [0002]
• EP 0 877 272 A1 [0002]
• WO 2010/049076 A2 [0002]
• DE 10 2006 032 195 A1 [0002]
• DE 10 2009 029 202 A1 [0002]
• DE 10 2015 206 996 A1 [0002]

Claims (14)

A method for producing (600) a coupled wafer (100), comprising the following steps: a. Providing (610) a first MEMS wafer (110), wherein the first MEMS wafer (110) has a first functional layer (112) with first MEMS structures (112') and a first handle wafer (114); b. Independently providing (615) a TSV wafer (120) with silicon vias (150); and c. Connecting (620) a first side (110a) of the first MEMS wafer (110) to a first side (120a) of the TSV wafer (120) such that a coupled wafer (100) is obtained. Procedure according to Claim 1 , wherein the method comprises the following further steps: d. Providing (630) a second MEMS wafer (130), wherein the second MEMS wafer (130) has a second functional layer (132) with second MEMS structures (132') and a second handle wafer (134); and e. Connecting (640) a second side (110b) of the first MEMS wafer (110), which is different from the first side (110a), to a side (130b) of the second MEMS wafer (130). Procedure according to Claim 1 or 2 , wherein providing (615) the TSV wafer (120) comprises the following steps: a. providing a silicon wafer (210); b. oxidizing the silicon wafer (210) to form a silicon dioxide layer (220) on a surface of the silicon wafer (210); c. generating an etching mask (220') by structuring the silicon oxide layer (220); d. generating holes (250) penetrating the silicon wafer (210) for the silicon vias (150) using the etching mask (220'); e. at least partially removing the silicon dioxide layer (220) on the back side of the wafer to expose the holes (250); and f. oxidizing the holes (250). Procedure according to Claim 1 or 2 , wherein providing (615) the TSV wafer (120) comprises the following steps: a. providing a silicon wafer (210); b. applying an etching mask (220') to a surface of the Si wafer (210); c. structuring the etching mask (220'); d. etching holes (250) into the silicon wafer (210) using the structured etching mask (220'); e. back-thinning the silicon wafer (210) such that the holes (250) completely penetrate the silicon wafer (210); and f. oxidizing the holes (250). Method according to one of the preceding claims, wherein the method comprises the following further steps: • at least partially removing (650) the first handle wafer (114) and thereby exposing a surface (112a) of the first functional layer (112); and • adding (660) further first MEMS structures (116') by growing one or more further layers (116) with the further first MEMS structures (116') on the exposed surface (112a). Method according to one of the preceding claims, wherein the bonding (620) of the first side (110a) of the first MEMS wafer (110) to the first side (120a) of the TSV wafer (120) takes place before the bonding (640) of the second side (110b) of the first MEMS wafer (110) to the side (130b) of the second MEMS wafer (130). Method according to one of the preceding claims, wherein the providing (610) of the first MEMS wafer (110) and the TSV wafer (120) comprises producing the first MEMS wafer (110) and the TSV wafer (120), and the producing of the first MEMS wafer (110) and the TSV wafer (120) occurs in a temporally overlapping manner. Method according to one of the preceding claims, wherein by connecting (620) the first side (110a) of the first MEMS wafer (110) to the first side (120a) of the TSV wafer (120), one or more connection points (180) are formed which are suitable for forwarding electrical signals between a rewiring level (300) of the MEMS wafer (110) and at least some of the silicon vias (150) of the TSV wafer (120). Method according to one of the Claims 1 until 8 , wherein the first MEMS structures (112', 116') comprise structures for actuators and/or sensors and the second MEMS structures (132') comprise structures for mirror plates. Coupled wafer (100), preferably produced according to one of the methods 1 to 9, comprising a first MEMS wafer (110), wherein the first MEMS wafer (110) has a first functional layer (112) with first MEMS structures (112') and a first handle wafer (114), and a TSV wafer (120) with silicon vias (150), wherein a first side (110a) of the first MEMS wafer (110) is connected to a first side (120a) of the TSV wafer (120). Method for producing MEMS chips (500) with one or more MEMS components (510), comprising the following steps: a. producing (600) a coupled wafer (100) comprising a coupled wafer (100) according to Claim 10 and b. singulating (680) the coupled wafer (100) into a plurality of MEMS chips (500). Procedure according to Claim 11 , wherein the manufacturing (600) of the coupled wafer (100) according to Claim 2 and preferably one of the Claims 3 until 9 and the coupled wafer (100) further comprises the second MEMS wafer (140). Procedure according to Claim 12 , wherein after the production (600) of the coupled wafer (100) and before the singulation (680) of the coupled wafer (100), a release (670) of the first MEMS structures (112', 116') and/or the second MEMS structures (132') takes place. MEMS chip (500) manufactured according to one of the methods 11 to 13.