DE102008038300A1 - Semiconductor component, has field isolation region whose thickness increases from thickness of gate isolation area towards one of source or drain, where increased thickness is adjusted towards oxidation field thickness - Google Patents

Abstract

The invention relates to a semiconductor device with a semiconductor structure and a method for producing the same. The semiconductor structure has two laterally arranged on the upper side of a semiconductor body switching electrodes of a lateral FET. A gate electrode is arranged on a gate insulation region of the upper side of the semiconductor body. The gate electrode controls the off-state and the on-state between the switching electrodes of the FET. The gate electrode on the upper side of the semiconductor body merges into a lateral field plate arranged on a field insulation region. In this case, the lateral field plate forms a gate electrode of a second device, and the field isolation region gradually changes in thickness from a thickness of the gate insulation region to a thickness of the field isolation region toward one of the switching electrodes.

Description

Background of the Invention

The The invention relates to a semiconductor device having a semiconductor structure and a method for producing the same. The semiconductor structure has a laterally arranged on the top of a semiconductor body control electrode like a FET and a field plate at the same potential. The Gate electrode is on a gate insulation area on top of the semiconductor body arranged. The gate electrode controls the off-state and the on-state between the switching electrodes of the FET.

Such lateral FET structures are increasingly being used as power switches in integrated circuits. On the one hand, these semiconductor components should have a high dielectric strength, on the other hand they should have a low on-resistance R _on at the highest possible saturation current I _DS . Ideally, the drain current in saturation mode is little dependent on the drain-source voltage. This extends the scope of the FET structures to be used as a linear amplifier stage in analog circuits.

In addition to optimizing the electrical and thermo-mechanical parameters, integrated circuits are all about reducing costs. For this purpose, the on-resistance (R _on ) is related to the area requirement of a semiconductor component. A characteristic is therefore the specific switch-on resistance, which will be indicated by R _on · A. The variables to be optimized are accordingly the on-resistance and the saturation current of the semiconductor component. However, the dielectric strength and reliability of the semiconductor component as well as the ESD robustness (electro static discharge - safety) should also be ensured.

The behavior of a lateral FET transistor can be used as a series circuit of a MOSFET transistor as the first device 7 and a second device 13 describe with the characteristic of a FET transistor when a field plate oxide is arranged with a field plate on the top along the drift path of the lateral FETs. In this arrangement adds to the resistance of the first device 7 (For a MOSFET, the channel resistance) In addition, the resistance of the second device with the characteristic of a FET transistor, the second device with the characteristic of a FET often forms a multiple of the channel resistance.

A Optimization of the on-resistance can be double by the application Diffused dopant regions (DMOS) can be achieved, as it passes through these Technology possible is minimum, adjustment independent channel lengths to realize. The dielectric strength can be determined by suitable dopant ratios with respect to the drain zone of the FET and with respect to the surrounding Semiconductor material, or can be improved by field plates. Furthermore the compensation principle can be applied to lateral FETs, in which adjacent to the drift zone of the FET structure, a complementarily doped Area is arranged so that in the case of blocking the presence of movable charge carriers is reduced and thus an avalanche breakthrough is hindered.

For this purpose, the drain zone and the surrounding semiconductor material of the lateral FET are designed such that, starting from a predetermined blocking voltage between drain and surrounding semiconductor material of the transistor, a drift zone without freely movable charge carriers and at the same time adjacent complementary doped semiconductor material zones without freely movable complementary charge carriers. This area corresponds to z. B. the above-mentioned second device with the characteristic of a FETs. By suitable dimensioning of these areas thus the required dielectric strength at low R _on · A and high saturation current can be achieved in a small area. Despite these possibilities, in the conventional lateral FET structures, neither the R _on A nor the saturation current nor the robustness, taking into account the required dielectric strength, are still optimal for known semiconductor structures.

Summary of the invention

In one embodiment of the invention, a semiconductor device having a semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure has two laterally arranged on the upper side of a semiconductor body switching electrodes of a first and a second device as in a MOSFET. A gate electrode is disposed on a gate insulating region of the upper surface of the semiconductor body. The gate electrode controls the off-state and the on-state between the switching electrodes of the FET. The gate electrode on the upper side of the semiconductor body merges into a lateral field plate arranged on a field insulation region. In this case, the lateral field plate forms a gate electrode of the second device with the characteristic of a FET, and the field isolation region has an increasing thickness taking into account the critical field strength, which is from a thickness of a gate insulation region of the first device to a thickness of the field isolation region of the second device in the direction of one of the Switching electrodes passes, wherein the increasing thickness according to the permissible oxide field strength directed.

With this embodiment The invention is a surface optimized High-voltage FET, preferably an LDMOS transistor by reduction reaches the resistance of the second device.

embodiments The invention will now be described with reference to the accompanying drawings described.

Short description of the figures

1 shows a principle equivalent circuit diagram of a lateral FET according to the invention;

2 shows a schematic cross section through a portion of a semiconductor device according to an embodiment of the invention;

3 shows a schematic cross section through an insulated well of a semiconductor body with a semiconductor structure of a semiconductor device according to the embodiment of the invention;

4 shows a schematic cross section through a portion of a semiconductor device according to another embodiment of the invention;

5 to 9 show schematic cross-sections through an insulated well of a semiconductor body in the manufacture of an embodiment of the invention;

5 shows a schematic cross section through a portion of a semiconductor wafer with a prepared pan and prepared basic structure with a Damageimplantation for producing a wedge-shaped gate insulation region;

6 shows a schematic cross section through the portion of the semiconductor wafer according to 5 according to a photographic technique for determining the wedge-shaped gate insulation region;

7 shows a schematic cross section through the portion of the semiconductor wafer according to 6 after etching the insulation area conditioned by damage implantation;

8th shows a schematic cross section through the portion according to 7 after application of a gate oxide layer and structuring of the control electrodes on an exposed semiconductor region of the upper side of the semiconductor body;

9 shows a schematic cross section through the portion according to 8th upon completion of the semiconductor structure for a semiconductor device of an embodiment of the invention;

10 shows schematic diagrams of different increasing oxide thicknesses under a gate electrode.

Detailed description of embodiments

1 shows a principal equivalent circuit diagram of a lateral FET (eg LDMOS) according to the invention. Between the three externally accessible terminals source S, drain D and gate G are within the semiconductor structure, a lateral FET 7 with a gate electrode 9 as the first device and a FET 13 (JUNCTION FIELD EFFECT TRANSISTOR) with a gate electrode 12 coupled as a second device such that the drain electrode 6 and the source electrode 5 be used separately, with the drain of the first device 7 with the source of the second device 13 and the gate electrodes 9 and 12 connected together so that first the channel under the gate electrode 9 of the MOSFET 7 and then the resistance of the serially connected channel region of the gate electrode 12 of the second device 13 takes effect.

2 shows a schematic cross section through a portion of a semiconductor device 1 according to an embodiment of the invention. In this subarea, the basic structure of a semiconductor structure 2 in a semiconductor body 3 shown. The semiconductor body has a buried layer in a well 20 , which is located in the bottom area of the tub on. On this buried layer 20 that as an epitaxial layer 31 may be applied to a half-fiber substrate, is another epitaxial layer 32 with a comparison of the buried layer 20 arranged lower dopant concentration.

In this low-doped epitaxial layer 32 is now the semiconductor structure 2 for the semiconductor device 1 embedded. This structure essentially has a multi-layered body zone 21 on that is in a deep body zone layer 22 , a middle body zone layer 23 and an upper body zone layer 24 divided. In the upper body zone layer 24 is the bodyzone of the MOSFET 7 arranged and within the body zone is a highly doped source zone 29 arranged, which have the same conductivity type as the epitaxial layer 32 has, but with significantly higher dopant concentration. At some distance from the upper body zone layer 24 is a drain zone 26 arranged between upper body zone layer 24 and the drainage zone 26 a drift zone 16 is available. Between the drift zone 16 and the source zone 29 forms in the upper body zone layer 24 a channel 14 of the MOS-FET transistor when connected to the gate de 9 a corresponding potential is placed.

The stream passing through the canal 14 flows, then overcomes the drift path 16 and then reaches the drain zone 26 which has the same conductivity type as the source zone 29 , The resistance of this drift zone 16 is decisive for the on-resistance R _on . This on-resistance can be reduced by the fact that the drift zone 16 is doped higher. This depends on whether it succeeds, a higher-doped drift zone 16 vacate when switching to the blocking mode of charge carriers. Once this freedom is supported by the fact that the deep body zone 22 below the drift zone 16 extends and contributes to that when switching to the blocking mode carriers from the drift zone 16 subtracted from.

Furthermore, the removal of charge carriers from the drift zone 16 by activating the second device 13 with the characteristic of a FET whose gate electrode 12 is disposed on an insulating layer, which is of a I solationsschichtdicke a in the region of the MOSFET gate oxide gradually up to a thickness b of a Feldplattenoxids on the length or a portion of the length of the drift path 16 rises, as exemplified by the 10A to 10D show, wherein the gate electrode 12 of the second device 13 with the gate electrode 9 of the first device 7 is connected and thus when applying a blocking potential, the removal of charge carriers from the drift path 16 more strongly supported than a lateral field plate 11 , When applying a forward potential to the gate electrode 12 of the second device 13 with the characteristic of a FET, this reduces by accumulating charge carriers in the channel region 15 at the interface between semiconductor material and insulating material, the on-resistance of the semiconductor device according to the invention.

There are two measures that are responsible for this optimization of the device 1 combine, executed. On the one hand, the doping in the channel area 15 of the second device 13 with the characteristic of a FET without increasing the doping of the low doped epitaxial layer 32 raised. The canal area 15 is at the same time within the drift zone 16 of the MOSFET, so that the lateral MOSFET now between the two switching electrodes 5 and 6 a drift zone 16 is available, which has an increased doping and thus a lower sheet resistance.

However, this measure requires that the clearing out of mobile charge carriers from the channel area 15 of the second device 13 with the characteristic of a FET is supported by an additional measure, otherwise the compensation principle with the help of the deep body zone 22 below the drift zone 16 can not be sustained. This additional measure becomes clear with the following figures and simulations. For this purpose, the gate electrode 9 of the MOSFET or first device 7 over the canal area 15 of the second device 13 extends with the characteristic of a FET. The efficiency of this measure is determined by the appropriate design of the MOSFET gate electrode 9 and the second device 13 with the characteristic of a FET gate electrode 12 further improved.

The effect of the "second device 13 with the characteristic of a FET gate electrode 12 can be generally reduced by reducing the field oxide or field isolation thickness b or the polysilicon gate electrode 12 of the second device 13 achieve with the characteristic of a FET. In addition, in addition, a dielectric having a larger dielectric constant than field oxide in the field isolation region 10 be used. Nevertheless, the dielectric strength of the dielectric must be ensured and must not be endangered. In order to achieve this, according to the invention, the gate insulation region 28 of the second device 13 with the characteristic of a FET in the direction of the drain connection region or the drain region 26 Gradually increasing and thus made thicker.

This ensures that the electric field in the dielectric of the gate insulation region 28 no critical size is achieved, which enhances the robustness of the semiconductor device 1 which could jeopardize the blocking capacity. Here, the gradual increase, which in 2 as a wedge-shaped rise of the gate insulation region 28 of the second device 13 is designed to be profiled differently, so that the course of the gradual increase the potential profile at the top of the semiconductor device 1 optimized. Furthermore, this measure can still by applying a negative voltage to the Polysiliziumgateelektrode 12 of the second device 13 be strengthened.

In the case of blocking, the channel area should be 15 of the second device 13 stay cleared out, so that no avalanche breakthrough occurs. The semiconductor device according to the invention 1 also takes advantage of a second effect that occurs when switching the first device 7 positively affects. When the MOSFET is switched on as the first device 7 is the potential of the MOS gate electrode 9 relative to the canal area 15 of the second device 13 positive, which results in electrons at the interface between the top 4 of the semiconductor body 3 and the gate isolation region 28 be accumulated. This in turn leads to a reduction of the on-resistance, because of this accumulation of charge carriers, a higher conductivity in the drift path 16 of the second device 13 provided.

The gained higher breakdown voltage can be achieved by increasing the path doping of the second device 13 be converted into a reduced bulk resistance of the same. On the one hand, this achieves an improved on-resistance at low drain voltages and, on the other hand, an optimized saturation current which, in addition, also has a lower drain-source voltage dependence, is formed.

This structure can be used both for the improvement of transistors with n-conductivity and for transistors with p-conductivity, since the polysilicon in each case has the appropriate potentials. Due to the gradually increasing design of the gate insulation area 28 the polysilicon gate electrode 12 for the second device 13 , the drift range 16 , the carrier compensation is supported and a higher doping of the drift path 16 with unchanged high breakdown voltage allows. In addition, the polysilicon gate electrode causes 12 of the second device an accumulation of charge carriers at the interface between the semiconductor body top 4 and gate insulation area 28 , which leads to a lowering of the on-resistance R _on .

The complementarily doped deep body zone layer 22 , which are also along the drift zone 16 of the FET but below this drift zone 15 is arranged, supports the rapid clearing of the drift path 16 when switching to the blocking state of the FET and additionally allows the drift path 16 to dope higher than the surrounding semiconductor material in the low-doped epitaxial layer 32 , Therefore, the deep body zone layer extends 22 from the region of the coupling to the source zone 29 up to the highly doped drain zone 26 ,

Simulation comparisons with lateral MOSFET structures of conventional type have shown that with a constant dose of dopants as in the comparison semiconductor component in the drift zone 16 by introducing the structuring of the gate electrode according to the invention 12 of the second device 13 already a reduction of the on-resistance can be achieved by 9% and an increase of the saturation current by 11% can be achieved by the effects described above. In addition, the breakdown voltage is significantly increased by about 5% and the voltage for safe operation of the semiconductor device, that is, a voltage range until the onset of a charge carrier multiplication can be maintained unchanged, so that it despite improvement of on-resistance, saturation current and breakdown voltage not too a premature multiplication effect of the charge carriers comes (also for a higher VGS).

The function of the middle body zone layer 23 in the multi-layered bodyzone 21 which is more highly doped than the deep body zone layer 22 , lies in the contacting of the active upper body zone layer 24 with the carrier compensation zone of the deep body zone layer 22 , It serves in this context only to ensure a good contact and a transfer of the source potential to serving as a charge compensation zone deeper body zone layer 22 ,

3 shows a schematic cross section through an insulated pan 17 a semiconductor body 3 with a semiconductor structure 2 a semiconductor device 1 according to the 2 , The isolated tub 17 becomes laterally through trench structures 33 , which are also referred to as trench structures limited. These trench structures 33 laterally surround the tub 17 and consist of an electrically conductive filler 38 a vertical field plate 18 that of the semiconductor material of the tub 17 through an insulation layer 35 on the moat walls 34 the trench structure 33 is isolated. The trench bottom 36 has a contact layer 37 which makes contact with a complementary and thus p-type substrate 19 manufactures.

On a top 41 of the complementarily conductive substrate 19 is a first highly doped and thus a good conductive epitaxial layer 31 Applied in the tub 17 a buried layer 20 forms. On this buried layer 20 is another lower doped epitaxial layer 32 of the first conductivity type applied, which is the surrounding semiconductor material or bulk material for the semiconductor structure 2 forms. The details of the semiconductor structure 2 have been explained above and in this illustration the 3 are the components with the same functions as in 2 denoted by like reference numerals and therefore will not be discussed separately.

In this embodiment of the invention, the drain electrode surrounds 6 with the drain zones 26 the semiconductor structure according to the invention 2 while a central source electrode 5 the source zone 29 within the upper body zone layer 24 contacted. Above the canal area 14 in the upper body zone layer 24 is a gate oxide in the gate insulation region 8th arranged over which a gate electrode 9 the FET controls the current between drain and source. Over a drift zone 16 , across which the voltage between source and drain drops, is a gradually increasing gate oxide region of the gate electrode 12 of the second device 13 arranged. The gradual increase of the gate oxide thickness is the potential curve within the drift zone 16 adjusted to ensure that the insulation thickness of the respective oxidation layer is sufficient to those to the drain zone 26 towards increasing voltage zwi the drift path 16 and the gate electrode 12 of the second device 13 to isolate.

The from the gate electrode 9 of the first device 7 and the gate electrode 12 of the second device 13 formed gate electrode is in an intermediate oxide layer 42 embedded, the vias 49 has in corresponding contact holes, which the individual zones in the semiconductor body with contact surfaces 44 on the top 43 the intermediate oxide layer 42 connect. The semiconductor device 1 can have several such tubs 17 with the semiconductor structure according to the invention 2 and thus form an array of MOSFET cells. Because the contact surfaces 44 both for Source S and for Drain D and also for Gate G on top 43 the intermediate oxide layer 42 are arranged and the wells partially over the space charge zone of the pn junction between the substrate 19 and the buried layer 20 Insulated from each other, such power semiconductor devices can be integrated with integrated circuits on the same semiconductor body. Thus, the semiconductor device 1 may be constructed of a plurality of such wells or cells, or such cells may be provided for the power supply of an integrated circuit on the same semiconductor body.

4 shows a schematic cross section through a portion of a semiconductor device 40 , According to another embodiment of the invention. Components having the same functions as in the previous figures are identified by the same reference numerals and will not be discussed separately. The difference to the in 2 shown semiconductor structure is in this embodiment of the invention is that the deep body zone layer 22 , which serves as a charge compensation zone, completely flat in the surrounding low-doped epitaxial layer 32 is introduced. And the middle body zone layer 23 arises from the fact that a local higher doping of the deep body zone layer 22 is achieved by appropriate ion implantation. This results in a more compact design of the semiconductor device 40 , Additionally, due to the effect of the second device 13 and the oxide gradually increasing from a gate oxide thickness a of the MOSFET to a field plate oxide thickness b below the gate electrode 12 of the second device 13 one higher than the surrounding low doped epitaxial layer 32 doped drift zone 16 in the semiconductor body 3 to be ordered.

Due to this high doping of the drift zone 16 could be shown with simulation comparisons that the on - resistance can be reduced by 24%, while the saturation current is increased by 25%. In addition, the safe operating area voltage has also been improved by 20% over the 2 shown semiconductor device 1 the first embodiment of the invention, in which the drift path 16 having the same dopant dose as the comparative component. The dose for the drift path 16 in the embodiment according to 4 could be increased by 30% without changing the threshold voltage and without significantly reducing the breakdown voltage. Compared to the first embodiment according to 2 , in which the breakdown voltage increases by a few percent, here the breakdown voltage remains approximately at the same level.

The 5 to 9 show schematic cross-sections through an insulated pan 17 a semiconductor body 3 in the manufacture of an embodiment of the invention. In addition shows 5 a schematic cross section through a portion of a semiconductor wafer 25 with prepared tub 17 and a prepared basic structure for producing a gradually increasing gate insulation region of a gate electrode in the region of the second device 13 in this semiconductor structure 2 , As 5 shows, is the tub 17 through a pn junction between the substrate 19 and the first highly doped epitaxial layer 31 and through laterally arranged the tub 17 surrounding vertical field plates 18 isolated.

Of the semiconductor device structure according to the invention 2 is in the second low-doped epitaxial layer 32 of the first conductivity type already the deep base zone layer 22 introduced as a charge compensation zone in the drift regions 16 the MOS transistor is used. The drift areas 16 are also already realized and doped higher than the surrounding low doped epitaxial layer 32 , A middle body zone layer is not yet provided with dopant and the entire area for the semiconductor structure according to the invention 2 is of a field oxide of thickness b on top 4 of the semiconductor body 3 covered.

To form a gradually increasing oxide or insulating layer area, first is the semiconductor top 4 from a protective layer 45 covered in a window for a damage implantation 39 in the direction of arrow A is opened. With this damage implantation 39 the field oxide becomes in the field isolation area 10 conditioned. This conditioning affects the etch rate at which this oxide can be removed. The higher the dose of this damage implantation with which the oxide layer is conditioned, the higher the lateral etching rate for such a silicon dioxide. Since the dose can be varied with depth, and thus along the thickness of the field oxide, it is possible to prepare for the oxide by etching to the depth decreasing etching rates by the conditioning.

6 shows a schematic cross section through the portion of the semiconductor wafer 25 , according to 5 , and after a damage implantation in a field isolation area 10 into it. A dashed line 46 gives the future etch limits of a conditioned subarea 27 which, as in 5 shown - achieved by damage implantation. Before the etching step is now on the top of the semiconductor body and the insulating layer 10 another protective layer 47 applied, except for an etching window 30 the remaining areas of the semiconductor well 17 protects against the etching attack. The size and position of this etching window in its planar extent corresponds to the size and position of the planar extent of the source, bulk and gate regions to be produced.

7 shows a schematic cross section through the portion of the semiconductor wafer 25 , according to 6 after etching an insulation area conditioned by damage implantation 10 , In the size of the window 30 in the protective layer 47 becomes the top 4 of the semiconductor body 3 exposed by a wet etch, at the same time a gradually increasing oxide thickness under the protective layer 47 at the edges of the window 30 arises. The accuracy of this gradual increase of the etch profile in the oxide thickness can be determined by the in 5 and 6 ion implantation preferably achieved by argon ions.

After exposing the top 4 of the semiconductor body 3 in the area of the window 30 For example, it is now possible to first apply a gate oxide thickness by thermal oxidation, and thereafter the gate oxide, as well as the gradually increasing oxide in the gate insulation region 28 to cover with a polysilicon layer as a gate electrode. At the same time, a window is opened again in the polysilicon for the gate electrodes, which is the top side 4 of the semiconductor body is exposed and provided for the introduction of the upper body zone layer. When introducing the upper body zone layer, a defined channel length for the MOSFET structure of the first De can be adjusted simultaneously self-adjusting at the edges of the polysilicon layer. The result shows the next figure.

8th shows a schematic cross section through the portion according to 7 after applying a gate oxide layer to an exposed semiconductor region of the top 4 of the semiconductor body 3 , Furthermore, polysilicon is already for the gate electrodes on the thin gate oxide 8th , as well as applied to the gradually increasing area of the gate oxide of the second device, wherein another window 48 into the polysilicon of the gate electrodes 9 and 12 as well as into the underlying gate oxide 8th is introduced to the top 4 of the semiconductor body 3 re-expose and the upper body zone layer 24 introduced so deeply that it diffuses the middle, contacting body zone layer 23 when penetrating the deep body zone layer 22 forms. The window 48 is simultaneously used for a further implantation of dopant, in which now a complementary to the body of the body conductive dopant is introduced in a high concentration for source zones. The fact that a double implantation or diffusion takes place through the same window, automatically forms a constant channel length for the MOSFET structure of the first device.

9 shows a schematic cross section through the portion according to 8th after completion of the semiconductor structure 2 for a semiconductor device 40 the further embodiment of the invention. Components having the same functions as in the previous figures are identified by the same reference numerals and will not be discussed separately. After completion of in 8th shown semiconductor structure 2 in a tub 17 is just the source zone 29 along with the highly doped drain zones 26 and an intermediate oxide layer 42 for the entire insulation. Thereafter, through holes are made in contact holes 49 in the intermediate oxide layer 42 placed over on the top 43 the intermediate oxide layer 42 arranged contact surfaces 44 with the different zones in the semiconductor body 3 communicate electrically.

10 shows with the subfigures 10A to 10D different increasing thicknesses of the insulating layer under the gate electrode of the second device. While in 10A As the insulation thickness increases linearly from a to b, the insulation thickness increases 10B stepped. Furthermore, it is also possible the insulation thickness progressively increasing as in 10C or progressively decreasing as in 10D as long as it is ensured that a permissible oxide field strength is not exceeded.

1

Semiconductor device (Embodiment)

2

Semiconductor structure

3

Semiconductor body

4

top of the semiconductor body

5

first Switching electrode (source)

6

second Switching electrode (drain)

7

first Device (MOSFET)

8th

Gate insulating region (MOSFET)

9

gate electrode

10

Field isolation area

11

lateral field plate

12

gate electrode

13

second Device (FET)

14

channel of the MOSFET

15

channel region

16

drift region

17

epitaxial

18

vertical field plate

19

substratum

20

buried Layer (epitaxy)

21

Body zone (Multi-layer)

22

depth Body Zone layer

23

middle Body Zone layer

24

upper Body Zone layer

25

Semiconductor wafer

26

drain region

27

conditioned subregion

28

Gate insulating region

29

source zone

30

etching window

31

highly doped epitaxial layer

32

low doped epitaxial layer

33

grave structure (Trench)

34

grave wall

35

insulation layer the trench walls

36

grave soil

37

contact layer on the ditch floor

38

electrical conductive filter material (in trench)

39

Argon ion implantation

40

Semiconductor device (Embodiment)

41

top of the substrate

42

intermediate oxide

43

top the intermediate oxide layer

44

contact area

45

protective layer

46

dashed line

47

protective layer

48

window

49

by contact in a contact hole

a

thickness the gate insulation

b

thickness the field isolation

D

drain

G

gate

S

source

Claims (25)

Semiconductor device having a semiconductor structure comprising: - one Semiconductor body arranged with two laterally on top of the semiconductor body Switching electrodes of a lateral FET, - one on a gate insulation area the top of the semiconductor body arranged gate electrode of a first device, wherein the gate electrode Inhibit state and on state between the switching electrodes the FET controls, and wherein the gate electrode on the top of the semiconductor body merges into a lateral field plate arranged on a field isolation region, and wherein the lateral field plate partially a gate electrode a second device with the characteristic of an FET forms and the field isolation region in its thickness of a thickness of the gate insulation region to a thickness of the field isolation region toward one of Switching electrodes passes, wherein the increasing thickness depends on the allowable oxide field strength. Semiconductor device according to claim 1, wherein the transition from the thickness of the gate insulation region to the thickness of the field isolation region a linear increasing or incrementally increasing or progressive increasing or degressively increasing course. Semiconductor component according to Claim 1 or Claim 2, wherein the first device is an n-channel high-voltage MOS and the second Device represents a gate and bulk controlled drift path or a p-channel high-voltage MOS and a corresponding drift path, wherein the high-voltage MOS is preferably an LDMOS. Semiconductor device according to claim 3, wherein the second Device has the characteristics of a FET and the third distance of the lateral FET. A semiconductor device according to claim 3, wherein the channel region of the second device a higher dopant concentration as the surrounding doping of the semiconductor body has. A semiconductor device according to claim 1, wherein the semiconductor structure is arranged in an epitaxial tub of a first conductivity type. A semiconductor device according to claim 1, wherein the semiconductor structure forms a cell of a cell array of a lateral FET device. A semiconductor device according to claim 1, wherein the semiconductor structure a monolithic integrated circuit breaker of an integrated Circuit is. A semiconductor device according to claim 1, wherein the epitaxial tub laterally from a vertical field plate surrounding an active area a complementary one Line type is limited, and where the vertical field plate a complementary doped substrate contacted. A semiconductor device according to claim 1, wherein said Epitaxial trough a buried highly doped layer of the first conductivity type having. The semiconductor device according to claim 1, wherein the semiconductor structure comprises a multilayer body zone arranged in the epitaxial trough, which has a lightly doped deep body zone layer as a charge compensation zone, a middle body zone layer provided with an average dopant concentration as a transition zone, and an upper body zone layer in which Switching potential at the gate electrode forms a channel of the FET structure. Method for producing a semiconductor component with semiconductor structure of a lateral FET, the following process steps having: - Provide a semiconductor wafer, the wells of the first isolated from each other Conduction type for semiconductor structures in the tubs; - bring in a multilayer body zone of the complementary conductivity type in at least one of the tubs for a lateral FET, where there is a deep weakly doped body zone layer extending laterally under a drift zone as a charge compensation zone; - bring in a highly doped drain zone of the first conductivity type at the end of Drift region; - Apply a field insulating layer on the semiconductor wafer; - conditioning a portion of the field insulating layer for a gradually decreasing etching of a Field isolation region to a gradually increasing gate insulation area a second device; - Training of the wedge-shaped Gate isolation area of the second device in the conditioned field isolation area during etching a gate isolation region of the MOSFET within the conditioned field isolation region; - bring in an upper body zone layer of the complementary conductivity type and a highly doped source zone of the first conductivity type in the center of upper body zone layer; - Apply a common gate electrode for the first device and the second device on the corresponding gate insulation or wedge-shaped gate insulation regions the semiconductor structure; - Complete of the semiconductor device. The method of claim 12, wherein the introducing a deep weakly doped body zone layer after covering to be protected Regions done by ion implantation. The method of claim 12, wherein the introducing a highly doped drain zone of the first conductivity type at the end of Drift zone after covering areas to be protected with a Mask by means of phosphorus or Arsenionenimplantation takes place. The method of claim 12, wherein applying a field isolation layer on the semiconductor wafer after the ion implantation steps by oxidation of the top of the semiconductor wafer or by means Deposition of a dielectric layer on top of the semiconductor wafer he follows. The method of claim 12, wherein conditioning a portion of the field insulating layer for a wedge-shaped etching to a gate insulation region a second device after covering areas to be protected by means of damage Implantation in the partial area of the field isolation area takes place. The method of claim 12, wherein for forming of the wedge-shaped Gate isolation area of the second device in the conditioned field isolation area during etching a gate isolation region of the FET within the conditioned one Field isolation area first an etching mask applied within the conditioned field isolation region an etching window for the Free etching of Gate isolation region of the FET has. The method of claim 12, wherein for forming of the wedge-shaped Gate insulation region is carried out a wet chemical etching. The method of claim 12, wherein the introducing an upper body zone layer of the complementary conductivity type and a highly doped source zone of the first conductivity type by masked Ion implantation followed by diffusion takes place. The method of claim 12, wherein applying a common gate electrode for the first and second device to the corresponding gate insulation or wedge-shaped gate insulation regions the semiconductor structure by means of depositing and structuring a Polysilicon layer takes place. The method of claim 12, wherein for the production insulated from each other low doped wells of the first conductivity type first a low-doped semiconductor wafer of the complementary conductivity type with a highly doped epitaxial layer of the first conductivity type is provided. The method of claim 21, wherein the highly doped Epitaxial layer of the first conductivity type a low-doped epitaxial layer of the first conductivity type is applied, which determines the dopant concentrations the tubs has. The method of claim 22, wherein a trench structure in the two grown on the semiconductor wafer epitaxial layers is introduced, each well is surrounded by a trench. The method of claim 23, wherein the trench walls with an insulating layer are coated and the trench bottom is etched free. The method of claim 24, wherein the trench bottom is provided with a contact layer to the complementary conductive semiconductor wafer, and wherein the trench structure is filled with an electrically conductive material.