DE102006056876A1 - Data transmission method for buffer memory, involves using basic clock rate processing method when clock rate, which corresponds to basic clock rates, is present, so that data words are synchronously processed corresponding to clock rates - Google Patents

Abstract

The invention relates to a method for data transmission between two data processing systems, each having slightly different clock rates and wherein the clock rates used are variable, characterized in that in the presence of a clock rate corresponding to an integer multiple of a basic clock rate, adapted for the processing of the basic clock rate Method is used in such a way that in each process step, an integer multiple corresponding plurality of data words is processed simultaneously. As a result, the advantage can be achieved that when using arbitrary integer multiples of the basic clock rate, the load of the arithmetic unit which executes the method remains constant and that the same method can be used unchanged for all multiples of the basic clock rate used.

Description

Technical area

The The invention relates to a method for data transmission between two data processing systems, which each slightly have different clock rates and the used Clock rates changeable are.

State of the art

Around Data from one data processing system to another data processing system transferred to in the case, that is the frequency with which the data processing system to which the data is delivered, with the frequency at which the data is supplied by the delivering data processing system have minimal deviations, used buffer memory. One used in these buffer stores provides the case that data are delivered faster than read out for Data is removed from the data stream. In the event that the data delivered slower than read out, this process provides for the Insert of data determined by this procedure.

One Buffer memory consists in principle of an input memory, in which the data from a first data processing system a first frequency (data rate) are stored and an output memory, from which a second data processing system data with a second frequency takes. Interposed is a procedure which transfers data from the input memory to the output memory in such a way continuously from the output memory data from the second data processing system can be taken with its frequency. For this it is necessary that If necessary, data generated by this method and in the data stream added or data is taken from the data stream.

The algorithms used in this method may be of varying complexity, for example, simply insert empty data words into the data stream, repeat the last data word, or apply mathematical methods optimized for the type of data to be transmitted. An example of an applied algorithm is described in the following literatures: O. Hodson, CS Perkins & V. Hardman, "Skew detection and compensation for Internet audio applications" . Proceedings of the IEEE International Conference on Multimedia and Expo, New York, July 2000 ,

Generally the use of a buffer memory is provided in applications, in which data can be inserted or removed in the data stream, without that suffers the usability of the data stream. This is for example, during transmission given by audio and video signals.

One another application is e.g. the telephony over the internet, being digital Data representing speech signals delivered on a packet-by-packet basis, but for output at an analogue output to equidistant ones Data is supplied to a digital-to-analog converter Need to become.

An extension of the buffer memory is a so-called jitter buffer. A jitter buffer has the task of arranging received data packets, eg encoded voice, to decode and output the data words extracted from the data packets with a precisely defined clock rate. For this purpose, he applies a method described above for matching different data rates of the received packets and the output data words. In EP 1 460 810 A2 the operation of a jitter buffer and a method for controlling a jitter buffer is described.

Consists the requirement to process several data rates in a buffer memory to be able to for example alternatively with 8kHz or 16kHz sampled signals, so must after In the prior art, the method described above applies to both Frequencies adapted and corresponding, e.g. implemented by software become. These are for each clock rate used is based on the coefficients of the method lying algoithm to calculate separately. Also, the procedure must with the clock rate (sampling rate) of the synchronous speed signal expire. this leads to to higher Demand for program memory and for equivalent higher load of the arithmetic unit.

Presentation of the invention

Of the Invention has for its object to provide a method by means of which has both a basic clock rate, which is the lowest one to process Clock rate is, as well as integer multiples of this basic clock rate can be processed. In this case, the cost of program memory and computing power requirements do not climb and for every data rate used should be constant. Extensions of existing ones Translations of buffers to the possibility of using multiple Clock rates are simplified by this invention as the method adjusted to slightly different data rates only slightly must become.

The object is achieved by a method having the features of claim 1 and a System according to claim 4 solved.

According to the invention is provided in each case the integer multiple of data, which corresponds to the current multiple of the basic data rate, respectively at the same process steps simultaneously from the input memory to transfer to the output memory.

advantageous Features of the invention are that the method for matching different data rates for all data rates unchanged can be left and that the burden of the arithmetic unit is not increases with increasing data rate.

Especially it is advantageous to multiply the number 2 series high (2, 4, 8, 16, ..) apply for it in the most common used computing units support is present, e.g. by corresponding memory addressing commands and memory access commands.

Advantageous is also an application of the method according to the invention when the method as Part of a jitter buffer procedure is performed.

A advantageous embodiment of the invention is obtained with a System for data transmission between two data processing systems, each slightly different from each other have different clock rates and wherein the clock rates used changeable in integer multiples of a basic clock rate are, in which at least one input memory and at least one output memory are provided, further comprising means for transmitting data from the at least one input memory in at least one output memory are provided wherein the transmitted simultaneously in each case a method step Amount of data corresponds to the integer multiple of the dataset which transmit at the basic clock rate becomes.

Brief description of the drawings

1 Schematic representation of a buffer memory according to the prior art.

2 Schematic representation of a buffer memory according to the invention, in the processing of the double basic clock rate.

3 Schematic representation of a buffer memory according to the invention, in the processing of four times the basic clock rate.

Embodiment of the invention

In 1 is exemplary and schematically shown a buffer memory. This comprises an input memory ES which consists of individual memory cells SZ1, SZ2, SZ3 ... SZn which can be used eg according to the "first in-first out" method and in which data are supplied by a first data processing system From which the data are supplied to a second data processing system, the data is transferred from the input memory ES into the output memory AS by means of an intermediate processing logic V.

The concrete application of this method can, for example, in one so-called jitter buffers, in this case, the first Data processing system that method or device which extracts the individual samples of a packet-oriented data stream, orders and if necessary decodes. The second data processing system would be in this Case of that method or device which outputs from the Jitter buffer takes over for example, a digital - to - analog conversion to output to be subjected to a loudspeaker.

The sequence of the method according to the invention is as follows:
Data words DW2, DW2, DW4... DWn supplied by a first data processing system are stored in the memory cells SZ1, SZ2, SZ3... SZn of the input memory ES. This is done with the speed determined by the first data processing system (clock rate). A second data processing system accepts the output data A with the speed (clock rate) determined by the second data processing system from the output memory AS. The clock rates of the two data processing systems are identical except for small tolerances. Processing logic V transmits a data unit from the input memory ES to the output memory AS in each method step. This processing logic V also provides for the removal of data from this data stream when the clock rate of the first data processing system is greater than that of the second data processing system and for inserting data into the data stream when the clock rate of the first data processing system is lower than that of the second data processing system. The removal or addition of data occurs, for example, with the algorithm as in "O. Hodson, CS Perkins & V. Hardman, "Skew detection and compensation for Internet audio applications" . Proceedings of the IEEE International Conference on Multimedia and Expo, New York, July 2000 "is described.

2 schematically shows an embodiment of a buffer memory according to the invention in the implementation with double clock rate of both data processing systems compared to the case in 1 , According to the invention, the amounts of data corresponding to the integer multiple of the basic clock rate, in this case two times, are transferred from the input memory ES to the output memory AS in a processing step of the method. The applied algorithm remains unchanged. This is in 2 indicated by 2 arrows pointing to 2 memory cells. In a practical implementation, for example, instead of one byte (8 bits), one word (16 bits) could be processed, a change that is easy to make in all common programming languages. The load of the arithmetic unit remains opposite to that in 1 case constant and the algorithm of the processing logic V requires no change.

3 schematically shows a further embodiment of a buffer memory in inventive implementation in operation with four times the clock rate of both data processing systems compared to the case in 1 , According to the invention, in a processing step of the method ie the integer multiple of the basic clock rate, in this case four times, corresponding amounts of data are transferred from the input memory to the output memory. This is in 3 indicated by 4 arrows pointing to 4 memory cells. In a practical implementation, for example, instead of one byte (8 bits), a double word (32 bits) could be processed, a change that is easy to make in all common programming languages. The load of the arithmetic unit remains opposite to that in 1 case constant and the algorithm of the processing logic V requires no change.

A

output data

e

input data

AS

output memory

IT

input memory

V

processing logic

SZ

memory cell

DW

data word

Claims (4)

Method for data transmission between two data processing systems, each having slightly different clock rates and wherein the clock rates used are variable, characterized in that in the presence of a clock rate corresponding to an integer multiple of a basic clock rate, adapted for the processing of the basic clock rate method in such a way is used, that in each process step, an integer multiple corresponding plurality of data words DW is processed simultaneously. Method according to claim 1, characterized in that the multiples of the basic clock rate the 2 high n times the Grundtaktrate are limited. Application of a method according to one of claims 1 or 2, characterized in that the method is carried out as part of a jitter buffer method. System for data transmission between two data processing systems, each slightly different from each other have different clock rates and wherein the clock rates used in integer multiples of a basic clock rate are changeable, characterized in that at least one input memory ES and at least one output memory AS are provided that further Means for transmitting of data from the at least one input memory ES in the at least an output memory AS are provided, wherein in each case a step simultaneously transmitted amount of data the integer Multiples of the amount of data transmitted at the basic clock rate becomes.