DE102006006782B4 - A method of handling design errors of an integrated circuit layout - Google Patents

Abstract

Method for handling errors in the review of a design of an integrated circuit,
a. wherein the design of the integrated circuit is checked for errors according to given rules,
b. the design having multiple cells,
c. in the case of a deviation of the design from the given rules an error is detected,
d. where the detected error is written to an error file,
e. wherein at least one detected error is written into a mask file if the error is allowed as a permitted error despite the deviation from the rules, wherein at least
a legal error indicating the cell is stored in the masking file in which the error occurs, creating for each cell a masking file with allowed cell errors, the masking file having data about the nature of the error, the position of the error in the cell and data about the position of the cell in relation to the ...

Description

The Invention relates to method according to claim 1 and 13.

The Dimensions of integrated circuits continue to decrease, so that parasitic Effects play an increasingly important role in the functioning of the play integrated circuits. To avoid unwanted parasitic It is necessary that effects in the development of integrated effects Circuits the layout of the masks to make the integrated Circuits accurate checked for errors. In reviewing the Layouts a design rule comparison (design rule check) is performed to to check if the structures determined in the layout correspond to the given rules. For one However, custom layout design sometimes requires that error compared using an automatic program be recognized to the design rules, still be allowed. This allows an individual adaptation of the layout to the desired functionality and to the defined framework conditions.

The Layout is being used by using automatic programs a computing unit checks for compliance with design rules and errors, which are detected are stored in an error file. Becomes now a detected error nevertheless admitted, so is recognized for the Error filed a mask file. By comparing a detected errors with the errors stored in the mask file become allowed errors when creating a bug report or skipped on a screen when graphing or not shown. In this way it is possible that efficiently only the Error checking the Layouts are displayed or output that are not allowed Represent error.

A corresponding method is for example from the US patent US 6 418 551 B1 known.

Out JP 63119244 A For example, a design system for an integrated circuit layout is known. A description is given of a method for checking an integrated circuit layout whose task is to easily detect real errors by means of a design rule check (DRC) and to facilitate the updating of a database with a conventional DRC tool. The design rule monitoring is carried out in advance for each basic cell with the aid of a CAD tool and output data of the CAD tool are stored in the database corresponding to the basic cells.

Layout data, using layout design using basic cells are subjected to a design rule check (DRC). error data are output as graphic data. The design rule check becomes to each basic cell in advance in the same way as for the layout data applied and the output data output as error data assigned to a database corresponding to the basic cells. The basic cell, which is arranged in the layout data is passed through subcells replaced a calculation route. By subtracting the layout data with replaced subcells from the usual ones DRC error data can virtually eliminates error data relating to the basic cells become.

Out JP 03234039 A For example, a method for checking a layout structure is known, wherein information about a reference source and coordinate values are stored in the reference source for error data of a DRC method. The object of the method described is to reduce the time for a manual check of errors and to reduce the possibility of an error by extracting the name of a cell to which an error segment belongs and information about coordinate values in a cell. Furthermore, the same group number is assigned to error segments whose information matches. In the process, layout data is processed and the name of a cell in which an error segment occurs is assigned to an error segment information. Furthermore, coordinate values of error segments of a cell are detected. If the coordinate values of the errors match, the error segments are assigned to a common group. In this way, a coordinate value does not have to be output for each individual error segment.

The The object of the invention is an improved method to provide for handling design errors.

The invention relates to a method for handling design errors, in particular design errors, wherein an integrated circuit design is checked according to predetermined rules, wherein the design comprises a plurality of cells, wherein a deviation of the design from the predetermined rules, an error is detected the error is written into an error file, whereby at least one detected error is written into a masking file if, despite the deviation from the rules, the error is treated as a permitted error, a permitted error indicating the cell being stored in the masking file, in the the error occurs. In the embodiment of the method according to the invention, an error is assigned to the cell in which the error has occurred during the check of the design. This is a clear assignment of the error possible. The error is stored in the form of a file containing a description of the error, an indication of the cell in which the error lies, and an indication of coordinates describing the position of the error within the cell.

On this way it is possible allowed errors to be assigned to a cell. This is an increased flexibility in the Treatment of allowed errors possible.

In a further embodiment The procedure handles layout errors, with a built-in layout Circuit is checked by given rules, the layout being multiple Cells, wherein in a deviation of the layout of the given rules an error is detected, the error in an error file is written, with a detected error is written to a masking file if the error persists the deviation from the rules is treated as a permitted error, whereby a permitted error with specification of the cell is stored in the masking file is where the error occurs.

In a further embodiment will be in the review of the Design or layout with given rules and recognition of an error the error is assigned to an error class. Thus are all errors are classified in the error file.

In a further embodiment The procedure is also a permitted error according to predetermined Rules divided into one of several classes, with allowed errors The different classes are treated differently when checking for errors become. For example, errors of different classes are dependent on a determination, for example, in an error report or in the Presentation of permitted errors handled differently. So can a permitted error of a first class during the error report or not taken into account in the presentation of the allowed errors become. Mistakes of a second class, on the other hand, will be either at Error report and / or taken into account in the presentation.

In a further embodiment In the method, errors that are identical, i. for example have a layout geometry with an identical geometry in the same class divided. This is a simplified treatment the error in the form of classes of errors possible. Thus, for example By establishing that mistakes are made of certain classes be treated in a defined way. Thus is It may not be necessary to customize each error individually treat, but it is sufficient, a class of a corresponding Attributable to treatment.

The The invention will be explained in more detail below with reference to FIGS. Show it:

1 a schematic representation of a computer system for carrying out the method,

2 a schematic program flow for designing and manufacturing an integrated circuit,

3 a schematic representation of an error file for an admitted error,

4 a schematic representation of a program for checking a layout for design errors,

5 a schematic representation of a geometric error,

6 a schematic representation of classes of errors,

7 a method for creating a mask file, and

8th a schematic representation of a layout.

Description of a preferred embodiment

The The present invention will now be described more in detail with reference to the accompanying drawings explains in which preferred embodiments the invention are shown. However, the invention can be embodied in various ways embodiments be realized and is not limited to the illustrated embodiments limited. The function of the present invention as follows explained can be in the form of a hardware, in the form of a software or in a Combination of hardware and software can be realized. Farther For example, the present invention may be in the form of a computer program product a computer readable storage medium having computer readable program codes be realized on the storage medium. As a computer-readable storage medium can any type of disk, CD-ROM readable storage medium can any type of floppy disk, CD-ROM or optical or magnetic storage device be used.

1 shows a schematic representation of a hardware arrangement of a computer system 10 which has an integrated circuit verification system. The computer system 10 preferably has a computer 11 on having a review program 12 has that from the computer 11 can be processed. The review program 12 is trained to be an elek trical structure of the integrated circuit and / or to check a layout of the integrated circuit. The computer system 10 has a memory 13 , a data drive 14 or a data bus 15 , About the store 13 , the data drive 14 or the data bus 15 For example, the data representing the electrical structure and / or layout of the integrated circuit layout may be supplied to the computer 11 be supplied. Furthermore, the computer system 10 an ad 16 , a printer 17 and an input unit 18 on. As an example, the verification program 12 on a computer system 10 , such as an Ultraspark ^™ 5 Work Station from Microsystems Computer Corporation.

2 shows a schematic structure of a program for developing, testing and manufacturing an integrated circuit.

At a first program step 20 A specification for the electrical characteristics of the integrated circuit is created. Subsequently, at a following program step 21 a physical design of the integrated circuit is performed based on the specification taking into account given design rules. In this case, a functional design of the integrated circuit is created as a structural description on a gate level or an electrical level.

Depending on the chosen embodiment is optionally in a third program step 22 the functional design checks for predetermined rules, in particular an electrical correct functioning. Will at the third program step 22 If it detects that the functional design has errors, they will be in an error file 80 stored. It then checks to see if the detected error is in a mask file 81 is stored. Is the detected error not in the mask file 81 filed, so becomes the second program step 21 returned and corrected the error in the functional design.

However, if the comparison proves that the detected error is in the mask file 81 is stored as a permitted error, the detected error is retained and not corrected in the functional design.

Depending on the chosen embodiment, the mask file may already be 81 in the data store 13 be filed or during the execution of the first review process will be at the third program step 22 an operator selected to mark a detected error as a permitted error. If the operator identifies a recognized error as a permitted error, the permitted error in the masking file becomes 81 stored. The error file 80 stays unchanged. The masking of supposedly correct errors, ie allowing allowed errors, is accomplished by matching data of the error file and the masking file.

Depending on the chosen embodiment may also on the third program step 22 be dispensed with and after the second program step 21 the fourth program step 23 be processed.

After checking the functional design with the first examination procedure in the third program step 22 becomes the fourth program step 23 branched. At the fourth program step 23 From the functional design, a layout design is created for the masks required for the manufacture of the integrated circuit. In the process, a physical design is created from the functional design, which includes the layouts of the masks of the integrated circuit.

Of the physical design is a very complex process in the Usually divided into a sequence of manageable small design steps becomes. In general, the layout is done using multiple cells created an abstraction of the integrated circuit and thus mastering the layout design e.g. enable at gate level. The design of the layout of the individual gates creates one Cell library that creates the objects for the algorithms of the geometric layout of the overall circuit. To The definition of cells becomes the available place of integrated Circuit divided into larger blocks. At the same time, the larger blocks will open the area distributed in the way that possible little area is consumed. The blocks again, parts of the integrated circuit, e.g. an array a memory chip, or pads. After the placement The cells are used to determine the connections between the cells. The cells can For example, individual gates, individual registers, individual counters have. Dependent from the embodiment can Cells also larger circuit blocks, such as e.g. DRAM memory cells, an array of memory cells, input / output units etc. represent.

After creating the layout of the integrated circuit in the fourth program step 23 will be in the following fifth program step 24 Checks if the specified layout corresponds to given design rules. The computer has it 11 via an appropriate database stored in memory 13 is stored, and in which the permissible design rules, ie the permissible geometric structures for the layout are stored. The design rules are very much dependent on the particular technology used to make the integrated circuit. In addition, the design rules are under Um would be different from the individual chip manufacturers. For example, design rules apply to minimum distances between electrical traces, minimum widths of electrical traces, overlaps of conductive layers, and inner layers of individual layers and layer combinations.

Detects the computer 11 When checking the layout that areas of the layout do not comply with the given design rules, they will appear in a second error file 82 stored. It also checks if the detected error is in a second mask file 83 is stored. Returns the check that the detected error in the second mask file 83 is stored, the error is treated as a permitted error. In the second mask file 83 Errors are filed that do not comply with the design rules but are still allowed for other reasons. The second mask file 83 can already exist or be created by an operator while checking the layout. For this purpose, a detected error of the operator is displayed and the operator can recognize the detected error as an allowed error in the second masking file 83 save. This is possible if the detected error does not comply with the design rules, but is still allowed by the operator.

at the review of the Layouts, the layout in a further embodiment in a hierarchical Structure checked. The exam The layout is done in one embodiment according to a hierarchy tree the cells, preferably bottom-up.

For one allowed error is in both the error file and in the Mask file each stored a date. The writing of a Date in the error file or mask file is either automatically or as instructed by the operating personnel of the computer system. The date of the error indicates a name of the error, the coordinates the error in the cell where the error was detected, and the Form of the error, for example, the type of polygon, the number the corners and the coordinates of the polygon also indicate the date the coordinates of the cell with which the cell is integrated Circuit is placed on. Depending on the embodiment the date may contain only individual elements of it.

Returns the check of the layout at the fifth program step 24 that an error was detected and the error was not detected in the second mask file 83 is stored, so the error is not a permitted error and is the fourth program step 23 returned. At the fourth program step 23 the layout changes accordingly to avoid the error.

Returns the comparison at the fifth program step 24 that the detected error is already in the second mask file 83 is stored, the error is allowed as a permitted error and there will be no change in the layout with respect to this error at the fourth program step 23 carried out.

After the layout has been checked and all detected and unauthorized errors have been eliminated, the fifth program step is completed 24 the sixth program step 25 in which the layout is used to produce an integrated circuit with corresponding semiconductor technology.

Depending on the chosen one embodiment can additionally to the review of Draft rules to perform an LVS comparison in which the hierarchical Layout opposite the schematic design is checked. For this purpose, the layout becomes a hierarchical netlist of components and networks created and the hierarchical netlist with the electrical Netlist of functional design compared. Also with this Can compare Errors are detected in the same way as in the layout comparison be treated.

3 shows in the schematic representation of a file for an error, which is stored accordingly in an error file and possibly in a mask file. The file has a name for the error, a name for the cell in which the error was detected, coordinates of the error, the description of the polygon with the number of vertices.

4 shows a more detailed representation of an embodiment of the fifth program step 24 in which the layout is checked for design flaws.

At a first program point 30 the program detects an error. In a following second program point 31 the computer checks 11 whether the error can be assigned to one of several error classes. The computer checks 11 the error classes that are in memory 13 are stored. For every class is in memory 13 an information about the type of error class filed. To identify the nature of a fault, for example, geometric data representing geometric structures is used. Detects the computer 11 When verifying that the error can be assigned to an error class, the computer rearranges 11 at the following third program point 32 the error of an error class and identifies the error with a label for the error class.

In a further embodiment, at the second program item 31 checks if the same error has already been detected and an error class has been created for it. If this is the case, the newly detected error is assigned to the same error class. Is that at the first program point 30 Recognized errors, so is the second program item 31 created a new error class and assigned the error to the new error class.

At the following third program point 32 it is checked whether the newly detected error represents a permitted error. For example, an error class may be used as an allowed error class in memory 13 be filed. In addition, the newly detected error of an operator can be displayed for evaluation. If the operator identifies the newly detected error as a permitted error, the error is stored in the second mask file. In addition, the operator can specify that all errors that are assigned to an error class represent allowed errors and, after recognition, are also entered in the mask file in addition to the error file.

5 shows an example of a geometric structure corresponding to an error. In this case, the layout has the fault that a first interconnect L1 has too small a distance D from a second interconnect L2.

Depending on the chosen one embodiment If a permitted error is then assigned to an error class, if the allowed error does not match the type of error of the error class, but is still in a certain similarity range. For geometric figures are deviations from, for example 3% in one direction.

By an appropriate input, the operator can use the computer 11 to suggest for each or all errors a new error class for this type of error in memory 13 create and take into account in further reviews.

After completion of the third program point 32 the query takes place at a following fourth program point 33 which error classes of the allowed errors or which allowed errors are output in an error report or in the display of the errors found on the display 16 should be displayed. An operator may specify the appropriate classes or individual errors. Depending on the selected embodiment, the classes that are to be displayed or taken into account in the error report may already be preset. In this way, the error classes can be used to simplify the structuring and handling of errors.

6 shows a schematic representation of a masking file 81 in the classes 41 . 42 . 43 are arranged for three different types of errors. In a first class 41 a first error F1 and a second error F2 are stored. In a second error class 42 is a fourth error F4 filed. In a third error class 43 is a fifth error F5 filed. The first and second errors F1, F2 belong to the same error class, since the two errors are identical or at least have a fixed similarity, for example fixed geometrical dimensions of a given geometric structure.

7 shows a schematic overview of another embodiment of the method, the computer system 10 is processed. At a first program block 50 will the computer 11 the data file for the description of the geometric layout supplied in the form of a GDSII format. From the data file of the first program block 50 the computer creates at a following second program block 51 a cell list, that is, the structure and structure used to create the integrated circuit layout. 8th shows a corresponding cell structure of the layout. The cell structure of the layout with the positions of the individual cells in the hierarchically overlying cells is combined with the information about the cells used and the structure and hierarchy tree of the cells to a decomposition block 52 forwarded. In addition, the information about the cell structure, in particular the position of the cells in the hierarchically higher cells, from the second program block 51 to a connection block 53 forwarded.

The computer 11 leads to the data file of the layout of the program block 51 at a processing block 54 checking if the layout complies with the given design rules. Due to the error found in the layout of the computer is from the computer 11 created an error file and a mask file. In the error file all errors are stored, that by the computer 11 were found. The mask file stores the errors that represent permissible errors, that is, that violate the rules specified, but are still kept unchanged in the layout. In addition, the errors are classified in a training in error classes and provided with a label for the associated error class. Preferably, an error is assigned to a cell in which the error first occurred in the hierarchical check. Both the error file and the mask file will be at a following third program block 55 created in RVE format. In addition, the computer 11 starting from the processing block 54 a pattern file at a sample block 56 creates the errors found in the form a graphically displayable file, preferably in GDSII format stores. Depending on the chosen embodiment, the detected errors can be graphically displayed 16 being represented.

Starting from the program block 55 Creates the arithmetic unit at another processing block 57 created an extended file. In this case, a detected error is evaluated by an operator or automatically under predetermined rules as a permitted error. For this, the allowed error is written into a masking file. The extended file contains both the error file and the mask file and can also be displayed graphically. Starting from the further processing block 57 may depend on the program selected in a presentation block 58 both the detected errors and / or the allowed errors graphically with the display 16 being represented.

Starting from the further processing block 57 the mask file will be in a subsequent decomposition block 52 taking into account the cell structure of the layout in each case a masking file for each cell converted and stored in a Waiverdatei. In this case, the permissible detected errors are respectively assigned to the cell in which the error was first detected during the hierarchical check. Thus, a mask file is created for each cell in which errors and / or allowed errors occur.

Starting from the decomposition block 52 becomes at a following production block 59 created a database with all masking files of all cells of the layout. From the database with the masking files is at the following connection block 53 creates a data file containing the mask files for the cells that are listed in the cell list and for which the layout was checked. The layout of the layout and especially the hierarchical structure of the layout are taken into account. Preferably, an error is only assigned to the cell in which the error first occurred during the hierarchical check. At a following fifth program block 61 a check is made as to whether there is an associated error in the error file for each error of a mask file. For this, the data of the current error file from the third program block 55 considered. The error file is recreated each time it is checked. The mask files may also be from previous passes where the layout was checked. This allows the masking files to be used more often. If the check reveals that for a permissible error of the masking file no corresponding error is stored in the error file, the error is possibly deleted from the masking file after a query and a checked database for the masking files of the individual cells is created. The checked database becomes the processing block 57 fed. The files of the errors are like in 3 described constructed. Due to the described method, it is possible to reuse once created masking files in later reviews of the layout, which may also include other cells of the layout. Since there is a masking file for each cell, the location of each allowed error is stored in the allowed error cell, and moreover, the position of each cell relative to the layout is stored, the masking files of the cells can be reused in testing other cells since the position of a permitted error of one cell can be calculated for each other cell and for the layout.

In order to can the data of the masking files are transferred to different hierarchical levels and on appropriate reviews again be used. Thus, it is not necessary for each review new Create masking files.

8th schematically shows a layout of an integrated circuit 70 , The integrated circuit 70 has a first cell 70 on, which is a second cell 71 , a third cell 72 , a fourth cell 73 and fifth cells 74 having. The first cell represents a random access memory (RAM), which in turn contains a plurality of subcells which are not shown in detail. The subcells may in turn contain further subcells. Depending on the layout used, the cells can be formed as sub-cells up to the transistor level. This results in a hierarchical structure of the cells. Will now be the layout of the integrated circuit 70 checked, the smallest subcells are checked first. Subsequently, the cells, which in turn contain the subcells, are checked hierarchically upward. In this way, a hierarchical order of the cell check is performed. For each cell that contains subcells, on the one hand, the coordinates are stored, with which the cell is positioned on the block. In addition, for each of the subcells, the coordinates are stored with respect to the cell with which the subcells are positioned with respect to the cell.

Claims (13)

A method of handling errors in the review of an integrated circuit design, a. wherein the design of the integrated circuit is checked for errors according to given rules, b. the design having multiple cells, c. in the case of a deviation of the design from the given rules an error is detected, d. wherein the detected error is written to an error file, e. wherein at least one detected error is written to a masking file if the error is permitted as a permitted error despite the deviation from the rules, wherein at least one allowed error indicating the cell is stored in the mask file in which the error occurs, for each Cell, a mask file is created with allowed cell errors, the mask file having data about the nature of the error, the location of the error in the cell, and data about the position of the cell relative to the layout. Method according to claim 1, characterized in that that a layout of the integrated circuit based on given Rules is checked that the layout has multiple cells that in case of a deviation of the Layouts from the given rules an error is detected. Method according to claim 1 or 2, characterized that a permitted error according to given rules in a class is divided, and that in case of admitted errors different Classes these different when checking be treated. Method according to one of claims 1 to 3, characterized that identical errors are divided into a class. Method according to claim 2, characterized in that that allowed mistakes of the layout, which have a similar or same geometry have to be divided into a class. Method according to one of claims 1 to 5, characterized that error in checking the Design and that allowed errors in a review not are displayed. Method according to Claim 6, characterized that a class is determined, and that allowed errors of the particular Class are displayed and the allowed errors of the other classes not be displayed. Method according to one of claims 1 to 7, characterized that the draft is in a given hierarchy of cells Error is checked and that a permitted error is stored with an indication of the cell in which the allowed error in a hierarchical check of the Cells was first detected. Method according to one of claims 1 to 8, characterized that an error file for a allowed error is stored, a description of the error, an indication of the cell that contains errors and an indication of Coordinates that indicate the position of the error within the cell and describe the position of the cell in the layout. Method according to one of claims 1 to 9, characterized that the permitted errors in a misreport report not issued and / or not displayed. Method according to one of claims 1 to 10, characterized that for allowed error files are stored in a memory, and that for every Cell creates a mask file that allowed the files of the Have errors contained in the cell. Method according to one of claims 1 to 11, characterized that when reviewing the integrated circuit a database with already determined masking files for the Cells is used, the database is then checked, whether for any error of the masking files an error in an error file included is that the errors in the masking files are deleted when not the same error is stored in the error file, and that the revised ones Masking files for the ad or a report about the allowed error is used. Method for handling allowed errors the review of a Design of an integrated circuit, a. being the design the integrated circuit is checked for errors according to given rules, b. the design having multiple cells, c. being at a Deviation of the design from the given rules an error is recognized, d. where the detected error is in an error file is enrolled, e. where at least one detected error is written to a masking file if the error persists the deviation from the rules is allowed as a permitted error, in which in the review of integrated circuit a database with already determined Maskierungsda shares for the Cells is used, the database is then checked, whether for any error of the masking files an error in an error file containing the error in the mask files is deleted, if not the same error is stored in the error file, and the revised ones Masking files for the ad or a report about the allowed error is used.