DE102004017533A1 - Method for etching porous dielectric - Google Patents

Abstract

The invention relates to a method for etching a porous dielectric. The method comprises plasma etching the thin layer in a plasma etching chamber with CF¶4¶, H¶2¶ and a noble gas, wherein the ratio of CF¶4¶ gas flow to H¶2¶ gas flow is between 1.33: 1 and 2, 7: 1 and the noble gas flow is greater than about 42% of the total gas flow in the plasma chamber.

Description

The This invention relates to methods for etching a porous dielectric layer, which forms part of a connection structure on a substrate, such as for example, a wafer or a multi-chip module is formed. The invention is particularly, but not exclusively, contemplated Method of etching a porous dielectric layer, which forms part of a dual damascene structure. The invention in particular relates to a method for etching the upper part of a Dualdamaszen structure.

Around to reduce the RC products in tie layers, it is necessary to reduce the capacitive coupling between adjacent conductors. It is therefore materials with low dielectric constant (k) desirable and it is known that a vacuum gap has the lowest value k = 1 has. A known method for reducing the k value in huge Insulators is insertion a porosity such that a matrix of material and recesses present is, which reduces k to a value smaller than the one from the matrix.

such porous Materials show numerous problems in the integration into practical Devices, and an additional complexity This results from the fact that ever smaller structures are required are. To date, have not been porous Dielectrics successful in known devices in their mass production for the public Sales integrated.

For example there is a potential integration scheme at nodes of 65 nanometer technology, thereby depositing the total thickness of the dual damascene dielectric with no etch stop layer therein becomes. The trench is then for etched a time-controlled duration into the dielectric, and after a partial penetration into the thickness of the dielectric is the etching completed. Beyond and beyond well-known, desirable Aspects of Anisotropic Etching There is the additional Need for the bottom of the etched trench to be smooth is. This is obviously a big challenge if that Dielectric porous is (i.e., contains recesses). If the recesses are very small, then stopping is in the Dielectric with recesses acceptable in some respects, wherein a "healing" of these recesses also desirable is.

Applicants have developed a porous dielectric known as Orion ^™ and described in various patent applications in the name of the Applicants, for example in WO / 03/009364. This material has a k-value in the range of 1.8 to 2.6 and is currently undergoing testing for integration in 65 nanometers (and less than 65 nanometers) design rule logic devices with a k-value of 2.2 to 2.5. This material was etched in this invention, although the invention relates to any low-k porous carbon doped silicon dioxide dielectrics, such as a SiCOH type material. Typically, such carbon-doped oxides have methyl groups contained therein. The carbon concentrations (and hence the hydrogen concentrations) can be varied, with higher concentrations resulting in porosity under certain circumstances.

It It should be emphasized that this application concerns unetched sidewalls. It is known to achieve anisotropic (directional) etching of polymer on side walls deposit to protect them from chemical attack while a bombard the etching front (Bottom of the trench) removes this protective layer and thereby a down directed etching allows. After etching The photoresist and remnants of the polymer are removed.

It is further understood that in almost all cases material layers forming an interlayer completely etch through it, such that the etch process is etched more slowly on an "etch stop" layer or any other layer etched by the etchant used than that of FIG corrosive layer, stops. It is somewhat unusual to terminate the etch prior to full etch of a layer, however, eliminating an etch stop layer is highly desirable because it reduces the effective k-value of the structure and reduces the number of interfaces between layers , Applicants have discovered that, which may not be surprising, a rough trench bottom is formed when such partial etching is performed on a porous dielectric. This is off 1 (a) and 1 (b) seen.

1 (a) and (B) show rough etching fronts in a scanning electron microscope image after partial etching using CF ₄ and CH ₂ F ₂ gases at 1250 Watt plasma power of a helicon source, 400 W plate (wafer) biasing capacity, 2 mTorr, with wafer-helium backpressure of 15 torr (giving a wafer surface temperature of about 90 to 100 ° C, as indicated by temperature-sensitive labels) in a MORI ^™ process chamber, such as it is supplied by the applicants.

1 (a) shows a dual damascene structure. The etched porous oxide surface is with 1 designated.

It There is therefore a need for an improved etching process, around a smooth bottom of an etched Feature which is within a carbon doped porous dielectric Layer made of silicon oxide is available too put.

In one aspect, the invention relates to a method of etching a thin, carbon-doped silicon dioxide type dielectric layer comprising plasma etching the thin layer in a plasma etch chamber with CF ₄ H ₂ and a noble gas, wherein the ratio of CF ₄ gas flow to H ₂ gas flow is between 1.33: 1 and 2.7: 1 and the noble gas flow is greater than about 42% of the total gas flow through the plasma chamber.

In another aspect, the invention provides a method of plasma etching a porous dielectric layer of carbon doped silica material, such as a SiCOH material, with the following desired characteristics: characteristics achieved result etch depth 40-70% of the thin film thickness etching rate 200-500 nm / min Selectivity to the photoresist greater than 5: 1 ARDE percentage (ARDE = aspect ratio dependent etch rate; aspect ratio dependent etch rate: the difference in etch rate for features with different aspect ratio) less than 5% Micro-trenching not visible in an electrograph roughness not visible in an electrograph when the surface is viewed in top view or at 45 ° gloss angle (with a minimum magnification of 20,000)

Even though the invention has been described above, it is understood that these any combination according to the invention of features which are described above or in the following description are disclosed.

The The invention can be carried out in different ways, and below Exemplary preferred embodiments are with reference on the attached Drawings described. These show in:

1 (a) and (B) Scanning electron micrographs (SEM) of an etching front and partial etching using CF ₄ and CH ₂ F ₂ gases;

2 (a) . (B) and (C) analogous etching fronts using CF ₄ and H ₂ with increasing amounts of argon present;

3 (a) the etch front, which results in a non-optimized process;

3 (b) the effect of a partially oxygen-based covering step on the material of 3 (a) ;

4 (a) and (B) the effect of reduced backside cooling;

5 (a) and (B) analog SEM images for a particular set of process conditions;

6 (a) and (B) the result of the process using reduced cooling for certain process conditions with 7 can be compared;

7 an analog representation for the same process as 6 (a) and (B) but with increased cooling; and

8 (a) and (B) the surface of the etch front before and after a mask etch has occurred.

Although a rough etching front 1 (a) and (B) how they are in 5 As it can be seen as an obvious consequence of the porosity of the thin film, it was observed that the surface roughness was larger than the average polymer size of 1 to 4 nanometers. This suggests that the roughness of the etch front is not simply the result of exposing the pores, and it has therefore been postulated that an improved etch process may result in a smoother etch front / trench bottom.

Initially, Applicants have found that noble gas additions, such as argon, improve the smoothness of the etch front, as in FIG 2 (a) . (B) and (C) shown.

Everyone in 2 The above processes were carried out in the above-mentioned MORI ^™ chamber with a chamber pressure of 110 mT, a plasma power of 700 W applied to only the wafer plate and a helium back pressure on the wafer of 15T (ie, the wafer temperature was about 90-100 ° C).

The in the examples according to 2 (a) . (B) and (C) used gas flow rates were:

at 1 is the etch front / bottom surface of the porous oxide, with no argon added at (a), argon added at (b), and most (c) argon added to a reactive ion etch process of CF ₄ + H ₂ at (c). It will be seen that the addition of argon leads to a smoother etching front 1 leads, with the etching front at 2 (c) is the smoothest. This is the exact opposite of what would be expected, since it would be expected that increasing the physical sputter etch components by adding a heavy noble gas would increase the roughness of the etch front of a non-uniform density material.

The process according to 2 (c) is still not acceptable and shows for example 2 pronounced microtrenching.

It should be emphasized that the Applicants have chosen a mixture of CF ₄ and H ₂ instead of the otherwise common CF ₄ / O ₂ mixture as the etching gas in all cases for the following reasons.

CF ₄ is a well-known and readily available source of fluorine and, due to its low polymer production, can etch with lower wafer bias powers than other known fluorine-containing etch gases. Although thin silicon dioxide layers are generally etched with a gas mixture of CF ₄ and oxygen, it has been found that oxygen should be excluded from the etching process, as Applicants believe that methyl groups can form in the thin layer. which would be stripped off the thin layer by the O ₂ .

Hydrogen was then selected because of its ability to purge fluorine and increased selectivity due to suppression of the etch rate of silicon as compared to silicon dioxide or carbide as an additional process gas. Hydrogen plasma is used to heal or treat applicants' materials GB-A-0020509 known with low k value. It is known that higher levels of hydrogen have only a limited effect on the etch rate of silica and increase polymerization. Therefore, the plasma would provide hydrogen radicals directly from the hydrogen gas rather than CH ₂ F ₂ gas.

argon because of his ability the effectiveness to increase the ionization, selected as heavy noble gas (it can others are also selected such as krypton or xenon).

Considerable DOE (Design of Experiment) experiments were then performed, leading to the conclusion that a CF ₄ : H ₂ ratio of 2: 1 is best for this application and a range of the ratio of CF ₄ to H ₂ Gas flow between 1.33: 1 and 2.7: 1 is acceptable.

This is an unusually high concentration of hydrogen. It is generally believed that in a gas mixture of CH ₄ + hydrogen, the etch rate for both silicon dioxide and silicon at about 40% hydrogen in the gas mixture of CH ₄ + H ₂ drops to about zero due to the degree of polymerization.

It has also been found that for the CH ₄ and H ₂ flow rates used, the argon flow rate should be at least 90 sccm and preferably about 77% of the total gas flow rate. In a process with 80 sccm of CF ₄ and 40 sccm of hydrogen, the argon gas flow rate was preferably 400 sccm and at least 90 sccm.

In 3 (a) is another, not optimized process shown. at 1 the etching front is shown and shows a certain surface roughness, for example 4 and microtrenching, for example, at 2 after complete etching into about 80 percent of Orion porous SICOH material with a k value of 2.2. ARDE is less than 2% (0.25 nm / 1.25 μm structures), the selectivity to photoresist 3 is greater than 6: 1 and the etch rate is greater than 300 nm / min. Same structure according to 3 (a) was then subjected to partial oxygen based masked stripping, and the results are in 3 (b) shown. As can be seen, there is a high roughness on the etched bottom of the trench.

It has been found to further improve the results of the etching which is doped within the thickness of the porous carbon doped oxide stops, two more changes necessary. First, the porous SICOH material should have small pores with tightly controlled Have distribution. A material with an average Pore size in the range from 1 to 4 nanometers is etched smoother than a porous dielectric with a big one average pore size, for example from 4 to 5 nanometers and pores ranging in size from 2 nm to 12 nm. It has also been shown that the wafer temperature during etching the surface roughness the etching front affected.

A higher Wafer temperature leads to a smoother etching front. However, the maximum temperature is due to the reticulation of the photoresist limited.

It is notoriously difficult to determine the temperature of a thin film during an etching (or deposition) process, since it is virtually impossible to measure it. There may be attempts to estimate using temperature-indicating labels or "Sensarray ^™ " wafers with embedded thermocouples, but these are only approximations. However, it has been found that reducing the pressure of helium on the backside of the electrostatically clamped wafer (thereby reducing the thermal coupling of the wafer to the electrostatic clamp used) improves the smoothness of the etch front, as in FIGS 4 (a) and (B) shown. These are submicron structures etched to 86% of the Orion thin film thickness with the coolant temperature of the electrostatic clamp set to -15 ° C. 4 (a) shows the etch result with 15 Torr helium pressure (sufficient to thermally couple the wafer to the clamp with a small thermal gradient) and 4 (b) shows the result 2 Torr. As can be seen, the etch front 1 at 4 (b) smoother than at 4 (a) ,

temperature scanning labels on the surface of a wafer show one Wafer surface temperature from 93 to 99 ° C for one Pressure of 15 Torr, -15 ° C coolant temperature and 143 to 149 ° C for 2 Torr helium backside printing and -15 ° C coolant temperature.

A acceptable wafer surface temperature for the Process of this invention is therefore determined to be above 100 ° C, preferably this temperature in a range of 130 ° C to 220 ° C, in particular between 130 up to 170 ° C and more preferably at about 150 ° C (the upper temperature is limited by the photoresist, higher On the other hand, temperatures are at least potentially equally preferred).

The preferred minimum pressure for the process is 80 mTorr. 5 (a) and (B) show the surface roughness 4 the etching front 1 for gas flows of 70 sccm CF ₄ , 30 sccm H ₂ , 90 sccm Ar and a 700 W line with a wafer-helium back pressure of 15 T (wafer "cold").

6 (a) and (B) show a smooth etching front 1 after etching with a higher wafer surface temperature (130 to 170 ° C). This is achieved by reducing the helium backside temperature to 2 Torr, whereby the thermal coupling between plate and wafer is reduced. The process conditions were otherwise: CF ₄ - 84 sccm; H2 - 42 sccm; Ar - 400 sccm; Pressure 200 mT and power 1,000 W.

7 shows rougher etch fronts after processing with lower wafer surface temperature (-10 ° C to + 99 ° C) when the helium backside pressure 15 Torr is. Here, the process conditions were substantially identical to those according to 6 with slight changes in the flow rates of CF ₄ and H ₂ , which were respectively 82.55 sccm and 37.5 sccm.

To prove that the improved smoothness of the etching front surface in the invention is not due to polymer residues covering the etching front / bottom, an N ₂ + H ₂ stripe was used after the etching to remove the photoresist. 8 (a) shows the smooth etching front 1 and the photoresist 3 in its place after the hot etching. 8 (b) shows the same smooth surface of the etching front 1 after stripping with an N ₂ + H ₂ plasma to remove the photoresist. There is no visible polymer residue left.

The First order effects of each individual factor can be like will be summarized.

The best process conditions for partially etching a SICOH-type dielectric with a smooth etching front are therefore:
Etching gases: 80 sccm CF ₄ , 40 sccm H ₂ , 400 sccm Ar, 5% variation in CF ₄ and H ₂ would give similar results as long as the ratio of CF ₄ to H _{2 is maintained} at about 2: 1.
Etching process pressure: 200 mTorr
Plasma power: 1000 W at 13.56 MHz applied to the wafer plate (RIE) (The power must be increased with increasing pressure to avoid a "wafer lens effect").
Wafer surface temperature: 100 to 170 ° C (for example, by adjusting the plate temperature and / or the thermal coupling by means of the helium back pressure).

Claims (11)

A method of etching a porous carbon doped silica type thin dielectric layer comprising plasma etching the thin layer in a plasma etching chamber with CF ₄ , H ₂ and a noble gas, wherein the ratio of CF ₄ gas flow to H ₂ gas flow is between 1.33: 1 and 2.7: 1 and the noble gas flow is greater than about 42% of the total gas flow in the plasma chamber. A method according to claim 1, characterized in that the ratio of CF ₄ to H _{2 is} about 2: 1. Method according to claim 1 or 2, characterized that the noble gas is argon. Method according to claim 3, characterized that the argon up to about 77% of the total gas flow in the plasma etching is available. Method according to at least one of the preceding Claims, characterized in that the thin film temperature in the range from 100 ° C up to 170 ° C lies. Method according to at least one of the preceding Claims, characterized in that the chamber pressure in the range of 90 mT to 300 mT. Method according to at least one of the preceding Claims, characterized in that the power supplied to the plasma between 700 and 1,000 watts. Method according to at least one of the preceding Claims, characterized in that the etching within the thin layer is ended. Method according to claim 8, characterized in that that the thin one Layer is arranged within a connection structure. Method according to at least one of claims 1 to 7, characterized in that the plasma etching a connection structure or form another relevant structure in the thin layer. Device with a thin layer, which according to a the previous method claims is etched.