EP0338102A1 - Process for manufacturing semiconductor integrated circuits comprising field effect transistors having submicron channels - Google Patents

Abstract

The invention relates to a process for manufacturing an integrated semiconductor structure having devices with dimensions in the submicrometre region, in which a three-layer resist system is used for producing a polymer or resist mask. The resulting polymer or resist mask is used to etch a layer, for example a polysilicon layer, on the semiconductor substrate. The process is characterised in that the pattern (6), which has been produced in the upper layer of the three-layer resist in conventional manner and which contains an angle of < 90 DEG , is transferred by RIE with CF4 into the plasma nitride centre layer (5) and by RIE with oxygen into the lower resist or polymer layer (4). According to the invention, the plasma nitride mask (5) is first removed, a facetting step is optionally carried out in oxygen to reinforce the positive angle in the mask structure (4) and only then is a lateral etching of the mask structure (4) carried out in oxygen in order to obtain the desired reduction in the dimensions of the mask. <IMAGE>

Description

The invention relates to a method for producing integrated semiconductor structures which contain field effect transistors with channel lengths in the submicron range.

In today's semiconductor technology, it is desirable to obtain line widths in the range of about 0.5 µm using standard photolithography methods and to avoid the use of more complex technologies such as electron or X-ray lithography. Considerable efforts have been made in recent years to develop processes for the manufacture of field effect transistors with channel lengths in the submicron range, while at the same time maintaining very narrow channel length tolerances. Examples of this work are described in U.S. Patents 4,209,349; 4,209,350; 4,234,362; 4,256,514, and 4,502,914. All of these patents describe processes for producing a silicon body with essentially horizontal and essentially vertical surfaces, on which a very thin layer is then deposited. In an anisotropic etching process, for example by reactive ion etching, the layer on the essentially horizontal surface is removed, while the layer on the essentially vertical surface is retained. The dimension of the vertical layer essentially depends on the layer thickness of the layer originally applied.

In this way, an area with very small dimensions can be produced, for example a channel of a field effect transistor with a length in the submicron range.

Another method uses a three-layer resist system to define the gate electrode of a field effect transistor by photo or electron beam lithography. In this method (see, for example, PCT application WO-80/00639), a relatively thick polymer or resist layer is applied as the base to the surface of a polycrystalline silicon layer, which is provided in part as a gate electrode. After a hardening step, an intermediate layer of silicon dioxide or nitride is applied by chemical deposition from the vapor phase. In the top layer, which consists of a highly sensitive positive or negative photoresist, the desired pattern of the gate electrode is produced by optical or electron beam exposure and development. The transfer of the pattern from the upper resist layer into the silicon dioxide or nitride barrier layer takes place by reactive ion etching or plasma etching with CF₄, CHF₃, optionally in a mixture with O₂ and the like, and by reactive ion etching with O₂ the pattern is in the lower polymer or Transfer the resist layer. In this etching step, a relatively high oxygen pressure of approximately 50 to 70 μbar is used in order to achieve a lateral undercut of the silicon dioxide / nitride barrier layer by a desired amount, for example by approximately 0.2 μm on each side. The photoresist bars of the lower layer, which are narrowed compared to the starting line width in the upper resist layer by the lateral undercut, serve as a mask during the subsequent reactive ion etching of the polysilicon.

A disadvantage of this process is its poor uniformity. For example, it has been shown that the base of the photoresist bars is not very precisely defined and that their width on chips differs greatly from the center of the wafer to the edge of the wafer. In addition, the mean, lateral undercut is limited to a certain value by the geometry of the desired structures and the etching rate for the lateral undercut is not constant over time. In addition, the influence of neighboring structures during the etching is increased by the overhang of the silicon dioxide / nitride barrier layer. Another disadvantage of this method is that, due to the barrel-like shape of the photoresist bars, a negative angle is formed in the reactive ion etching into the polysilicon, which increases during the subsequent manufacture of the spacers by deposition and reactive ion etching and the ion implantation of the source and drain regions leads to strong fluctuations in the effective channel lengths of FETs.

The object of the invention is to provide an improved method which uses a three-layer resist for producing a resist or polymer mask and in which the dimensions of the photoresist mask of the upper layer are transferred with great precision into the lower resist or polymer layer and the line widths of the layer by reactive ion etching Resist or polymer mask produced can be narrowed in a defined manner by lateral etching. The resist or polymer mask serves as a mask during the subsequent reactive ion etching of the polysilicon and allows the production of a positive angle in the polysilicon, which is very desirable both for a good definition of the spacers on the polysilicon edges and for the ion implantation.

The object of the invention is achieved by a method according to claim 1.

The invention is described below with reference to the specific description and FIGS. 1 to 4 explained in more detail.

• Fig. 1 eine Dreilagenstruktur zur Herstellung einer Resist- oder Polymermaske;
• Fign. 2A - 2B ein Verfahren nach dem Stand der Technik;
• Fign. 3A - 3F das Verfahren gemäß der Erfindung:
• Fign. 4A - 4F eine Variante des Verfahrens gemäß der Erfindung.

Show it:

• 1 shows a three-layer structure for producing a resist or polymer mask;
• Fig. 2A-2B show a prior art method;
• Fig. 3A-3F the method according to the invention:
• Fig. 4A-4F a variant of the method according to the invention.

The layer structure which is shown in FIG. 1 is the starting point for the method according to the prior art and for the method according to the invention.

To produce the layer structure, an insulating layer (2) is applied to a VLSI substrate (1) made of silicon. This layer can consist of thermally grown silicon dioxide, part of the layer being provided on the substrate as a gate dielectric. The layer may also be composed of silicon dioxide, silicon nitride and the like, for example a combination of silicon dioxide, silicon nitride and silicon dioxide. The silicon dioxide layer is preferably thermally grown in an oxygen or oxygen-water environment at a temperature of approximately 800 ° C.

A silicon nitride layer is usually prepared by chemical vapor deposition using a SiH₄ / NH₃ gas mixture and N₂ as a carrier gas at a temperature of about 800 ° C under atmospheric pressure or under vacuum conditions.

In the layer structure shown in FIG. 1, the insulating layer (2) consists, for example, of silicon dioxide in a layer thickness of approximately 13 nm. The surface conductivity of the P-substrate (1) is in the areas in which field effect transistors are formed, set to a certain threshold Vt by ion implantation.

A polycrystalline silicon layer (3) is then deposited on the entire surface of the silicon dioxide layer (2) using silane in a hydrogen environment, in a temperature range from approximately 600 ° C. to approximately 650 ° C., preferably at a temperature of approximately 625 ° C. The thickness of the deposited polysilicon layer (3) is approximately 400 to 500 nm, preferably 430 nm. The entire surface of the layer (3) is doped by implantation of phosphorus or arsenic, and then the substrates are heated to approximately 900 ° C.

To produce the photoresist or polymer mask, an approximately 1 to about 2 μm thick polymer or resist layer (4) is applied to the surface of the polysilicon layer (3) by spin coating or spraying on, followed by a curing step at about 200 ° C. for about 30 minutes There are numerous materials from which the layer (4) can be made. There can be known positive and negative Photoresist materials, for example the usual phenol-formaldehyde novolak resins, polymethyl methacrylates, polyisoprenes or materials which are described in US Pat. Nos. 3,201,239 and 3,770,433, are used. However, polymer materials that are not photoconductors, e.g. B. polyimides can be used to form the layer (4).

In the method according to the invention, the TNS photoresist, which is described in U.S. Pat. Patent 4,397,937 and is based on a phenolic resin and a bisester of a 1-oxo-2-naphthalenesulfonic acid with an asymmetric primary or secondary aliphatic diol as a sensitizer. The layer thickness is approximately 1.1 µm. The layer (4) is cured under the conditions specified above.

A silicon nitride layer (5) is then applied to the layer (4) as an etching barrier for the reactive ion etching with oxygen in a layer thickness of approximately 0.1 μm. The silicon nitride is deposited by plasma deposition from an atmosphere containing silane, ammonia and argon at a pressure of about 1 mbar, a deposition temperature of about 200 ° C. and an energy density of about 0.05 watt / cm².

A photoresist layer (6) with a thickness of about 0.5 μm to 1.0 μm is applied to the plasma silicon nitride layer (5) as the top layer. In the method according to the invention, the layer consists of the same photoresist as the resist layer (4). However, it can also consist of another photoresist that is highly sensitive to radiation.

In the layer (6) in a method according to the prior art by exposure to a wavelength of 436 nm, followed by a hardening step in nitrogen at a temperature in the range from about 95 to about 105 ° C. for about 30 minutes and development generated the desired mask pattern in aqueous AZ developer based on tetramethylammonium hydroxide.

The pattern of the photoresist mask (6) is then transferred using a dry etching process into the nitride layer (5) and into the resist layer (4), the etching of openings in the silicon nitride layer (5) (FIG. 2A) by plasma etching with CF mit, at a flow of about 20 to 50 sccm, a pressure of about 30 to 60 µbar and an energy density of about 0.3 to 0.5 watt / cm², with about 30% overetching. The end point of the etching is determined by means of laser interference. The layer (5) with the etched openings serves as a mask for etching the resist or polymer layer (4). So far, oxygen with a relatively high pressure of about 50 to 70 μbar has been used for reactive ion etching of this layer in order to achieve a lateral undercut of the silicon nitride layer (5) by a desired amount. In this etching step, the resist layer (4) is anisotropically, ie etched vertically, and at the same time, due to the isotropic proportions of the etching medium, the nitride mask (5) is undercut laterally, which means that in comparison with the starting line width in the upper layer (6) lower layer (4) narrowed photoresist structures can be obtained. During the etching of the layer (4), the resist mask (6) on the nitride mask (5) is also completely removed.

As already described at the beginning, this method has considerable disadvantages with regard to the uniformity of the etching, so that the desired tolerances for the width of the photoresist structures cannot be observed everywhere. Another serious disadvantage is that the barrel-like shape of the photoresist bars, which is obtained when the nitride mask (5) is undercut laterally, is unfavorable for the subsequent etching of the polysilicon layer (3). In reactive ion etching of the polysilicon layer (3) (Fig. 2B), for example with Cl₂ / SF₆ / He, a negative angle is obtained in the polysilicon when using such a photoresist mask, which is undesirable with regard to the properties of the FETs.

Instead of the previously described prior art process, a multi-stage etching process was therefore developed which permits extremely precise control of the lateral etching of the photoresist structures (4) (FIGS. 3 and 4).

The layer structure that is shown in FIG. 1 is assumed. The TNS resist photoresist mask (6) is produced, as indicated above, by conventional exposure and development in a liquid developer. A positive resist angle in a range of approximately 75 to 85 ° is obtained. All dry etching steps can either be carried out in a parallel plate reactor, a plasma etching device or a hexode, for example of the AME 8121 type. The parameters for the individual etching steps depend on the device.

The new method uses the nitride layer (5) (FIGS. 3A, B and 4A, B) only to make an angle of at the locations defined by the photoresist mask (6) (FIGS. 3A, 4A) in the underlying photoresist (4) to etch about 80 to 85 °. The nitride layer (5) is then removed by reactive ion etching. The positive angle of the photoresist structure (4) can be increased by a faceting step in oxygen before the lateral etching of the photoresist structure (4) in oxygen, which is essential for the narrowing, is carried out. In this step, because of the photoresist angle of <90 °, the conditions for reactive ion etching with oxygen can be selected so that a predominantly anisotropic etching takes place, which is more precise than isotropic etching under an overhang of the nitride layer (5) and which is therefore over the etching time is precisely adjustable. The influence of neighboring structures on the lateral etching is also greatly reduced because there is no longer any shadowing nitride.

According to the invention, a lateral etching of the photoresist structure up to a total of approximately 0.75 μm was achieved with a 3 sigma tolerance (sigma = standard deviation) of only approximately ± 0.08 μm over the individual wafer and approximately ± 0.12 μm over the entire lot of 16 wafers, i . H. the tolerance from the beginning of the photolithography of about ± 0.1 µm was hardly increased.

The photoresist mask with angles of <90 ° and the photoresist bars, which were narrowed by a desired amount, was then used for reactive ion etching a pattern with positive angles and the desired line widths is generated in the polysilicon (3), which is very desirable in view of the required properties of the FETs.

In a special exemplary embodiment, the layer structure of FIG. 1 with the photoresist mask (6), which was produced in a conventional manner, is subjected to a series of dry etching steps in an AME 8121 type.

The nitride layer (5) of the layer structure consisting of a 0.8 µm thick photoresist mask (6) on a 0.1 µm thick nitride layer (5), a 1.1 µm thick photoresist layer (4) and a 430 nm thick polysilicon layer (3) is etched under the following conditions ( Fig. 3A):
CF₄ flow: 20 to 50 sccm;
Pressure: 30 to 60 µbar;
Energy density: 0.3 to 0.5 watts / cm²;
with 30% overetch.

The photoresist layer (4) is anisotropically etched under the following conditions (FIG. 3B):
O₂ flow: 40 to 60 sccm;
Pressure: 8 to 12 µbar;
Energy density: 0.2 to 0.4 watts / cm².

Etch stop at a photoresist thickness of about 0.2 µm before the end point.

Then the nitride layer (5) is etched off under the following conditions (FIG. 3C):
CF₄ flow: 20 to 50 sccm;
Pressure: 30 to 60 µbar;
Energy density: 0.3 to 0.5 watts / cm².

At the same time, about 0.1 µm of the photoresist layer (4) is etched off.

If desired, a faceting step is carried out under the following conditions (Fig. 3D):
O₂ flow: 15 to 25 sccm;
Pressure: <1 µbar;
Energy density: 0.2 to 0.4 watts / cm².

The remaining 0.1 µm of the photoresist layer (4) is etched off in this step.

A lateral etching is then carried out to narrow the photoresist structure (4) under the following conditions (FIG. 3E):
O₂ flow: 80 to 120 sccm;
Pressure: 90 to 100 µbar;
Energy density: 0.2 to 0.4 watts / cm².

The duration of this etching step results in the size of the lateral etching. With a duration of about 1.6 minutes, about 0.3 µm are etched off on both sides of the photoresist structure (4).

Finally, using the photoresist mask (4), the polysilicon layer (3) is etched in a parallel plate reactor or in a hexode under the following conditions:
Etching medium: Cl₂ / SF₆ / Hey 7.5 2.5 90 Vol.%; Flow: 35 to 45 sccm;
Pressure: 40 to 60 µbar;
Reduced energy density: 0.05 to 0.1 watt / cm².

Depending on the angle in the photoresist mask (4), an angle of <approximately 90 ° is obtained in the polysilicon layer (3).

In order to demonstrate the high precision of the lateral etching process (FIG. 3E), an attempt was made to show the contribution of photolithography to the 3sigma tolerances in a wafer lot, ie to separate the fluctuations in the output widths of resist structures from the contribution by reactive ion etching. In this experiment, all even numbers of 10 wafers were etched perpendicularly through the nitride layer (5) and the photoresist layer (4) in order to transfer the output widths of the resist structures into the polysilicon (3).

Before the reactive ion etching of the polysilicon (3), all odd numbers were subjected to a lateral etching in oxygen of approximately 0.45 μm. For both part numbers, the 3sigma tolerance obtained was identical with about 0.1 µm. Numerous SEM measurements confirmed that fluctuations in the initial width of the resist structures of 0.1 µm across the individual wafers are almost exclusively due to photolithography and development. This proves that the lateral etching process makes practically no contribution to 3sigma tolerances and that the latter are caused by the aforementioned photolithography and development.

In a further exemplary embodiment (FIGS. 4A to 4F), the individual etching steps were processed fully automatically in succession in a hexode. In this exemplary embodiment, a special faceting step (FIG. 3D in the previous example) was dispensed with before the actual lateral etching. With the fully automatic process, a photoresist structure (4) with almost vertical edges could be produced, the transfer of which into the polysilicon layer (3) results in an edge angle of 90 °. All advantages of the method according to the invention are also obtained in this exemplary embodiment.

Claims (13)

1. Method for producing an integrated semiconductor structure with components with dimensions in the submicron range, in which A) three layers (4, 5, 6) are applied to a semiconductor substrate (1, 2, 3), the lower layer (4) on the surface of the substrate (3) made of a photoresist or polymer material, the next layer (5 ) consist of silicon nitride and the top layer (6) consists of a highly sensitive photoresist; B) creates the desired pattern of a mask in the top layer (6); is transferred by reactive ion etching (RIE) or plasma etching into the silicon nitride layer (5) and into the photoresist or polymer layer (4) and C) the resulting mask in the layer (4) is used for etching the layer (3) of the semiconductor substrate;
characterized in that
Ba) the pattern (6) by RIE or plasma etching in the nitride layer (5) and
Bb) is transferred into the photoresist or polymer layer (4) by RIE with oxygen;
Bc) the nitride layer (5) is removed by RIE or plasma etching;
Bd) the resulting mask (4) is optionally subjected to a faceting step in oxygen and
Be) is reduced in size by a desired amount by lateral etching in oxygen. 2. The method according to claim 1, characterized in that the RIE (steps Ba to Be) is carried out in the same device. 3. The method according to claim 2, characterized in that the RIE is carried out in a parallel plate reactor or in a hexode. 4. The method according to claim 1, characterized in that the nitride layer (5) (steps Ba and Bc) with CF₄ at a gas flow of about 20 to 50 sccm, a pressure of about 30 to 60 µbar and an energy density of about 0.3 to 0.5 Watts / cm² is etched. 5. The method according to claim 1, characterized in that the photoresist or polymer layer (4) in the exposed areas (step Bb) is etched with oxygen at a pressure of <about 12 µbar, whereby in the resist or polymer mask (4) Angles of about 80 to 85 ° can be obtained. 6. The method according to claim 5, characterized in that the photoresist or polymer layer (4) in the exposed areas with O₂ at a gas flow of about 40 to 60 sccm, a pressure of about 8 to 12 µbar and an energy density of about 0.2 to 0.4 watt / cm² is anisotropically etched. 7. The method according to claims 1, 5 and 6, characterized in that
the resist mask or polymer mask (4) is subjected to a faceting step in oxygen at a gas flow of approximately 15 to 25 sccm, a pressure of <approximately 1 μbar and an energy density of approximately 0.2 to 0.4 watts / cm² to reinforce the positive angles. 8. The method according to claim 1, characterized in that the resist or polymer mask (4) after the removal of the nitride layer (5) (step Bc) is laterally etched at an oxygen pressure of about 100 µbar for a certain time (step Be), to reduce their dimensions by a certain amount. 9. The method according to claim 8, characterized in that the resist or polymer mask (4) with O₂ at a gas flow of about 80 to 120 sccm, a pressure of about 90 to 100 µbar and an energy density of about 0.2 to 0.4 watts / cm² is laterally etched. 10. The method according to claim 1, characterized in that the resist or polymer mask (4) is used for etching a structure with angles <about 90 ° in the layer (3) of the semiconductor substrate. 11. The method according to claim 10, characterized in that the layer (3) consists of polysilicon and for RIE the same a mixture of, in volume%, about 6 to 8% SF₆, 2 to 3% Cl₂, the rest helium is used. 12. The method according to one or more of claims 1 to 10, characterized in
that to produce the resist or polymer mask (4) a three-layer resist system from an approximately 1.1 µm thick lower layer of a resist based on phenolic resin and a bisester of a 1-oxo-2-naphthalenesulfonic acid with an asymmetric primary or secondary aliphatic diol as a sensitizer; an approximately 0.1 µm thick plasma nitride layer; and an approximately 0.8 μm thick upper resist layer consisting of the material of the lower layer is used. 13. Application of the method according to claims 1 to 12 for the production of FET's with channel lengths in the submicron range.

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