DE10115291C1 - Dynamic semiconductor memory in personal computer, includes controller which is programmed to refresh memory bank by resetting all word lines and to activate word lines - Google Patents

Abstract

Memory banks (1-4) each including memory cells (115-117), are connected to the same word line (121). A memory element connected to memory bank, stores an address associated with an activated word lines. A controller (6) is programmed to refresh memory bank by resetting all word lines and to activate one of word lines having the address stored in memory element after refreshing. An Independent claim is included for semiconductor memory operating method.

Description

The invention relates to a semiconductor memory with memory banks that include dynamic memory cells; the stores cells are arranged in rows and over a word line controllable; when accessing a memory cell the respective word line activated; a control device tion ensures a refreshing process.

Dynamic semiconductor memories contain memory cells that as is well known, a selection transistor and a memory con include capacitor. The memory cells are in multiple memory arranged benches. One memory bank contains all of them Functional units to access a memory cell perform. The memory banks are independent of one another operated. The memories are within a memory bank cells arranged in rows. All memory cells one Lines can be controlled by a word line. With an act The selection transistors of the Memory cell turned on, so that each Spei Cher capacitor is connected to a bit line. On the Bit line is the stored data value after amplification read-ready available through a sense amplifier.

Due to unavoidable leakage currents in the semiconductor chip the amount of charge stored in the storage capacitor, which represent either a logical "1" or a logical "0" sent, dismantled. The charge content of the memory cell is therefore refresh from time to time. The revival refresh interval is typically 64 milliseconds. The refresh process is for all word lines and the memory cells of a memory connected to it bank the data content after activating the word line  the memory cells in the sense amplifier amplified. Subsequently the amplified level is returned to the memory cell wrote. Finally, the word line is deactivated, so that the selection transistors of the connected Spei cells are blocked.

In system applications with dynamic semiconductor memories, for example in personal computers, is a storage con troller provided as a separate semiconductor chip to the Zu handles to control the dynamic semiconductor memory. Be Save known memory controllers for one of the open ones Memory banks of a controlled semiconductor memory Address of the currently open line. Because during processing of programs or data stored in the semiconductor memory it is highly probable that after subsequent memory accesses to successive memories addresses and thus adjacent memory cells can take place because of the temporary storage of the address of the already active fourth line of a memory bank to access this memory bank are generally accelerated.

In today's system applications, however, there is an effort in that a read access to the semiconductor mostly read larger data blocks and in one fast cache, a so-called cache memory be cached. For example, one is sufficient short loop of a work program completely the dynamic semiconductor memory in the opposite we considerably faster cache and loaded multiple times run through. Even if the subsequent access to the dyna mix semiconductor memory compared to a previous one access to neighboring, spatially adjacent Memory cells done is already so much time through Abar processing the program loop of the working memory that in the meantime a refresh or Operation was required. Because during the refresh process all word lines are traversed without further  Measures the information about the previously accessible, Word line no longer activated on the semiconductor memory available. If the memory controller has the address of the up ago activated word line has to be saved again to be transferred to the semiconductor memory in order to there the to activate the row activated after the refresh process. This is because according to the specification for synchronous working dynamic semiconductor memories, so-called SDRAMs, before a refresh command can be applied to the SDRAM, all memory banks in the preloaded state, so called precharge must be moved all-state, so that all word lines are deactivated and referenced tial. Only if the storage controller corresponds has appropriate registers in which the address of the activated th line has been cached and this address with a corresponding Activate command after a refresh Process for the relevant memory bank to the dynamic Transfers semiconductor memory, then this memory bank and activated the relevant line or word line. On the one hand, this has the disadvantage that the access speed is reduced because on the semiconductor memory itself through the refresh process the information about the open Line is lost and this information from the storage con troller can be retransmitted after the refresh process got to. On the other hand, additional data traffic is generated, the the memory bus in the system and therefore also the Ar speed is affected.

No. 6,175,535 B1 describes a semiconductor memory with memory described banks, the dynamic arranged in rows Have memory cells. The memory cells are row by row can be controlled by one word line each. Each of the memory banks an address register is assigned in which the address of the un Word line previously activated indirectly becomes. With a subsequent memory access, the new one Address compared with the buffered address. When accessing a memory cell on the same word line  is to take place, is the one controlling the access flow Control device switched so that a reset this word line is suppressed and the current Zu Extend handle cycle by a predetermined number of cycles is gert.

The object of the invention is to see a dynami rule semiconductor memory of the type mentioned to improve that memory access is faster can. In particular, the close should by a refresh process the dynamic semiconductor memory is not within reach be affected more than necessary.

According to the invention, this object is achieved by a half lead solved memory comprising: at least two memory banks ke, the dynamic memory cells arranged in rows summarize, the memory cells of a row of a word Line can be controlled and where for access to a Memory cell the word line to which this memory cell is connected, is activated; one each at least two Memory banks assigned first memory element to a to store an address assigned to an activated word line manuals; a controller to perform a refresh process for one of the at least two memory banks perform all the word lines of one memory bank are activated and connect all word lines water memory bank are reset, and to follow up the refreshing process to activate that word line four, whose address is stored in the first storage element is.  

In the dynamic semiconductor memory according to the invention assigned to each memory on the semiconductor memory itself a memory element, expediently a register, provided to temporarily store the address that the currently activated word line is assigned. in principle it is sufficient if the address of the activated memory cell is cached. So far was this information at most in the memory controller? temporarily stored. The the Refresh- Before gear controlling control device sets during the re freshs back all the word lines of a memory bank to then that word line automatically closes again activate, whose address in the regi is saved. In addition, it is useful to have a further memory element assigned to each memory bank,  expediently to be provided as a 1-bit register in which the Activation status of the assigned memory bank saved is.

With a Re. Externally applied to the semiconductor memory The fresh command is the word line for all memory banks gen deactivated and pulled to reference potential (command: Precharge all). Then for all memory banks like At the beginning, the refresh process is explained by each memory bank the memory cells of all rows each because read out line by line, amplified and returned again be written. Then the restoration of the Bank status as before the refresh process for all memories benches. This means that where the so-called open bit of the second memory element assigned to a memory bank was set, the bank is activated as such and also the line is activated whose address in the first of the Memory element associated with memory bank was stored (Command: Activate all with memory recovery object). The functionality for each memory bank includes al so that with an Activate command directed to the bank the Row address is stored in the first memory element and the open bit is set. The bank is now activated marked, as well as a line within this bank. With a precharge command resets the open bit. The The address of the previously activated memory cell remains stored in the first storage element and can be used with the next most Activate command can be reactivated. Compared to the conventional solution involving the memory controller no additional data traffic on the memory bus generated. The on-chip buffering of the open bit and the address of the last activated line ensures white tere automatic and quick recovery of the before Refresh process of the current bank status.

The activation of a word line means that its level is raised so far that the selection transistors on it  connected memory cells switched completely conductive are. The level is usually above that of the outside led supply voltage and is powered by a voltage pump pe generated. As a result, the storage capacitors are the inner memory cells arranged half a row above the full permanently switched selection transistor with one each Bit line connected. A word line that is not activated will connected to reference potential. The reference potential is usually Mas In other applications, the deactivated word line also be associated with a negative potential to si ensure that the selection transistors of the row are full are constantly blocked.

The invention based on the in the drawing illustrated embodiment explained in more detail. The one Zige figure shows a section with rele for the invention Functional units of a dynamic semiconductor memory chers (DRAM).

The DRAM shown in the figure has four memory banks 1 , 2 , 3 , 4 . Each of the memory banks contains a multiplicity of memory cells with all the control logic which enables the memory banks to work independently of one another. Memory bank 1, for example, has three memory cells 115 , 116 , 117 . These memory cells are arranged in one row of the memory bank 1 and all are connected to the same word line 121 . Word line 121 can either be physically a single line or consist of multiple segments and be logically viewed as a word line. Each of the memory cells is constructed identically. For example, the memory cell 115 comprises a selection transistor 119 , which can be driven on the gate side by the word line 121 and is connected to a storage capacitor 120 at one of the connections of the controlled current path. The storage capacitor 120 stores a charge amount corresponding to either a logic "1" or a logic "0". The other connection of the controlled path of the selection transistor 119 is connected to a bit line 120 . To access the memory cell 115 , the word line 121 is activated, so that the selection transistor 119 is turned on and connects the capacitor 120 to the bit line 112 . A sense amplifier 118 amplifies the relatively small level change on bit line 112 . With activation of the word line 121 , the data in all memory cells connected to the word line are thus kept increasingly available in sense amplifiers.

Leakage currents ensure that the amount of charge stored in the storage capacitor 120 is reduced over time. Therefore, a refresh operation is to be carried out, as standard about every 64 milliseconds, by activating the respective word lines for all memory cells of the memory bank 1 one after the other, the data values output by the memory cells on the bit lines are amplified in assigned sense amplifiers and then written back to the memory cells , so that finally the word line is deactivated again and the same as the refresh process is applied to the next line. The word line 121 is driven by a word line driver 111 , which either outputs the activation potential VPP or the reference potential (ground) VSS. The word line driver 111 is in turn controlled by a row decoder 110 , which activates one of the plurality of word lines as a function of a row address supplied to it. The memory cell array comprises further word lines running parallel to the word line or the row of memory cells 115 , 116 , 117 , as well as further bit lines running parallel to the illustrated bit lines 112 , 113 , 114 . The other memory banks are constructed accordingly in order to be able to provide the same functionality.

Commands CMD and addresses ADR are supplied to the semiconductor memory externally via external connections 51 , 52 . A command decoder 5 decodes the commands and causes a control device 6 to supply the functional units concerned in the semiconductor memory with control signals in such a way that the externally applied and decoded command is processed. For example, the control device 6 generates corresponding control signals in order to carry out read or write requests. The environment is of interest here when executing an externally created refresh command. The control device 6 is connected to respective control interfaces 13 , 23 , 33 , 43 associated with the memory banks 1 , 2 , 3 , 4 . Each of the interfaces, for example the interface 13 assigned to memory bank 1 , has two memory elements.

A first memory element or register 131 is used to store the address of the word line that is currently open or activated in the memory bank, e.g. B. to save the address of the word line 121 . A second memory element or register 132 stores whether the memory bank 1 is open or not. One of the word lines is activated during the open state, and all word lines within the memory bank are deactivated during the closed state. The first state is referred to as the Activate state, the last state as the Precharge state. Register 132 stores the so-called open bit. If, for example, the word line 121 is activated in the memory bank 1 and the assigned readers provide the data values of the memory cells 115 , 116 , 117 for access, this state is signaled in the interface 13 in the memory element 132 by a set open bit. the address of word line 121 is also stored in register 131 . This address is used in the row decoder 110 in order to forward the high word line potential VPP to the word line 121 via the driver 111 .

An externally initiated refresh process takes place using the functional units described as follows. The re fresh request is communicated to the semiconductor memory via the connections 51 , 52 and decoded in the command decoder 5 . This instructs the control device 6 to first issue the control signals for a precharge all command. It now who brought all word lines in the precharge state in all memory banks 1 , 2 , 3 , 4 , ie connected to the reference potential VSS. The open bit assigned to the memory banks, e.g. B. stored in register 132 for memory bank 1 is reset. The address of the word line of the respective memory banks opened immediately before the refresh request is created is already stored or is stored on the occasion of the precharge all command, for example in register 131 for memory bank 1 . In a second step of the refresh request, the actual refresh is now carried out within all memory banks as a result of the control commands issued by the control device 6 . Finally, the control sequence 6 for an Activate All command is issued by the control device 6 with restoration of the respective bank status. This means that the open bit is again set for all banks and that word line is automatically activated within the bank, the address of which is stored in the corresponding register, for example in register 131 for memory bank 1 .

The precharge all / refresh / activqte all commands are supplied in the form of respective control signals in parallel to the interface devices 13 , 23 , 33 , 43 .

Through the circuit and control measures described ensures that automatically after a refresh by purely internal measures of the semiconductor memory before Refresh existing bank states can be restored. This has the advantage that a line from a bank is already active fourth and is immediately available for further memory access Available. This is based on the experience that a memory access with high probability again on the same line compared to the previous one  Access to adjacent memory cells takes place. The ar speed of the entire system is determined by this measure took increased. The bank closes through a refresh process status information on the semiconductor memory chip itself not lost more.  

LIST OF REFERENCE NUMBERS

1

.

2

.

3

.

4

memory banks

110

row decoder

111

Word line driver

112

.

113

.

114

bit

115

.

116

.

117

memory cells

118

sense amplifier

119

selection transistor

120

storage capacitor

121

wordline

13

.

23

.

33

.

43

Interface devices

131

.

132

register

5

instruction decoder

51

.

52

connections

6

control device
VPP word line voltage
VSS reference potential
CMD command signals
ADR address signals

Claims (7)

1. A semiconductor memory comprising:
at least two memory banks ( 1 , 2 , 3 , 4 ) comprising dynamic memory cells ( 115 , 116 , 117 ) arranged in rows, the memory cells ( 115 , 116 , 117 ) of a row being controllable by a word line ( 121 ) and the word line ( 121 ) to which this memory cell is connected is activated for access to a memory cell,
each have a first memory element ( 131 ) assigned to the at least two memory banks ( 1 , 2 , 3 , 4 ) in order to store an address assigned to an active fourth word line ( 121 ),
a control device ( 6 ) to carry out a refresh process for one of the at least two memory banks ( 1 , 2 , 3 , 4 ), in which all the word lines of the one memory bank are activated and then all the word lines of this memory bank are reset, and in order to after the refresh process to activate that word line ( 121 ) whose address is stored in the first memory element ( 131 ). 2. Semiconductor memory according to claim 1, characterized in that one of the at least two memory banks ( 1 , 2 , 3 , 4 ) assigned second memory element ( 132 ) is provided to the state that a word line within the respective memory bank is open , to store, and that the control device ( 6 ) is designed to activate the word line ( 121 ), the address of which is stored in the first memory element ( 131 ), and in the second memory element ( 132 ) following the refresh process. set the stated state. 3. Semiconductor memory according to claim 1 or 2, characterized in that the control device ( 6 ) is designed to in dependence on an externally applied to the semiconductor memory control command (CMD, ADR) in one of the at least two memory banks ( 1 , 2nd , 3 , 4 ) first deactivate all word lines, then carry out a refresh for all memory cells of this memory bank and then activate the word line whose address is stored in the first memory element ( 131 ). 4. Semiconductor memory according to one of claims 1 to 3, characterized in that the memory cells ( 115 , 116 , 117 ) have a selection transistor ( 119 ) and a capacitor ( 120 ) connected to the controlled path of the selection transistor ( 119 ), the control connection of the selection transistor ( 119 ) is coupled to one of the word lines ( 121 ). 5. Semiconductor memory according to one of claims 1 to 4, characterized by a word line driver ( 111 ) which is coupled on the output side to one of the word lines ( 121 ) and which is controllable such that an activated word line supplies a high level (VPP) is and a non-activated word line is supplied with a low level, in particular reference potential (VSS). 6. Semiconductor memory according to one of claims 1 to 5, characterized in that the address of an activated word line of each of the memory banks ( 1 , 2 , 3 , 4 ) is stored, that the charge content of all memory cells ( 115 , 116 , 117 ) of the memory banks ( 1 , 2 , 3 , 4 ) is refreshed again and that after the refresh, the word line ( 121 ) assigned to the stored addresses is reactivated within each of the memory banks ( 1 , 2 , 3 , 4 ). 7. A semiconductor memory according to claim 6, characterized in that a first state of a label assigned to a memory bank is stored if a word line ( 121 ) has been activated in the associated memory bank, and that a second state of the label is stored if none Word line is activated in the assigned memory bank, and that after the refresh, the word lines assigned to the stored addresses are activated and the indicator is set from the second to the first state.