DE1093710B - Sending device for the transmitter side of a time-division multiplexed pulse-code remote measuring system - Google Patents

Description

GERMAN

The encoder side of a pulse code telemetry system generally includes an analog value encoder, the converts any physical quantity into an analog current or voltage value, further one Encoder, which converts this analog value into digital characters, and finally a transmission device ', which gives the digital signs on a long-distance line. The encryptor can be an automatic one Step compensator, a mechanical encryptor, a sawtooth encryptor or another be a suitable device. The pulses generated by the encryptor are stored in a memory device, ζ. B. a counting chain, stored and sent over the trunk at an appropriate time. A shift register is normally used for this purpose, which is operated by means of shift pulses supplied by a clock generator sends out the content of the individual stages of the memory device in chronological order. The successive contents of the individual counting levels are assigned different values. In the all- ao Generally, the encryption process and the storage of the encryption pulses require less Time than the transfer of the memory contents to the pipeline.

It is known to use chain circuits of binary elements as a divider for the repetition frequency of a pulse train. It is also known to use a chain of binary elements as a counting chain. A chain circuit of bistable flip-flops ■■■ is also known, which can work either as a binary counter or as a shift register.

In the case of a time-division multiplex telemetry system ^: '·' different measuring points are cyclically scanned by the same "encryption" and transmission devices. It will be readily appreciated that in such a device it is desirable not to suffer any loss of time between storage and transmission on the trunk. Are z. B. storage device and shift register one and the same circuit, then the measured value of a new measuring point can only be recorded when the measured value of the previous measuring point has already been sent. The time that is required for the transmission is therefore lost in the cyclical scanning of the various measuring points.

In the case of a transmitter, this loss of time is used for the transmitter side of a time-division multiplexed pulse-code telemetry system avoided using a digital encoder to convert the analog measured value into a digital value, a counting chain for the temporary storage of the digital value, a shift register for transferring the digital value to the trunk line and a clock for Control of the shift register is equipped and transmitting device

for the transmitter side of a time-division multiplexed pulse-code telemetry system

Applicant:

Siemens & Halske Aktiengesellschaft,

Berlin and Munich,
Munich 2, Witteisbacherplatz 2

Dipl.-Phys. Dieter v. Sanden, Munich-Solln,

and Dipl.-Ing. Joachim Dittmann, Karlsruhe,

have been named as inventors

which is characterized according to the invention in that two identical, alternating from the clock generator as a binary counter and as a shift register switched chain circuits, bistable flip-flops are used. .

While the information content of one binary ^ = counter is still sent over the trunk line after its switchover to a shift register, the reset other binary counters already count the counting impulses of a subsequent measuring point. Between the cyclical Switching to different measuring points does not require any special waiting times.

According to a further development of the invention, the counting, reset and shift pulses can Binary counters are fed via diode gates controlled by the clock generator.

The control of the diode gates as well as the switching of the binary counters can be done by means of switching transistors which are controlled by the clock generator via a flip-flop circuit.

The frequency of the shift pulses for emptying the binary counter can be so much higher than the clock frequency be how the number of levels of binary counters is.

The mode of operation of the invention is explained in more detail using a circuit diagram. This circuit diagram is based on an exemplary embodiment of the invention. The two binary counters each consist of ten individual transistor flip-flops Z ₁ to Z ₁₀ or Z ₁ 'to Z ₁₀ '. They are switched alternately in such a way that one of the counting chains always works as a binary counter and the other as a shift register. the

: - -, 009 649/270

Switching takes place via two transistor switches S ₁ and S ₂ , and transistors Tr ₁ and Tr ₂ of transistor switches S ₁ and S ₀ are used for switching . These two transistors are provided to connect two rectifiers GZ ₁ and Gl _{2 of} the multivibrators Z ₁ to Z ₁₀ or Z ₁ to Z ₁₀ 'to zero potential via a resistor R ₁ , which is the case when Tr ₁ or Tr _{2 are} in the conductive state, or to block the rectifiers with a voltage of - 30 volts, which is the case when Tr ₁ or Tr _{2 are} non-conductive. In the first case, the counting pulses from an encryptor, not shown, whose number of pulses is proportional to the measured value of an analog transmitter, pass through a capacitor C ₁ to one of the first two flip-flops. In the second case, the rectifiers GZ ₁ and GZ _{2 are} blocked. The counting chain can then work as a shift register. The shift pulses arriving on a line 1 via capacitors C ₂ and C ₃ and rectifiers Gl _i and Gl ₅ to the base of the transistors of the multivibrator are used for this purpose. The shift pulses come from a clock generator (not shown). You move the binary numbers stored in the binary counter toggle for each clock pulse by one place to the right, ie up to the next toggle. The transistor switches S ₁ and S ₂ mentioned at the outset are controlled by a clock generator (not shown) via a flip-flop circuit F. The clock frequency of this encoder is 25 Hz in the exemplary embodiment. The pulse repetition frequency of the shift pulses is 250 Hz.

The counting pulses, clock pulses and output by the scrambler reset pulses to the binary counter are applied via diodes gates T _1, T ₂ and T ₃ with the diodes D ₁ to D ₆ to the payer Z ₁ to Z ₁₀ and Z ₁ 'to Z _10'. The diodes of the gates receive their control bias via resistors R ₂ , R ₃ and R ₇ from transistor Tr ₃ of transistor switch S ₁ or via resistors R ₅ , R ₆ and R _t from transistor Tr ₄ of transistor switch S ₂ . Two resistors R ₈ and R ₉ on the individual counting flip-flops are used to generate a bias voltage for the rectifiers Gl ^ and Gl _{5 of} the respective subsequent flip-flop. A rectifier GI ₆ , a capacitor C ₄ and a resistor R ₁₀ in each trigger stage of the dual counter are used to reset the trigger stages to the initial state. They are controlled by the already mentioned reset pulse via the diode gate T ₂ . The switching elements of each of the flip-flops of the two binary counters Z ₁ to Z ₁₀ and Z ₁ 'to Z ₁₀ ', which serve the same tasks in all stages, have the same reference numerals. The output pulses of the dual counters Z ₁ to Z ₁₀ or Z ₁ 'to Z ₁₀ ', which are connected as shift registers, are transmitted via monostable multivibrators AI or M ' and a transformer Ü to the long- distance line L ίο for transmission.

Claims (4)

Patent claims: 1. Sending device for the transmitter side of a time-division multiplexed plus-code telemetry system with a digital encoder for converting the analog measured value into a digital value, a counting chain for temporarily storing the digital value, a shift register for transmitting the digital value to the long-distance line and a clock generator for controlling the shift register, characterized in that two identical ladder circuits of bistable flip-flops are used alternately as binary counters and shift registers by the clock generator. 2. Sending device according to claim 1, characterized in that counting, resetting and shifting pulses are fed to the binary counters via diode gates controlled by the clock generator. 3. Sending device according to claim 1 or 2, characterized in that the control of the Diode gates and the switching of the binary counter through a flip-flop circuit from the clock controlled switching transistors takes place. 4. Transmitting device according to claim 1 and following, characterized in that the repetition frequency of the shift pulses a multiple of the clock frequency by the number of stages of one of the binary counters amounts to. Documents considered: German Auslegeschrift No. 1 059 031; "Pulse and Digital Circuits," Millman and Taub, McGraw Hill Book Corp., 1956, pp. 323-327, and 412/413. 1 sheet of drawings