DE2625626A1 - METHOD FOR CODING AND DECODING ANALOG SIGNALS - Google Patents

Description

INGS »a HUFNAGEL

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LANDV / cHi-ISTfi. S5 GOSO MUNICH 2 TEL. O 89/55 5719

Munich, June 8th 1976 Lawyer sold ten ζ .: 46 - Pat.

Hasler AG, Belpstrasse 23, CH 5000 Bern 14, Switzerland

Method for coding and decoding analog signals

The invention relates to a method for the coding and decoding of analog signals in a transmission method, in which the coded signals are sent to the receiver by means of individually triggerable code telegrams be transmitted.

The triggering of the code telegrams can be made dependent on the signal; if they want to transfer a For long-distance calls, code telegrams identifying the amplitudes of the signal are only transmitted if is spoken. It is an object of the invention

609883/0765

specify a method for coding analog signals, which in said transmission method requires the smallest possible number of bits with a sufficient signal-to-noise ratio.

The invention is characterized in that test time segments largest predetermined duration are formed that by repeated sampling during each test period it is checked whether the change in the analog signal since the beginning of the current test period has exceeded a predetermined positive or negative threshold value that immediately when this occurs a corresponding code telegram is transmitted and the current test period is ended, that at the end of each Test time segment that reaches the specified maximum duration, one that reached at this point in time Change assigned code word is transmitted, and that in the receiver each received code word in a Amplitude change converted back and continuously the Sum of the amplitude changes is formed.

The coding method corresponds to low rates of change of the signal using differential pulse code modulation (DPCM) with lower Sampling frequency and a delta modulation method for high signal change speeds with a high sampling frequency and a very high threshold value.

6098837Ö7S5

The advantages of the method will become apparent from the description of an exemplary embodiment with reference to the figures result. There are shown: FIGS. 1 and 2 diagrams to explain the mode of operation of the coding method. FIG. 3 shows a block circuit of the transmission encoder, FIG. 4 shows a Block diagram of the receiver decoder, Fig. A detailed circuit of the transmitter encoder and 6 is a pulse timing diagram for this circuit.

In Fig. 1, the course of an analog signal z. B. a continuously variable voltage V as a function represented by time. At time t, the voltage has some value V. The following is only

CL '

the voltage change V_ = V - V _{0 is} considered. + V

Jk Gt Γ

and - V let two threshold spanriations be exceeded is detectable. In the example given, the "signal has exceeded the upper threshold at tg and a corresponding code word is then transmitted. The first test period is thus t ... tg. The voltage V is subtracted from V. V goes to

Jv X, JL

Time tg almost on Hull; what remains is the change of V from the moment the threshold value is exceeded until tg.

The longest duration of a test period is on Sampling time periods specified. At the 10 samples

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at times t7 -. tl6 will not exceed a of the two threshold values. At time tl6 the test section is ended, the value V becomes a digital code word converted and transmitted directly or after appropriate conversion. This coding can be linear or non-linear.

The code word generated when the threshold is exceeded is the same as the code word that is received when the Amplitude T is encoded.

As indicated in FIG. 2, the delta coding with a variable transmission rate corresponds to one Coding with a non-linear quantization scale. If the limit value V is exceeded after η scans, corresponds to this on the parallels to the coordinate axis at time t, the sections Vr. This results in a

very favorable signal-to-noise characteristic as a function of on the signal amplitude.

The size of the threshold voltage is made dependent from the one that has elapsed since the beginning of the respective test period Time, the delta coding characteristic can be changed with it. The same result can be

609883/0765

can be achieved by making the intervals between the sampling pulses dependent on the one from the beginning of the test period elapsed time. In the end the threshold voltage can be a function of the transmitted code words. Then through the code word At the end of the test period, the longest duration is the ratio of the analog voltage change to the respective Referred to as the threshold value.

Fig. 3 gives a block diagram of the encoder on the transmitting side. A clock 1 gives continuously Pulses that are sent to all of the circuit block inputs marked CP.

2 is the input for the analog signal, 3 is an analog signal Adding circuit for the pending on lines 2 and 4 Tensions. The voltage on line 4 is the comparison signal of the delta and DPCM modulation, this is kept constant by a capacitor 5 for certain periods of time and at the end of these periods of time can be changed gradually.

The amplitude discriminator 7 is connected to the output line 6 of the adding circuit, which is a Output signal on line 8 emits when the

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The amount of the voltage V on line 6 is greater than the amount of the comparison voltage V. A sign discriminator 9 is also connected to line 6 and emits a signal on output lines 10 and 10a when the voltage on line 6 is positive. The signal on line 10 actuates a switch 11 in such a way that it connects a line 12 with the voltage -V in its rest position and with the voltage + V in the working position.

The signal on line 8 actuates the changeover switch 13 via a logic circuit 17 and line 28, the line 12 in the working position to the input 14 of a charge transfer circuit 15 (charge parcelling unit) connects. The signal on line 8 also has a signal via line 16 at the triggering input of the charge transfer circuit 15 and thus causes the transfer of an amount of charge which is proportional corresponds to the voltage applied to input 14, to capacitor 5. Finally, a signal is sent to the telegram generator 18 given, which causes the transmission of a telegram in which at least one bit is through the output signal of the sign discriminator 9 is determined. So far the circuit corresponds to a delta modulator, which with each cycle either a message "positive change" or a message "negative change" or does not send a message. The telegram output is labeled 19.

609883/0765

In addition to the circuit blocks mentioned, the system contains a DPCM coding device, that is to say one Device for differential pulse code modulation. This consists of a sample and hold circuit (sample and hold circuit), which is connected via the line to an analog / digital converter 22 ", while the input 14 of the charge transfer device 15 via switch 13 to the output 21 of the Sample and hold circuit 20 remains connected. The coding can be linear or non-linear. The last one is on the right edge of the 'Pig. I indicated.

A counter 24 modulo 10 counts the clock pulses of the clock generator 1 and outputs at position 0 (= 10) a signal on its output line 25 from. This signal goes through the logic circuit 17 line 27 and causes circuit 20 to sample the voltage on line 6 on line 21 to be transmitted and kept constant there for a short time, it also causes the conversion of the Analog signal on line 21 into a digital code word by analog-to-digital converter 22, which via Line 23 is transmitted to the telegram generator 18. The switch 13 remains in the rest position, so that the signal on line 16, the transfer of an amount of charge corresponding to the voltage on line 21 to the capacitor 5 effected via the charge transfer circuit 15.

609883/0765

It also initiates the transmission of a telegram by the telegram generator 18.

The line 16 is also provided with a zero position input of the counter 24 connected, so that this after each occurrence of a signal on line 16 from zero begins to count.

In Fig. 4 is the receiving side of the transmission system shown. The telegrams arriving on line 40 are received and controlled by the receiver 41 written into a shift register 42 by a clock signal on line 53 ». The receiver 41 is not described in more detail as it is not part of the invention heard. In the arrangement shown, "the shift register has 42 cells ED for the start bit,

EY for the sign bit and Bl 'B7' for the

Information bits. These correspond to lines AD,

AV, Bl B7 in the transmitter. Depending on the sign bit

the switch 44 is switched over via the amplifier 43 and switches either the voltage -V to the reference input 45 of a digital / analog converter 46 or the voltage + V. The digital / analog converter converts the points on its inputs 47

Bl 'B7 ^{1 of} the shift register 42 received signals

into an analog voltage. ED controls a univibrator 43, which for a predetermined time

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Switch 49 closes and thus the capacitor 50 of the integrating amplifier 51 by one of the analog voltage at the output 52 of the digital / analog converter corresponding step changed.

Was the telegram in the sender due to an overrun the threshold causes + V or -V, so are the bits in points B1-B7 all equal to 1 and a + V or -V corresponding to the output of the digital / analog converter is produced Voltage, depending on the position of switch 44. If the telegram was sent via the analog / digital converter in Transmitter generates, the amount of the output voltage on line 52 is less than V, corresponding to the binary Code word, and the step by which the charge on the capacitor 50 changes, is in the corresponding Mass smaller.

Fig. 5 shows a detailed circuit block diagram of Fig. 3. The adder circuit 3 comprises an operational amplifier 61 with the two input resistors 62 and 63 and the feedback resistor 64. The sample and hold circuit 20 consists of an input operational amplifier 65 and an amplifier 66 with the gain factor 1, which are connected via the switch 61 . At the input of the amplifier 66 is the capacitor 68, which at

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Closing the switch 67 to the output voltage of the amplifier 65 is charged. The switch 67 is opened via an amplifier 69 when on line 27 the signal occurs, which triggers an A / D conversion in converter 22.

This converter is not described in detail, since such circuits are commercially available as integrated circuits are. The same applies to the counter 24.

The charge transfer unit 15 contains an input operational amplifier 70 with an input resistor and a feedback resistor 73. Its output is coupled via a capacitor 74 and a switch 75 to the input of an operational amplifier 76, which is fed back via a capacitor 77. Switch 75 is operated via amplifier 78.

The amplitude discriminator 7 contains an analog comparator 79, whose inputs are on lines 6 and 12 and whose output is state 1, when the signal V_ on line 6 is greater than the voltage on line 12. The output of the comparator 79 is with an input of an EXCLUSIVE-OR gate 80

609883/0765

connected, the other input of which is a sign signal receives over line 10. The state 1 occurs at the output of this EXCLUSIVE OR gate if | Vx | <| Vr | is. This signal sets a flip-flop 81 when the clock signal CP goes from 0 to 1.

The sign discriminator 9 contains an analog comparator 82, one input of which is connected to line 6, the other input of which is connected to ground Flip-flop 83, the entrance gates of which are closed and which therefore cannot be set as long as CP is at 1, and two outputs 10 and 10a.

The signal at output 10 puts switch 11 in the working position when the sign of V is positive is. The output of the comparator 82 is connected via the line 10a to a flip-flop 85, at whose A signal appears at the output, which indicates the sign of the code word to be transmitted.

The reference voltages + V and -V are generated by the reference voltage generator 92 generated. This can also be controlled by the clock generator via the line labeled CP will.

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The logic circuit 17 has the following inputs:

Line signal designation
CP CP clock pulses
8 C Threshold exceeded 25 Z ₀ Counter in zero position

The clock signal CP is delayed by a delay circuit 86 by a fraction of a clock period. That delayed clock signal is denoted by CPV ".

Line Signal Condition Designation

27 E * = C. Z _Q. CPV triggering of the A / D

Converter and hold the sample and hold circuit.

16 A = (C + Z). CPY initiation of the charge transfer and reset the counter

28 P = C. CPV switch to delta

modulation.

AD = (C + Z ₀ ). CP start of transmission.

603883/0785

The lines AD, Bl..B7, AV are connected to the telegram generator not shown in FIG. 5; the Signals occurring on them are used to structure telegrams, and AD delivers the start signal, Bl ... B7 the amplitude identification (lllllll for the largest Amplitude) and AV the sign signal.

Fig. 6 gives the course of the voltages at various Points of the circuit according to FIG. 5 again. A "positive logic" is required: the logic corresponding to state 1 Voltage is greater than that corresponding to the state.

The clock pulses CP of the clock generator 1 are shown on the first line, the same ones on the second line Pulses after passing through the retarder 86, drawn with CPV. The third line gives the positions of the Counter 24. The fourth line is a representation of the course of the voltage V on the line 6; the other lines show the designated signals on the specified lines.

Because of exceeding the upper threshold during the position 3 of the counter 24 flip-flop 81 is set at the beginning of the CP pulse and the signal C on

609883/0765

Line 8 goes to 1. This generates a signal A on line 16 via OR gate 87 and AND gate 89 as soon as CPV begins. A 1 appears at the outputs Bl-. ..B7 _f and at the end of CP also at the output of the XHTD gate 88, which causes the XJ transmission of a code telegram via line AD.

The state of AV was set to 1 by the sign discriminator. C continues to set the switch 13 um, so that when the switch 75 is closed, the + V corresponding amount of charge on the capacitor 77, which corresponds to the capacitor 5 in Fig. 3, transferred will. The signal A resets the counter 24 to its basic position.

This counter now counts the clock pulses and the limit value is still not exceeded. When the counter arrives on Hull, the signal Z goes over line 25, gate 91, line 27, triggers the sample and hold circuit 20 and the A / D converter 22, which transmits a code word to the outputs Bl ... B7. At the end of the * CP pulse, The pulse is emitted via gates 87 and 88 and line AD, which causes the transmission of a code telegram.

609883/0765

Claims (1)

PATENT CLAIMS Method for coding and decoding analog signals in a transmission method, "in which the coded signals are transmitted to the receiver by means of individually triggerable code telegrams, characterized, that test periods of the greatest predetermined duration are formed, that by repeated sampling during each test period it is checked whether the change in the analog signal since the beginning of the current test period has exceeded a predetermined positive or negative threshold value,
that if this occurs, a corresponding immediately Transmit code telegram and the current test period is terminated, that at the end of each test period, the said has reached the greatest duration, a code word assigned to the change achieved at this point in time is transmitted will, and that in the receiver each received code word is converted back into an amplitude change and continuously the Sum of the amplitude changes is formed. 609883/0765 2 · Method according to claim 1, characterized in that that the code word generated when the threshold value is exceeded is the same as the code word which is in an am Telegram generated at the end of a test section would be assigned a change equal to the threshold value. 3. The method according to claim, characterized in that that the threshold value is a time function, the value of which depends on the time since the beginning of the respective test period is dependent. 4. The method according to claim ⁷ , characterized in that that the threshold value is a function of the transmitted code words and that by the code word at the end of a test period the ratio of the change in analog voltage to the respective threshold value is designated. /1
Method according to patent claim, characterized in that the intervals between two successive scans during each test time interval are a function of the time that has elapsed since the start of the test time interval. 609883/0765 6. Device for carrying out the method according to claim I, characterized in the transmitter by a summing circuit (3)> at one input (2) the analog signal and at the other input (4), which is connected to an analog memory arrangement (5), there is a comparison signal which relates to the value of the analog signal at the beginning of the relevant test period ", and at the output (6) of which the change voltage occurs, by a clock (l), which is a Query of the amplitude change causes by an amplitude discriminator (7) which emits a signal when the change voltage is positive or exceeds the negative threshold value, by a sign discriminator (9), which is one of the Emits a signal corresponding to the polarity of the change voltage, by a logic circuit (17) which is connected to the amplitude discriminator and the clock generator and upon receipt of a signal from the amplitude discriminator, the triggering of the exceeding of the threshold value indicating signal on the transmission line and the subtraction of the threshold value from the change quantity causes, and after receiving a predetermined number of clocks without exceeding the threshold value Coding of the change voltage in an analog / digital converter (22), the transmission of one of the change voltage 609883/0765 corresponding coded message and a return controls the change voltage to zero, further characterized in that the receiver is a Receiver triggered by each telegram received is of a known type for differential pulse code modulation. 7 · Use of the procedure for the transmission of analog signals in a messaging system in which each message is provided with an address by the sender and sent to a plurality of recipients is sent and received by the recipient identified by the address will. 609883/0765