DE1085356B - Electrical, binary computing device - Google Patents

Description

GERMAN

The invention relates to an electrical, binary computing device, in particular for serial multiplication Binary counter shown with any factors, with one counting level for each binary digit.

Structure and mode of operation of binary counters with counting levels each consisting of bistable elements has been known for some time. The known Eccles-Jordan circuit, for example, can be used as a bistable element to serve. Such binary counters can also be used to count in other number systems if the output lines of the individual stages are connected to one another accordingly. For example, with a count the four-stage binary counter decade by interrupting the count at the tenth input pulse and the circuit is designed so that the counter starts counting again at the eleventh pulse. As counting pulses one uses so-called trigger pulses, which are derived from square pulses, z. B. by means of Differentiators.

After all counting pulses have been fed to the counting chain, the counter remains in the position it has reached, so that it can be viewed at the same time as a memory for the fed pulses. Such counters can also be designed so that the stored number represents a multiple of the counting pulses supplied; If, for example, the first counting stage is bypassed and the pulses are fed to the second stage, the end result is multiplied by two. The stored number can also be multiplied by 4, 8, 16 etc. by bridging the corresponding counting levels. Intermediate values are also possible, e.g. B. the factor 10, by bridging the first and third stage. Here, however, the problem arises that the carry pulse of the third stage occurs simultaneously with a count pulse and must be processed accordingly.

Attempts have been made to circumvent this difficulty by first storing the transmission pulse in an intermediate element and only feeding it to the next stage when the actual counting pulse has been processed. However, this results in a delay which significantly reduces the counting speed, so that in many cases such counters are therefore unsuitable. The use of delay elements in order to avoid the coincidence of two pulses acting on the same circuit is generally known per se, e.g. B. in adding circuits in which two so-called half adders are connected in series. Since in certain cases an adding pulse and a carry pulse can coincide with these adding circuits, but only one pulse can be processed, one pulse is delayed, ie stored, until the other pulse has been processed; only then is the other impulse released for processing.
In order to avoid the disadvantages of the known counting chains

Applicant:

International

Standard Electric Corporation,
New York, NY (V. St. A.)

Representative: Dipl.-Ing. H. Ciaessen, patent attorney,
Stuttgart-Zuffenhausen, Hellmuth-Hirth-Str. 42

Claimed priority:
Netherlands June 26, 1952

Hans Helmut Adelaar, Antwerp (Belgium),
has been named as the inventor

avoid, it is proposed according to the invention that the individual signal pulses for multiplication can optionally be fed to different counting stages at the same time and that a possible coincidence of signal pulses and carry pulses at the input of a stage is prevented by the fact that between the input of a counting stage and the output of the previous one Counting stage a parallel connection of AND gate and exclusive OR gate (four-pole network D) is arranged in such a way that one input («) with the previous stage, the other input (e) with the signal pulse source, the output (δ) of the exclusive OR gate with the next, the output (d) of the AND gate with the next but one level.

The optional setting of the supply of the input pulses to the various counting levels can be made using a second counting chain can be made by, for example, the stages in the on-state close a corresponding bridging contact. This immediately gives the opportunity to enter this second counting chain store the multiplier and then feed the counting pulses to the first counting chain, the result is then the multiplication of the multiplier stored in the second counting chain with that in the first Counting chain incoming multiplicands.

009 550/184

3 4

If the incoming numbers get stuck in binary decimal α and c and the two output terminals b

are coded, ie each decimal place is binary and d. The input α is with the output of the third

is encrypted, then you can this representation in stage, the input c with the contact A ₁₀ , the output b

convert a pure binary representation if you connect each with the input of the fourth stage and the output d

Decimal place via a special input to the counter 5 via a decoupling rectifier with the input

chain leads up in such a way that one of the fifth stages is connected.

Digit of the counting chain directly the tens digit of the second. The four-pole network works as follows: Is present

and fourth stage and the under the position of the third, terminal α or c (but not both) a signal pulse,

sixth and seventh stage feeds, etc. In this way then this pulse appears at terminal b while

the tens digit becomes ten and the hundred digit io terminal d remains in peace. If there is an impulse at the same time

multiplied by a hundred, which then becomes the pure binary Dar- at the terminals α and c, then this pulse appears

position results. Terminal d, while terminal b remains at rest. The counting

Further details of the invention as well as a few sub-chains now work as follows:

games for those that can be used within the scope of the invention If contact A _{10 is} closed, the first pulse lying on the IN AND circuits and exclusive OR circuits 15 gang A passes to the second stage (2 ¹ ) and is shown below with reference to FIG. 1 to 10, for example, terminal c of the four-pole network. The second stage will be explained in more detail. It shows goes to position 1, and since there is an impulse on terminal c ,

Fig. 1 shows a binary counting stage of a known type, but none at terminal α of the four-pole network appears

Fig. 2 shows a known counting chain with the possibility of this pulse at terminal h and toggles the fourth stage (2 ³ )

Multiply the stored number by ten, 20 to position 1. The stored number is thus 2 ^x -j-2 ³

FIG. 3 shows a counting chain that is modified compared to FIG. 2, == 10.

4 shows a counting chain with a four-pole network according to the second pulse at input terminal A.

of the invention, - the second stage back to position 0, and the third

5 a counting chain according to the invention for multi-level then assumes position 1. The same

plication with any multipliers between 1 and 15, 25 impulse also reaches the terminal δ and brings the

Fig. 6 shows a modified arrangement for converting the fourth stage to position 0, which in turn is stage 5 (2 ⁴ )

from binary-decimal numbers to pure binary representation, to the position 1 tilts. The stored number is thus

7 shows a counting chain according to the invention with an 2 ² + 2 ⁴ = 20.

matching delay elements, the third pulse brings the second and fourth stages

Fig. 8 is a four-pole network with a double triode, 30 again in position 1, and the number stored is

9 and 10 two four-pole networks, each with a triode. 2 ¹ + 2 ² + 2 ³ + 2 * = 30.

Fig. 1 shows a binary counting stage, namely the known. The fourth pulse brings the second stage back in

Eccles-Jordan circuit, the mode of operation of which is known, position 0. A carry pulse is then received

and does not require any further explanation. the third stage, which also tilts to zero, and one

6 shows a carry pulse composed of such stages to the terminal α of the four-pole network

binary counting chain with the possibility of delivering. Since there is a pulse at terminal c at the same time,

multiply stored number by ten. If there is no output pulse at terminal b. Against it

Contact A ₁ closed, then the counting chain works, a pulse appears at terminal d, which is sent directly to the

normal. However, if contact A _{1 is} open and the fifth stage is reached. The fifth stage therefore goes into the

contacts A ₂ and A ₈ are closed, then go back to the zero position _40, and supplies a carry pulse to the

Input terminal A applied pulses to the second and sixth stage (2 ⁵ ), which then correspondingly to position 1

fourth stage of the counting chain. The third stage is through the going. That is, the fourth impulse brings the chain with the

Contact A _{8 separated} from the fourth stage and at stage 4 (2 ³ ) and 6 (2 ⁵ ) in position 1, while the

a special carry memory CC connected. other stages are in the zero position. The chain saves

If there is a carry pulse at the output of 45, the number 2 ³ + 2 ^S = 40.

third stage, then it is stored in the carry-over memory.Each pulse at terminal d acts on the same one, which only then passes this pulse on to the fourth way, like two consecutive pulses at the stage, when the corresponding pulse is sent to terminal b . If the A _r contact comes directly from terminal A to the fourth stage instead of k ₁₀ , it can be counted normally. In this case this is already saved. As can be seen from a 50 all impulses at the terminal α of the quadrupole network factor consideration, the in-works appear given to the terminal b without change,
stored pulses multiplied by a factor of 10. This principle can be generalized in various ways.

Another possibility, the coincidence of the over-mean. Two examples of this are shown in FIG. 5 carrier pulse of the third stage and the pulse from _U nd 6. The arrangement according to FIG. 5, which is to be avoided between three input terminals A , is shown in FIG. 55 consecutive pairs of counting stages each one four in this arrangement is a delay network Del polnetzwerk contains, can be set between the input terminal A and the fourth stage that the number of pulses to be counted with each previous counting chain and delays the number determined directly by the input within the limits of the counting chain multiple incoming pulses in such a way that it cannot be replicated with the. If you close z. B. the contacts h _x carry pulses of the third stage coincide 60 and A ₂ , then the number with 2 ° + 2 ¹ = 3 can be multi-. can. Otherwise this arrangement works like the plicate. A multiplication by 11, ie 2 ° + 2 ¹ + 2 ³ , arrangement of FIG. 2 is achieved by closing the contacts A ₁ , A ₂ and A ₈

Fig. 4 shows an arrangement according to the invention, etc. The contacts A ₁ , A ₂ , A ₄ and A ₈ can be through relays

which are controlled by the delay elements, which in turn are controlled by the successive

Disadvantages are avoided by the four-pole network D, 65 following stages of a second binary counting chain.

which lies between the third and fourth stages and which are controlled, such as in the lower part of FIG. 5

works without delay, is provided. The quadrupole is shown. This arrangement can e.g. B. used

network that the AND and exclusive OR circuit become to multiply two numbers together,

and whose structure includes, in some examples in which the number, which serves as a multiplier, is first to Figs. 8 to 10 is described, the two input has 70 input terminal Mr set and in the lower or

5 6

Stored multiplier counting chain, which are set up accordingly with the cathodes of the tubes, that they have the correct combination of the relays K ₁ , K _2, K ₄ , V ₂ and V ₃ etc. connected, their anodes with the terminal and K ₈ actuated and thus the corresponding contacts men c of the following corresponding four-pole network A ₁ ... k _{s are} closed. Then the number that works are related.

Multiplicand is used, at the input terminal Md mono- 5 delay elements having a delay T are stored ₃ and in this case because of the contacts between the actuated terminal of each Vierpolnetzwerkes and I ₁ .. .k _s d multiplied by the multiplier. If the terminals of the following four-pole network are brought back to the quiescent state, then where T _{3 is} equal to T ₂ minus the delay between the terminals c and d can be this operation with a different multiplier. Is the delay between and multiplicands to be repeated. The result io to terminals α and b equal to the delay between the second operation then appears automatically to that of terminals α and d, then T _{3 is} equal to T ₂ . On the other hand, the result of the first operation is added. T ₂ can be chosen such that it accommodates the delay

Fig. 6 shows an application of the arrangement in Fig. 5 between the terminals α and d . In this for converting decimal numbers into binary numbers. Case is T ₃ = zero, and these corresponding delays-This arrangement has the advantage that pulse trains, the 15 guiding elements can be omitted.

Hundreds, tens and ones of a three-digit number It is clear that between the terminal d of the last

Represent a decimal number, at which terminals H, Z or E four-pole network and the counting chain, no delay can be applied at the same time. Each four-pole network element is required, as there are no units D ₁ , D ₂ , D ₃ , D ₅ and D _{6 that} process any coincidence of pulses after this stage. Otherwise, coincident pulses from the binary stage to 20 are the tubes V ₁ , V ₂ etc. by negative biasing the respective terminal α and blocked directly from the pulse, which is sufficient to arrive at the associated terminal c in the event of a negative Im input line . pulses at the cathode do not allow any pulses to occur at the anode of the tube. The arrangement can be clear from the arrangement shown in Fig. 5, multiplication of a number by a predetermined that each pulse at the terminal Z in Fig. 6 with 2 ¹ -f- 2 ³ 25 multiplier can be set by the grid- = 10 is multiplied and that each pulse at the bias voltage at the corresponding tubes in over-terminal H is multiplied by 2 ² + 2 ⁵ + 2 ⁶ = 100, agreeing with the value of the multiplier to about so that the number stored in the chain the binary is reduced by half the value of the reverse voltage. The equivalent of the tubes V ₁ ... V ₄ represented by the three pulse trains, then serve as contacts k _t ... k _s corresponding to decimal numbers. It is also possible to give the 30 pulses shown in FIG. 5 at the input terminal α to be pulse trains for the individual digits of the decimal number in a pulse shaping stage N in sharp negative pulses one after the other on the converter. reshaped that placed on the cathodes of all tubes

If the arrangement of FIG. 5 is intended to be used for high counting speeds. The tubes, the bias of which can be used accordingly, then result from the reduced, the negative impulses transmitted to the fact difficulties that a pulse applied to the 35 their anodes, while the other tubes blocked terminal c of the four-pole network directly from the input - stay. Due to the delay of the different terminal arrives, the impulses do not come exactly with the carry delay elements at the same time impulse coincides, which arrives from the previous one at the respective terminals α and c of the corresponding stage at terminal α . That can come from a quadrupole network.

small delay between the time of arrival 40 FIGS. 8 to 10 show examples of four-pole networks of the count pulse at the previous stage and that for the facilities described above that occur in the subsequent time of the carry pulse at this stage to be explained in more detail.

result. This difficulty is all the more important, each Fig. 8 shows a network with a double triode V ₂ ,

further back in the counting chain the corresponding four-pole where the grid with the terminals α or c and the network is arranged, since the delay is through 45 both cathodes with the terminal d and via a large the carry pulses in the successive stages cathode resistance Rc added to the negative anode. Even if the pulses at terminals α and c voltage terminal HT are connected. The anodes are not exactly coincident or completely separated from each other by means of equal anode resistances Ra with the positive, there is still a risk that impulses tive anode voltage terminal HT are connected and occur at both terminal b and terminal d . 50 in addition, each anode is via a decoupling Fig. 7 now shows an arrangement which eliminates this difficult rectifier T ₄ or R ₅ with the connection point of the speed when high counting speeds are connected to the voltage divider R ₃ -R ₄ . The terminal b is called for. The pulse input line also shows parts at this connection point via a coupling of a delay chain, the first part of which has a delay capacitor C and at the connection point of the voltage rung T ₁ , the delay between a 55 plate A ₁ -S ₂ -

Input pulse and the carry pulse of a binary The mode of operation is as follows: Usually have

Counter level corresponds. The second and all subsequent terminals α and c have the same potential, so that the same parts have the delay T ₂ , which is the same as the delay between the terminals α and b and c and d of the anode currents in both halves of the double triode can flow. Accordingly, the two anodes of the four-pole network plus the delay between the 60 have the same potential, which is equal to or slightly more positive than the input and output pulses of a binary counter potential of the connection point on the voltage divider. The four-pole network should be constructed in such a way, R ₃ -R ₄ , so that the two rectifiers r _c r _{5 are} normally blocked, so that the delay between α and b is blocked like the references. If there is a negative delay between c and d at terminal α , while there is generally between pulse, then the left half of the double triode α and b or c and d are blocked different delays, while the anode current of the right triode occurs. becomes double its original value.

The input of the delay chain is also connected to the Since the potential of the cathodes is not essentially connected to the cathode of a tube V ₁ , the anode of which has changed on, the anode of the right tube is therefore the input of the first stage of the counting chain. The connection points of the subsequent parts of the delay 70 are sufficiently negative to make the rectifier r _{5 conductive.} This is how the negative impulse becomes

generated at terminal δ, while no pulse occurs at terminal d. The result is the same as if a negative pulse is only applied to terminal c. On the other hand, if there are coincident negative pulses at both terminals α and c, the cathodes become more negative and the anodes more positive. As a result, a negative pulse occurs at terminal d , while no pulse occurs at terminal b , since the rectifiers Ve remain blocked.

Fig. 9 shows a modified four-pole network with only one triode. This arrangement works with positive pulses, but can also easily be set up for negative pulses and works as follows: Assume that the terminals α and c are normally at the potential E ₀ and the tube F ₃ is blocked; from the source with the potential E ₁ (more positive than E ₀ ) a current flows through R ₅ , the rectifiers r _e and r ₇ to the terminals a and c, so that the terminals δ and d also have the potential E ₀ . If a positive pulse arrives at terminal a or c , the potential at terminal δ rises momentarily accordingly, since tube V _{3 is} not conductive, while the potential at terminal d remains unchanged. If pulses arrive at the terminals α and c at the same time, then both rectifiers F ₆ and F _{7 are} blocked, so that a current from the source with potential E ₁ via R ₅ , rectifier r ₈ and resistor R ₆ to the source with potential E. ₀ flows. Therefore a positive pulse appears at the terminal, while the tube F ₃ momentarily draws current and prevents a pulse at the terminal δ.

In the case of the arrangement according to FIG. 4 it should be noted that whenever a pulse occurs at terminal α , a coincident pulse appears at the same time at terminal c . In this case, the exclusive OR circuit as shown in Fig. 10 can be simplified. Here the terminal α is connected directly to the terminal d and to the grid of the normally blocked tube V ₄ , while the terminal c is connected to the anode and the terminal δ via the resistor R _g. If only a positive pulse arrives at terminal c, it also appears at terminal b. However, if there are coincident pulses at terminals α and c, then the pulse from terminal α also appears at terminal d, while pulse b is prevented by the current working of the tube.

Claims (7)

Patent claims: 1. Electrical, binary computing device, in particular for the multiplication of serial represented binary numbers with any factors, each with a counting stage for each binary digit, which supplies a carry pulse for every second input-side pulse, characterized in that the individual signal pulses for multiplication optionally different counting stages simultaneously can be supplied and that a possible coincidence of signal pulses and carry pulses at the input of a stage is prevented by a parallel connection of AND gate and exclusive OR gate (four-pole network D) in the between the input of a counting stage and the output of the preceding counting stage Way is arranged that one input (a) with the previous stage, the other input (c) with the signal pulse source, the output (δ) of the exclusive OR gate with the next, the output (d) of the AND gate with the next but one level is connected. 2. Computing device according to claim 1, characterized in that for the optional simultaneous application of the individual signal pulses to different counting stages, a further binary counting chain with the input (Mr) is provided, in which the multiplier pulse series is stored, and that this counting chain (K ₁ . ..K ₉ ; Jk _{1 ,. .K s} ) is connected to the computing device so that the stored multiplier pulse series connects the corresponding stages of the computing device to the input of the computing device, so that the signal pulses in the computing device are multiplied by this multiplier. 3. Computing device according to claim 1 and 2, characterized in that the digit pulse trains present in binary form of a multi-digit number, each corresponding to a digit of a non-binary number, simultaneously via corresponding inputs (E, Z, H) to the associated counting stages of the computing device Multiplication with its place value are supplied so that the binary equivalent of the said multi-digit number is stored in the arithmetic unit and thus a conversion from one to a binary number system can be carried out. 4. Computing device according to claim 1 to 3, characterized in that between the input (A) and the individual inputs (c) and in the connection from the outputs (d) to the relevant next stage delay _{elements (T 1} .. .T ₃ ) are provided, which are used to compensate for the delays caused by the counting chain compared to the directly supplied pulses. 5. Computing device according to claim 1 to 4, characterized in that the four-pole network (D) contains two triodes (F ₂ ), the cathodes of which are connected to one another, a signal pulse at each of the two control grids momentarily shifting the potential of the cathode to negative values, so that a pulse is applied to the second output terminal (AND gate), while if a signal pulse is applied to one and only one of the two triodes at the control grid, the anode potential of the other momentarily drops, so that the resulting pulse via the assigned diode (F ₄ , F ₅ ) is applied to the first output terminal (exclusive OR gate). 6. Computing device according to claim 1 to 4, characterized in that the four-pole network (D) contains only one triode (F ₃ ) which is blocked when there is no pulse at the inputs (a and c), and that both inputs (a , c) via diodes (r ₉ , r ₁₀ ) with the output (b) and the anode of the triode (F ₃ ) and via diodes (r _e , r ₇ ) with the reverse direction of flow on the one hand with the output (d) and the grid the triode and on the other hand via a common resistor (R ₅ ) are connected to a voltage source (E ₁ ) , so that if a pulse is present at one of the two input terminals (a, c) a pulse is only present at the output (b) and if there is a of input pulses at both input terminals («, c) only one pulse occurs at output (d) . 7. Computing device according to claim 1 to 4, characterized in that the four-pole network contains a triode (F ₄ in Fig. 10), the anode and the two output terminals (δ, d) at the potential of the two input terminals (c, a) be held when there is no signal pulse on the input side, and that switching means are provided which when a signal pulse is applied to one of the two input terminals Increase the potential of the output terminal (δ) momentarily, while if two signals coincide at the two input terminals, the grid of the triode is momentarily more positive, so that the triode becomes conductive and delivers a pulse to the output terminal (d) , while at the same time the application of a pulse to the output terminal (δ) is prevented. 10 Considered publications:
Book by CW Tompkins, JH Wakelin, and WW Stifler, "High-Speed Computing Devices," McGraw Hill Book Comp. Inc., New York-Toronto-London, 1950, pp. 291 ff, 191; Annals of the Computation Laboratory of Harvard University, Vol. 27, 1951, pp. 158-161. 1 sheet of drawings