CN216819815U - Chip reset circuit, chip and electronic equipment - Google Patents

Abstract

The utility model discloses a chip reset circuit, a chip and an electronic device, wherein the chip reset circuit comprises: the first detection unit is used for outputting a first trigger signal when at least one reset signal in the chip is detected to be triggered; a first logic circuit; a second logic circuit; the second detection unit, wherein, when a plurality of chips are cascaded, the first logic circuit receives and outputs the first trigger signal of the chip of the current stage; the second logic circuit receives the first trigger signals output by other chips and outputs second trigger signals; the second detection unit receives the first trigger signal and/or the second trigger signal and resets the chip of the current stage. The utility model can realize the simultaneous reset of all the cascade chips when any chip in the cascade chips triggers the reset, can effectively prevent the problems of system locking and the like caused by untimely synchronization of abnormal events, and has flexible application.

Description

Chip reset circuit, chip and electronic equipment

technical field

The utility model relates to the technical field of chip reset, in particular to a chip reset circuit, a chip and an electronic device.

Background technique

The reset function refers to the recovery function of restoring the chip to the initial configuration and state after the chip is powered on or encountering an abnormal working state, so that the chip starts to work from the initial state.

For a large-size touch display integrated display screen such as a tablet computer, the number of pixels on the display screen is much more than that of the mobile phone display screen, and because the design of the existing mobile phone driver chip is relatively mature, it is possible to combine multiple The driver chips used in mobile phones, such as TDDI (Touch and Display Driver Integration) chips, are designed in cascade to realize the driving of the display screen of the tablet computer, so as to avoid the complicated work and time consumption caused by the redesign.

The touch control circuit in the touch chip of a mobile phone usually has multiple reset sources, such as power-on reset, external IO reset, software reset, internal ESD reset, watchdog reset, abnormal power-off reset and so on. In the case of multi-chip cascade operation, it is generally necessary to realize the simultaneous reset of multiple cascaded chips to ensure the stability of the cascaded driving operation of multiple chips. Therefore, a reset source triggered by any one of the multiple cascaded chips is required. All of them can reset multiple chips working in cascade at the same time, so that the whole system can be restarted.

Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art.

Utility model content

In order to solve the above technical problems, the present invention provides a chip reset circuit, a chip and an electronic device, which can realize simultaneous reset of all cascaded chips when any one of the multiple cascaded chips triggers reset, thereby triggering the system Fast reset can effectively prevent problems such as system stuck due to untimely synchronization of abnormal events, and can flexibly adapt to the application of various cascaded chips.

According to a first aspect of the present disclosure, a chip reset circuit is provided, comprising: a first detection unit that receives at least one reset signal inside the chip and outputs a first trigger signal;

a first logic circuit, comprising a first input end and an output end, the first input end of the first logic circuit is connected to the output end of the first detection unit;

a second logic circuit, including a first input terminal and an output terminal;

The second detection unit includes a first input end and a second input end, the first input end of the second detection unit is connected to the output end of the first detection unit, and the second input end of the second detection unit connected to the output of the second logic circuit,

Wherein, when multiple chips are arranged in cascade, the output end of the first logic circuit is connected to the first input end of the second logic circuit in other cascaded chips; and

The first logic circuit receives and outputs the first trigger signal of the chip at this stage; the second logic circuit receives the first trigger signal output by other chips, and outputs the second trigger signal; the second detection unit Receive the first trigger signal and/or the second trigger signal, and reset the chip at this level.

Optionally, both the first logic circuit and the second logic circuit include at least one of an AND logic circuit, or a logic circuit and a non-logic circuit.

Optionally, the chip reset circuit further includes:

a third detection unit, configured to output a third trigger signal when at least one reset signal trigger from outside the chip is detected; and

The second detection unit further includes a third input terminal, the third input terminal of the second detection unit is connected to the output terminal of the third detection unit, and the second detection unit is used for receiving the first trigger signal, the second trigger signal and the third trigger signal, reset the chip at this level.

Optionally, each of the first detection unit, the second detection unit and the third detection unit includes at least one of an AND logic circuit, or a logic circuit and a non-logic circuit.

Optionally, both the first logic circuit and the second logic circuit further include a second input terminal for receiving a cascading enable signal, and the cascading enable signal is used to simultaneously control the first logic circuit and the output state of the second logic circuit.

Optionally, the first logic circuit further includes a third input terminal for receiving an output enable signal, where the output enable signal is used to control an output state of the first logic circuit.

Optionally, the second logic circuit further includes a third input terminal for receiving an input enable signal, where the input enable signal is used to control the output state of the second logic circuit.

Optionally, the at least one reset signal inside the chip includes at least one of a power-on reset signal, a software reset signal, an ESD reset signal, a watchdog reset signal, and an abnormal power-off reset signal.

According to a second aspect of the present disclosure, a chip is provided, including:

In the above chip reset circuit, the chip reset circuit is used to realize the reset function of the internal circuit of the chip.

Optionally, the chip includes:

The cascade output pin is used to output the first trigger signal of the chip of this stage;

Cascade input pin, used to receive the first trigger signal of other cascaded chips.

Optionally, the chip includes:

At least one external reset pin for receiving at least one reset signal from outside the chip.

According to a third aspect of the present disclosure, there is provided an electronic device, comprising: a display panel; and a plurality of the above chips in cascade, for providing driving and/or touch signals to the display panel.

Optionally, the display panel includes: cathode ray tube display panel, digital light processing display panel, liquid crystal display panel, light emitting diode display panel, organic light emitting diode display panel, quantum dot display panel, Mirco-LED display panel, Mini- LED display panel, field emission display panel, plasma display panel, electrophoretic display panel or electrowetting display panel.

The beneficial effects of the present utility model at least include:

In the chip reset circuit of the embodiment of the present invention, the first logic circuit can output a trigger signal to represent the reset signal of the chip when a chip triggers an internal reset, and the second logic circuit can make one chip receive the reset signal output from other chips, The second detection unit determines whether the chip needs to be reset by detecting the reset signal from the chip and the reset signal from other chips, so that when any one of the multiple cascaded chips triggers the reset, all the cascaded chips can be reset at the same time. Reset, and the number of logic circuits that the signal needs to pass through in this process is small, which can realize the rapid reset of the system, thereby effectively preventing problems such as system stuck due to untimely synchronization of abnormal events.

In a further preferred embodiment, the third detection unit is set to detect the reset signal from outside the chip, which enhances the reset function of the circuit.

In a further preferred embodiment, the output states of the first logic circuit and the second logic circuit can be simultaneously controlled by the cascade enable signal, so that the chip can be freely switched between cascade application scenarios and non-cascading application scenarios, which improves the Flexibility of chip application.

In a further preferred embodiment, the output state of the first logic circuit and/or the second logic circuit can be controlled by the output enable signal and the input enable signal, so that the chip can be used in cascaded application scenarios and non-cascaded application scenarios, And free switching in the bidirectional reset control and the unidirectional reset control further improves the flexibility of the chip application.

It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention.

Description of drawings

1 shows a schematic structural diagram of an electronic device provided according to an embodiment of the present invention;

2 shows a schematic structural diagram of a chip reset circuit inside a chip in a chip cascade application provided according to an embodiment of the present invention;

FIG. 3 shows a schematic diagram of chip pins provided according to an embodiment of the present invention.

Detailed ways

In order to facilitate the understanding of the present utility model, the present utility model will be more fully described below with reference to the related drawings. The preferred embodiments of the present utility model are shown in the accompanying drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough and complete understanding of the present disclosure will be provided.

FIG. 1 shows a schematic structural diagram of an electronic device provided according to an embodiment of the present invention. As shown in FIG. 1 , the electronic device includes a display panel 100 and a plurality of chips 200 . The plurality of chips 200 are connected in cascade, and perform data processing and signal transmission with the display panel 100 in a parallel operation manner.

Exemplarily, the electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large-size screens, such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving. . And when the display panel 100 in the electronic device can be operated by touch, the plurality of chips 200 are used to provide driving and/or touch signals to the display panel 100 .

Optionally, the display panel 100 includes: a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel Display panel, field emission display panel, plasma display panel, electrophoretic display panel or electrowetting display panel.

FIG. 2 shows a schematic structural diagram of a chip reset circuit inside a chip in a chip cascade application provided according to an embodiment of the present invention.

As shown in FIG. 2 , the chip reset circuit includes: a first detection unit 210 , a first logic circuit 220 , a second logic circuit 230 and a second detection unit 240 .

The first detection unit 210 is configured to output a first trigger signal Rst31 when at least one reset signal (eg, Rst11 , Rst12 , . . . , Rst1n ) inside the chip is detected to be triggered. Optionally, the at least one reset signal inside the chip includes but is not limited to at least one of a power-on reset signal, a software reset signal, an ESD reset signal, a watchdog reset signal, and an abnormal power-off reset signal.

Optionally, the first detection unit 210 includes at least one of an AND logic circuit, or a logic circuit and a non-logic circuit. For example, when the reset signals inside the chip are all reset at a low level, the first detection unit 210 can select an AND logic circuit with multiple input terminals, or a combinational logic circuit composed of an OR logic circuit and a non-logic circuit; When the signals are all reset at a high level, the first detection unit 210 can be selected as an OR logic circuit with multiple input terminals, or a combinational logic circuit composed of a logic circuit and a non-logic circuit; when a part of the reset signal inside the chip is a low-level complex. When the other part is reset at a high level, the first detection unit 210 can select an AND logic circuit with multiple input terminals to directly receive a reset signal of a low level reset and a reset signal to receive a high level reset through a non-logic circuit, or select The OR logic circuit with multiple input terminals directly receives the reset signal of the high level reset and the reset signal of the low level reset through the non-logic circuit. Of course, other reasonable combinations of logic circuits can also be selected according to the actual situation, as long as the detection of any reset signal trigger can be realized.

The first logic circuit 220 and the second logic circuit 230 each include a first input terminal and an output terminal, and the second detection unit 240 includes a first input terminal and a second input terminal. The first input terminal of the first logic circuit 220 is connected to the output terminal of the first detection unit 210 in the same chip, and the output terminal of the second logic circuit 230 is connected to the second input terminal of the second detection unit 240 in the same chip. The first input terminal of the second detection unit 240 is connected to the output terminal of the first detection unit 210 in the same chip, and the output terminal of the second detection unit 240 is connected to the reset terminal RST of the internal circuit 260 of the chip. In this embodiment, the internal circuit 260 is a general term for all circuits/modules/units/devices in the chip that need to be reset.

When multiple chips 200 are cascaded, the output terminal of the first logic circuit 220 in each chip is connected to the first input terminal of the second logic circuit 230 in other cascaded chips. At this time, the first logic circuit 220 is configured to output the first trigger signal Rst31 at the output end of the first logic circuit 220 when receiving the first trigger signal Rst31 of the chip of the current stage. The second logic circuit 230 is configured to output a second trigger signal Rst32 when receiving the first trigger signal Rst31 output by other chips. The second detection unit 240 is configured to reset the chip at this level when at least one of the first trigger signal Rst31 and the second trigger signal Rst32 is received.

Optionally, the second detection unit 240 includes at least one of an AND logic circuit, or a logic circuit and a non-logic circuit. For example, when the reset signals inside the chip are all reset at a low level, the second detection unit 240 can select an AND logic circuit with multiple input terminals, or a combinational logic circuit composed of an OR logic circuit and a non-logic circuit; when the reset signal inside the chip is reset When the signals are reset at a high level, the first detection unit 240 can be selected as an OR logic circuit with multiple input terminals, or a combinational logic circuit composed of a logic circuit and a non-logic circuit. Of course, other reasonable combinations of logic circuits can also be selected according to the actual situation, as long as the internal circuit 260 of the chip can be reset when any reset signal is triggered.

In FIG. 2 of the present utility model, the structure of the chip reset circuit is exemplified by taking the reset signal as a low level reset as an example. It can be understood that, based on the connection structure of the first logic circuit 220, the second logic circuit 230 and the second detection unit 240 shown in the present invention, when any one of the multiple cascaded chips is triggered to reset, Simultaneous reset of all cascaded chips is realized, and the number of logic circuits that the signal needs to pass through is small in this process, which can realize the rapid reset of the system, which can effectively prevent the system from being stuck due to untimely synchronization of abnormal events.

Further, both the first logic circuit 220 and the second logic circuit 230 further include a second input terminal for receiving the cascading enable signal CAS, the cascading enable signal CAS is used to control the first logic circuit 220 and the first logic circuit 220 simultaneously. Two output states of the logic circuit 230.

When the chips 200 need to be used in cascade, the cascade enable signal CAS can be set to be in a valid level state (same as the valid reset state of the reset signal), so that the output terminals of the first logic circuit 220 and the output terminals of the second logic circuit 230 are in a valid state. The output level signal can follow the level state of the signal received by its first input terminal, so as to realize the effective transmission of the trigger signal representing the reset signal, that is, when the reset of the chip is triggered, the first logic circuit 220 and the second The level signal output from the output terminal of the logic circuit 230 can trigger the second detection unit 240 in each cascaded chip to reset the internal circuit 260 . When the chip 200 does not need to be used in cascade, the cascade enable signal CAS can be set to be in an invalid level state (opposite to the valid reset state of the reset signal), so that the output terminals of the first logic circuit 220 and the second logic circuit 230 The output level signal is fixed at the level state opposite to the effective reset state of the reset signal, that is, when the reset of the chip is triggered, the level output by the output terminals of the first logic circuit 220 and the second logic circuit 230 The signal will not trigger the second detection unit 240 to reset the internal circuit 260 . In this way, the chip can be freely switched between cascaded application scenarios and non-cascaded application scenarios, which improves the flexibility of chip applications.

Further, the first logic circuit 220 further includes a third input terminal for receiving the output enable signal orst, where the output enable signal orst is used to control the output state of the first logic circuit 220 . And the second logic circuit 230 further includes a third input terminal for receiving the input enable signal irst, the input enable signal irst is used for controlling the output state of the second logic circuit 230 .

When the chips 200 need to be used in cascade, both the output enable signal orst and the input enable signal irst can be set to be in a valid level state (same as the valid reset state of the reset signal, and directly transmitted to the third corresponding or logic circuit). input terminal; or contrary to the effective reset state of the reset signal, it is transmitted to the third input terminal of the corresponding OR logic circuit after passing through the non-logical circuit), so that the output terminal of the first logic circuit 220 and the output terminal of the second logic circuit 230 output power The average signal can follow the level state of the signal received by its respective first input terminal to achieve effective transmission of the trigger signal, that is, the first logic circuit 220 in a certain chip can transmit the reset signal of the chip at this level. to other cascaded chips, and the second logic circuit 230 can also receive reset signals output by other cascaded chips, thereby realizing bidirectional reset control of the cascaded chips. It is also possible to set only one of the output enable signal orst and the input enable signal irst to be in a valid level state, so that the first logic circuit 220 in a certain chip can transmit the reset signal of the chip at this level to other cascaded chips. However, the second logic circuit 230 cannot receive the reset signal output by other cascaded chips, or the first logic circuit 220 cannot transmit the reset signal of the chip of this stage to the other cascaded chips while the second logic circuit 230 can receive the reset signal of other cascaded chips. The reset signal output by the cascaded chip is used to realize the one-way reset control of the cascaded chip. Of course, the output enable signal orst and the input enable signal irst can also be set to be in an invalid level state, and at this time, the same function as when the cascade enable signal CAS is in an invalid level state can be implemented. In this way, the chip can be freely switched between cascaded application scenarios and non-cascaded application scenarios, as well as two-way reset control and mid-one-way reset control, which further improves the flexibility of chip applications.

Optionally, the cascade enable signal CAS, the output enable signal orst and the input enable signal irst can all be provided by a control register inside the chip, but in some embodiments, they can also be provided by other devices outside the chip.

Optionally, both the first logic circuit 220 and the second logic circuit 230 include at least one of an AND logic circuit, or a logic circuit and a non-logic circuit. For example, when the reset signals inside the chip are all low-level resets, as shown in FIG. 2 , both the first logic circuit 220 and the second logic circuit 230 can be selected as OR logic circuits, or formed with logic circuits and non-logic circuits. When the reset signal inside the chip is reset at a high level, the first logic circuit 220 and the second logic circuit 230 can be selected as an AND logic circuit, or a combination logic composed of an AND logic circuit and an OR logic circuit. circuit. Of course, other reasonable combinations of logic circuits can also be selected according to the actual situation. As long as the input signals of the first logic circuit 220 or the second logic circuit 230 are all at the same potential as the reset signal, the chip at this stage can be controlled to output the corresponding trigger. signal.

Further, the chip reset circuit further includes: a third detection unit 250 . The third detection unit 250 is configured to output a third trigger signal Rst33 when at least one reset signal (eg, Rst21, Rst22) from outside the chip is detected to be triggered. At this time, the second detection unit 240 further includes a third input terminal, and the third input terminal of the second detection unit 240 is connected to the output terminal of the third detection unit 250 for receiving the first trigger signal Rst31, When at least one of the second trigger signal Rst32 and the third trigger signal Rst33 is used, the chip at this stage is reset.

It can be understood that, in the present invention, by setting the third detection unit to detect the reset signal from outside the chip, it helps to enhance the diversity of the reset function of the chip reset circuit.

Similar to the first detection unit 210, optionally, the third detection unit 250 includes at least one of an AND logic circuit, or a logic circuit and a non-logic circuit. For example, when the reset signals outside the chip are all low-level resets, the third detection unit 250 can select an AND logic circuit with multiple input terminals, or a combinational logic circuit composed of an OR logic circuit and a non-logic circuit; when the reset signal outside the chip is reset When the signals are all reset at a high level, the third detection unit 250 can be selected as an OR logic circuit with multiple input terminals, or a combinational logic circuit composed of a logic circuit and a non-logic circuit; when a part of the reset signal outside the chip is a low-level complex. When the other part is reset by a high level, the third detection unit 250 can select an AND logic circuit with multiple input terminals to directly receive a reset signal of a low level reset and a reset signal of a high level reset through a non-logic circuit, or select The OR logic circuit with multiple input terminals directly receives the reset signal of the high level reset and the reset signal of the low level reset through the non-logic circuit. Of course, other reasonable combinations of logic circuits can also be selected according to the actual situation, as long as the detection of any reset signal trigger can be realized.

By setting the chip reset circuit composed of two OR logic circuits and corresponding detection units inside the chip, the utility model not only enables the chips to be cascaded by a reset source triggered inside any chip to realize the common operation of all cascaded chips The reset ensures the stability and safety of the cascaded chip as a whole and the controlled device. At the same time, the two OR logic circuits can add unidirectional-bidirectional reset control and cascade-connection to the chip reset circuit without adding other logic circuits. The switching function of non-cascaded reset control improves the application flexibility of the chip, the circuit structure is simple, the number of required logic circuits is small, and the signal transmission delay is low.

It should be noted that the chip reset circuit provided by the embodiment of the present invention is not limited to be arranged in the chip 200 of the electronic device shown in FIG. In order to realize the reset function of the internal circuit of the chip. The present invention does not limit this.

Further, for the chip (IC) 200 provided with the chip reset circuit provided by the embodiment of the present invention, the schematic diagram of the chip pins is shown in FIG. 3 , including: a cascade output pin 1 and a cascade input pin 2 and at least one external reset pin 3. Among them, the cascade output pin 1 is used to output the first trigger signal Rst31 of the chip at this stage; the cascade input pin 2 is used to receive the first trigger signal Rst31 output by other cascade chips; at least one external reset pin 3 is used for for receiving at least one reset signal Rst21 from outside the chip. The chip 200 can realize the simultaneous reset of all the cascaded chips in the cascade application, and at the same time, the function is more powerful and the application is more flexible.

To sum up, in the chip reset circuit of the embodiment of the present invention, the first logic circuit can output a trigger signal to represent the reset signal of the chip when a chip triggers an internal reset, and the second logic circuit can make one chip receive the output from other chips. Reset signal, the second detection unit judges whether the chip needs to be reset by detecting the reset signal from the chip and the reset signal from other chips, and then can realize all cascades when any one of the multiple cascaded chips triggers reset The chip is reset at the same time, and the number of logic circuits that the signal needs to pass through in this process is small, which can realize the rapid reset of the system, thereby effectively preventing problems such as system stuck due to untimely synchronization of abnormal events.

In a further preferred embodiment, the third detection unit is set to detect the reset signal from outside the chip, which enhances the reset function of the circuit.

In a further preferred embodiment, the output states of the first logic circuit and the second logic circuit can be simultaneously controlled by the cascade enable signal, so that the chip can be freely switched between cascade application scenarios and non-cascading application scenarios, which improves the Flexibility of chip application.

In a further preferred embodiment, the output state of the first logic circuit and/or the second logic circuit can be controlled by the output enable signal and the input enable signal, so that the chip can be used in cascaded application scenarios and non-cascaded application scenarios, And free switching in the bidirectional reset control and the unidirectional reset control further improves the flexibility of the chip application.

Finally, it should be noted that: obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (13)

1. a chip reset circuit, is characterized in that, comprises: The first detection unit receives at least one reset signal inside the chip, and outputs a first trigger signal; a first logic circuit, comprising a first input end and an output end, the first input end of the first logic circuit is connected to the output end of the first detection unit; a second logic circuit, including a first input terminal and an output terminal; The second detection unit includes a first input end and a second input end, the first input end of the second detection unit is connected to the output end of the first detection unit, and the second input end of the second detection unit connected to the output of the second logic circuit, Wherein, when multiple chips are arranged in cascade, the output end of the first logic circuit is connected to the first input end of the second logic circuit in other cascaded chips; and The first logic circuit receives and outputs the first trigger signal of the chip at this stage; the second logic circuit receives the first trigger signal output by other chips, and outputs the second trigger signal; the second detection unit The first trigger signal and/or the second trigger signal are received to reset the chip at this stage. 2 . The chip reset circuit according to claim 1 , wherein both the first logic circuit and the second logic circuit further comprise a second input terminal for receiving a cascade enabling signal, and the The connection enable signal is used to control the output states of the first logic circuit and the second logic circuit at the same time. 3 . The chip reset circuit according to claim 1 , wherein the first logic circuit further comprises a third input terminal for receiving an output enable signal, and the output enable signal is used to control the first The output state of a logic circuit. 4 . The chip reset circuit according to claim 1 , wherein the second logic circuit further comprises a third input terminal for receiving an input enable signal, and the input enable signal is used to control the first The output state of the second logic circuit. 5 . The chip reset circuit according to claim 1 , wherein the first logic circuit and the second logic circuit both comprise an AND logic circuit, or a logic circuit and a non-logic circuit. 6 . at least one of. 6. The chip reset circuit according to claim 1, wherein the chip reset circuit further comprises: a third detection unit, configured to output a third trigger signal when at least one reset signal trigger from outside the chip is detected; and The second detection unit further includes a third input terminal, the third input terminal of the second detection unit is connected to the output terminal of the third detection unit, and the second detection unit is used for receiving the first trigger signal, the second trigger signal and the third trigger signal, reset the chip at this level. 7 . The chip reset circuit according to claim 6 , wherein the first detection unit, the second detection unit and the third detection unit all comprise an AND logic circuit, or a logic circuit and a non-logic circuit. 8 . at least one of them. 8. The chip reset circuit according to claim 1, wherein at least one reset signal inside the chip comprises a power-on reset signal, a software reset signal, an ESD reset signal, a watchdog reset signal, and an abnormal power-off reset signal. at least one of. 9. A chip, characterized in that, comprising: The chip reset circuit according to any one of claims 1-8, wherein the chip reset circuit is used to realize the reset function of the internal circuit of the chip. 10. The chip according to claim 9, wherein the chip comprises: The cascade output pin is used to output the first trigger signal of the chip of this stage; Cascade input pin, used to receive the first trigger signal of other cascaded chips. 11. The chip according to claim 10, wherein the chip comprises: At least one external reset pin for receiving at least one reset signal from outside the chip. 12. An electronic device, characterized in that, comprising: display panel; and A plurality of cascaded chips according to any one of claims 9 to 11 are used to provide driving and/or touch signals to the display panel. 13. The electronic device according to claim 12, wherein the display panel comprises: a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum Dot Display Panel, Mirco-LED Display Panel, Mini-LED Display Panel, Field Emission Display Panel, Plasma Display Panel, Electrophoretic Display Panel or Electrowetting Display Panel.

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